spelling
ok jmc@ guenther@ tb@

ansi

Remove get_pc_str_offset(), which has been unused since we switched
to clang, where the stack frame format changed significantly.

Prompted by guenther@ noticing deprecated ASM warnings
ok drahn@

Remove strange /* End of file */ style.

Improve defense against branch predictor target injection (Spectre "variant 2")
attacks. OpenBSD/armv7 is already in pretty good shape as we have always
been flushing the branch predictor cache on context switches. This diff adds
additional flushes to page faults in kernel address space. The impact on
performance should be minimal as these page faults should only happen when
userland (deliberately or accidentally) tries to access kernel addres space
which would lead to a fatal signal (SIGSEGV or SIGBUS).

Loosely based on changes made by Marc Zyngier in Linux and based on
information in Arm Trusted Firmware Security Advisory TFV 6.

Note that for Cortex-A15 (and Cortex-A72) you will need firmware that sets
the ACTRL[0] bit for this diff to be effective. Also note that with this
diff Cortex-A57 is still vulnerable.

ok jsg@

unifdef CPU_ARMv7 and ARM_ARCH_7
ok kettenis@ patrick@

unifdef CPU_XSCALE_PXA2X0, ARM_MMU_XSCALE, ARM_MMU_GENERIC (armv3)
and remove some xscale definitions.

ok kettenis@

Before pmap7.c rev 1.35 and pmap.h rev 1.44 DMA'able memory with the
BUS_DMA_COHERENT flag was mapped as device memory which does not use the
store buffer. It is now mapped as normal inner and outer non-cacheable
which does.

While we drain the cpu store buffer for this case, on cortex a9 systems we
also need to explicitly drain the PL310 L2's store buffer. With PL310
revisions r3p2 and later this is done automatically after being present in
the store buffer for 256 cycles. On i.MX6 PL310 is rev r3p1 which does
not have this behaviour. This issue is i.MX6 errata ERR055199 and PL310
errata 769419.

This change restores io performance with a usb flash drive attached to
my cubox. Raw reads go from 3 MB/s to 19 MB/s for example.

Based on code written by patrick@ some time ago.
ok kettenis@ patrick@

Remove code for Intel 80219/80321 xscale processors used by armish.
Generic xscale support and support for pxa2x0 used by zaurus remains.

Add cpu_auxcontrol() to clear and set bits in the implementation/model
specific Auxiliary Control Register (ACTLR).

ok patrick@

Remove support for ARM11. This was the last unused and unmaintained
processor in our code. Now we're left with only armv7 and XScale for
armish and zaurus.

ok jsg@

Remove support for ARM10.

ok jsg@

Remove support for ARM9E. This is another step in the plan to remove
all unused and unmaintained ARM processors from the past.

ok bmercer@ jsg@

Remove support for the XScale 80200. We don't use it, it didn't compile
and the included headers didn't even exist.

ok jsg@

Remove support for IXP425. This is another architecture that is not
used and has probably never been used at all. Some included headers
do not even exist.

ok jsg@

Remove support for StrongARM (SA1) and IXP12x0. Both are ARMv4 and
are not used by any of the arm platforms.

ok jsg@

Remove support for ARM9T (armv4t). Not used by any of the arm platforms.
From Patrick Wildt.

Remove support for ARM8, an old armv4 processor without thumb that was
never supported by any arm port and wouldn't have built due to a missing
cpufunc_asm_arm8.S file.

From Patrick Wildt.

Switch from PSR_X_bit and X32_bit PSR macro names to just PSR_X.
This matches FreeBSD and makes things a bit more consistent.
Discussed with Patrick.

It's been a quarter century: we can assume volatile is present with that name.

ok dlg@ mpi@ deraadt@

Add a function to read the ARM MPCore base address. This let's us
dynamically determine where e.g. the interrupt controller is.

ok bmercer@

Remove duplicate prototypes.

Add prototypes for secondary cache operations.

ok miod@

Use different setup functions for ARM9E and ARM10 to fix an undefined
instruction fault on ARM9E caused by a coprocessor call.

ok miod@

Add instruction fault register functions, which will be needed for further
ARMv7 support.

ok miod@

Late spring cleaning of the arm code for old dusty bits we do not want to
keep:
- remove bootconfig parameter passing feature (unused).
- unifdef __PROG32 and remove all remains of arm26 code.
- remove ARMFPE support (unused).
- remove support for ARM2, ARM2AS, ARM3, ARM6, ARM7, ARM7TDMI and StrongARM
processor families, and the related silicon bug workarounds (especially
the SA-110 STM^ bug).
- remove cpu_functions no longer necessary after previous removals.
- remove ARM32_DISABLE_ALIGNMENT_FAULTS option (unused).
- make FIQ support conditional on option FIQ (unused, but may be eventually).

Discussed with drahn@ and jasper@ long ago, I was sitting on this commit for
no good reason.

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

Whitespace cleanup on generated asm code, so it is readable.

Pieces of arm11 and armv7 support for newer cpus. This is work in progress
and not complete.

add support for arm9e core, taken from NetBSD.
ok drahn@

cf_context_switch takes an u_int argument.

ok drahn@

Turn GetCPSR() into an inline get_cpsr(), and remove more dead code.

de __P of sys/arch/arm.

branches: 1.1.2;
Arm port, NetBSD codebase stripped down, 32bit only support.

ansi

Remove get_pc_str_offset(), which has been unused since we switched
to clang, where the stack frame format changed significantly.

Prompted by guenther@ noticing deprecated ASM warnings
ok drahn@

Remove strange /* End of file */ style.

Improve defense against branch predictor target injection (Spectre "variant 2")
attacks. OpenBSD/armv7 is already in pretty good shape as we have always
been flushing the branch predictor cache on context switches. This diff adds
additional flushes to page faults in kernel address space. The impact on
performance should be minimal as these page faults should only happen when
userland (deliberately or accidentally) tries to access kernel addres space
which would lead to a fatal signal (SIGSEGV or SIGBUS).

Loosely based on changes made by Marc Zyngier in Linux and based on
information in Arm Trusted Firmware Security Advisory TFV 6.

Note that for Cortex-A15 (and Cortex-A72) you will need firmware that sets
the ACTRL[0] bit for this diff to be effective. Also note that with this
diff Cortex-A57 is still vulnerable.

ok jsg@

unifdef CPU_ARMv7 and ARM_ARCH_7
ok kettenis@ patrick@

unifdef CPU_XSCALE_PXA2X0, ARM_MMU_XSCALE, ARM_MMU_GENERIC (armv3)
and remove some xscale definitions.

ok kettenis@

Before pmap7.c rev 1.35 and pmap.h rev 1.44 DMA'able memory with the
BUS_DMA_COHERENT flag was mapped as device memory which does not use the
store buffer. It is now mapped as normal inner and outer non-cacheable
which does.

While we drain the cpu store buffer for this case, on cortex a9 systems we
also need to explicitly drain the PL310 L2's store buffer. With PL310
revisions r3p2 and later this is done automatically after being present in
the store buffer for 256 cycles. On i.MX6 PL310 is rev r3p1 which does
not have this behaviour. This issue is i.MX6 errata ERR055199 and PL310
errata 769419.

This change restores io performance with a usb flash drive attached to
my cubox. Raw reads go from 3 MB/s to 19 MB/s for example.

Based on code written by patrick@ some time ago.
ok kettenis@ patrick@

Remove code for Intel 80219/80321 xscale processors used by armish.
Generic xscale support and support for pxa2x0 used by zaurus remains.

Add cpu_auxcontrol() to clear and set bits in the implementation/model
specific Auxiliary Control Register (ACTLR).

ok patrick@

Remove support for ARM11. This was the last unused and unmaintained
processor in our code. Now we're left with only armv7 and XScale for
armish and zaurus.

ok jsg@

Remove support for ARM10.

ok jsg@

Remove support for ARM9E. This is another step in the plan to remove
all unused and unmaintained ARM processors from the past.

ok bmercer@ jsg@

Remove support for the XScale 80200. We don't use it, it didn't compile
and the included headers didn't even exist.

ok jsg@

Remove support for IXP425. This is another architecture that is not
used and has probably never been used at all. Some included headers
do not even exist.

ok jsg@

Remove support for StrongARM (SA1) and IXP12x0. Both are ARMv4 and
are not used by any of the arm platforms.

ok jsg@

Remove support for ARM9T (armv4t). Not used by any of the arm platforms.
From Patrick Wildt.

Remove support for ARM8, an old armv4 processor without thumb that was
never supported by any arm port and wouldn't have built due to a missing
cpufunc_asm_arm8.S file.

From Patrick Wildt.

Switch from PSR_X_bit and X32_bit PSR macro names to just PSR_X.
This matches FreeBSD and makes things a bit more consistent.
Discussed with Patrick.

It's been a quarter century: we can assume volatile is present with that name.

ok dlg@ mpi@ deraadt@

Add a function to read the ARM MPCore base address. This let's us
dynamically determine where e.g. the interrupt controller is.

ok bmercer@

Remove duplicate prototypes.

Add prototypes for secondary cache operations.

ok miod@

Use different setup functions for ARM9E and ARM10 to fix an undefined
instruction fault on ARM9E caused by a coprocessor call.

ok miod@

Add instruction fault register functions, which will be needed for further
ARMv7 support.

ok miod@

Late spring cleaning of the arm code for old dusty bits we do not want to
keep:
- remove bootconfig parameter passing feature (unused).
- unifdef __PROG32 and remove all remains of arm26 code.
- remove ARMFPE support (unused).
- remove support for ARM2, ARM2AS, ARM3, ARM6, ARM7, ARM7TDMI and StrongARM
processor families, and the related silicon bug workarounds (especially
the SA-110 STM^ bug).
- remove cpu_functions no longer necessary after previous removals.
- remove ARM32_DISABLE_ALIGNMENT_FAULTS option (unused).
- make FIQ support conditional on option FIQ (unused, but may be eventually).

Discussed with drahn@ and jasper@ long ago, I was sitting on this commit for
no good reason.

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

Whitespace cleanup on generated asm code, so it is readable.

Pieces of arm11 and armv7 support for newer cpus. This is work in progress
and not complete.

add support for arm9e core, taken from NetBSD.
ok drahn@

cf_context_switch takes an u_int argument.

ok drahn@

Turn GetCPSR() into an inline get_cpsr(), and remove more dead code.

de __P of sys/arch/arm.

branches: 1.1.2;
Arm port, NetBSD codebase stripped down, 32bit only support.

Remove get_pc_str_offset(), which has been unused since we switched
to clang, where the stack frame format changed significantly.

Prompted by guenther@ noticing deprecated ASM warnings
ok drahn@

Remove strange /* End of file */ style.

Improve defense against branch predictor target injection (Spectre "variant 2")
attacks. OpenBSD/armv7 is already in pretty good shape as we have always
been flushing the branch predictor cache on context switches. This diff adds
additional flushes to page faults in kernel address space. The impact on
performance should be minimal as these page faults should only happen when
userland (deliberately or accidentally) tries to access kernel addres space
which would lead to a fatal signal (SIGSEGV or SIGBUS).

Loosely based on changes made by Marc Zyngier in Linux and based on
information in Arm Trusted Firmware Security Advisory TFV 6.

Note that for Cortex-A15 (and Cortex-A72) you will need firmware that sets
the ACTRL[0] bit for this diff to be effective. Also note that with this
diff Cortex-A57 is still vulnerable.

ok jsg@

unifdef CPU_ARMv7 and ARM_ARCH_7
ok kettenis@ patrick@

unifdef CPU_XSCALE_PXA2X0, ARM_MMU_XSCALE, ARM_MMU_GENERIC (armv3)
and remove some xscale definitions.

ok kettenis@

Before pmap7.c rev 1.35 and pmap.h rev 1.44 DMA'able memory with the
BUS_DMA_COHERENT flag was mapped as device memory which does not use the
store buffer. It is now mapped as normal inner and outer non-cacheable
which does.

While we drain the cpu store buffer for this case, on cortex a9 systems we
also need to explicitly drain the PL310 L2's store buffer. With PL310
revisions r3p2 and later this is done automatically after being present in
the store buffer for 256 cycles. On i.MX6 PL310 is rev r3p1 which does
not have this behaviour. This issue is i.MX6 errata ERR055199 and PL310
errata 769419.

This change restores io performance with a usb flash drive attached to
my cubox. Raw reads go from 3 MB/s to 19 MB/s for example.

Based on code written by patrick@ some time ago.
ok kettenis@ patrick@

Remove code for Intel 80219/80321 xscale processors used by armish.
Generic xscale support and support for pxa2x0 used by zaurus remains.

Add cpu_auxcontrol() to clear and set bits in the implementation/model
specific Auxiliary Control Register (ACTLR).

ok patrick@

Remove support for ARM11. This was the last unused and unmaintained
processor in our code. Now we're left with only armv7 and XScale for
armish and zaurus.

ok jsg@

Remove support for ARM10.

ok jsg@

Remove support for ARM9E. This is another step in the plan to remove
all unused and unmaintained ARM processors from the past.

ok bmercer@ jsg@

Remove support for the XScale 80200. We don't use it, it didn't compile
and the included headers didn't even exist.

ok jsg@

Remove support for IXP425. This is another architecture that is not
used and has probably never been used at all. Some included headers
do not even exist.

ok jsg@

Remove support for StrongARM (SA1) and IXP12x0. Both are ARMv4 and
are not used by any of the arm platforms.

ok jsg@

Remove support for ARM9T (armv4t). Not used by any of the arm platforms.
From Patrick Wildt.

Remove support for ARM8, an old armv4 processor without thumb that was
never supported by any arm port and wouldn't have built due to a missing
cpufunc_asm_arm8.S file.

From Patrick Wildt.

Switch from PSR_X_bit and X32_bit PSR macro names to just PSR_X.
This matches FreeBSD and makes things a bit more consistent.
Discussed with Patrick.

It's been a quarter century: we can assume volatile is present with that name.

ok dlg@ mpi@ deraadt@

Add a function to read the ARM MPCore base address. This let's us
dynamically determine where e.g. the interrupt controller is.

ok bmercer@

Remove duplicate prototypes.

Add prototypes for secondary cache operations.

ok miod@

Use different setup functions for ARM9E and ARM10 to fix an undefined
instruction fault on ARM9E caused by a coprocessor call.

ok miod@

Add instruction fault register functions, which will be needed for further
ARMv7 support.

ok miod@

Late spring cleaning of the arm code for old dusty bits we do not want to
keep:
- remove bootconfig parameter passing feature (unused).
- unifdef __PROG32 and remove all remains of arm26 code.
- remove ARMFPE support (unused).
- remove support for ARM2, ARM2AS, ARM3, ARM6, ARM7, ARM7TDMI and StrongARM
processor families, and the related silicon bug workarounds (especially
the SA-110 STM^ bug).
- remove cpu_functions no longer necessary after previous removals.
- remove ARM32_DISABLE_ALIGNMENT_FAULTS option (unused).
- make FIQ support conditional on option FIQ (unused, but may be eventually).

Discussed with drahn@ and jasper@ long ago, I was sitting on this commit for
no good reason.

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

Whitespace cleanup on generated asm code, so it is readable.

Pieces of arm11 and armv7 support for newer cpus. This is work in progress
and not complete.

add support for arm9e core, taken from NetBSD.
ok drahn@

cf_context_switch takes an u_int argument.

ok drahn@

Turn GetCPSR() into an inline get_cpsr(), and remove more dead code.

de __P of sys/arch/arm.

branches: 1.1.2;
Arm port, NetBSD codebase stripped down, 32bit only support.

Remove strange /* End of file */ style.

Improve defense against branch predictor target injection (Spectre "variant 2")
attacks. OpenBSD/armv7 is already in pretty good shape as we have always
been flushing the branch predictor cache on context switches. This diff adds
additional flushes to page faults in kernel address space. The impact on
performance should be minimal as these page faults should only happen when
userland (deliberately or accidentally) tries to access kernel addres space
which would lead to a fatal signal (SIGSEGV or SIGBUS).

Loosely based on changes made by Marc Zyngier in Linux and based on
information in Arm Trusted Firmware Security Advisory TFV 6.

Note that for Cortex-A15 (and Cortex-A72) you will need firmware that sets
the ACTRL[0] bit for this diff to be effective. Also note that with this
diff Cortex-A57 is still vulnerable.

ok jsg@

unifdef CPU_ARMv7 and ARM_ARCH_7
ok kettenis@ patrick@

unifdef CPU_XSCALE_PXA2X0, ARM_MMU_XSCALE, ARM_MMU_GENERIC (armv3)
and remove some xscale definitions.

ok kettenis@

Before pmap7.c rev 1.35 and pmap.h rev 1.44 DMA'able memory with the
BUS_DMA_COHERENT flag was mapped as device memory which does not use the
store buffer. It is now mapped as normal inner and outer non-cacheable
which does.

While we drain the cpu store buffer for this case, on cortex a9 systems we
also need to explicitly drain the PL310 L2's store buffer. With PL310
revisions r3p2 and later this is done automatically after being present in
the store buffer for 256 cycles. On i.MX6 PL310 is rev r3p1 which does
not have this behaviour. This issue is i.MX6 errata ERR055199 and PL310
errata 769419.

This change restores io performance with a usb flash drive attached to
my cubox. Raw reads go from 3 MB/s to 19 MB/s for example.

Based on code written by patrick@ some time ago.
ok kettenis@ patrick@

Remove code for Intel 80219/80321 xscale processors used by armish.
Generic xscale support and support for pxa2x0 used by zaurus remains.

Add cpu_auxcontrol() to clear and set bits in the implementation/model
specific Auxiliary Control Register (ACTLR).

ok patrick@

Remove support for ARM11. This was the last unused and unmaintained
processor in our code. Now we're left with only armv7 and XScale for
armish and zaurus.

ok jsg@

Remove support for ARM10.

ok jsg@

Remove support for ARM9E. This is another step in the plan to remove
all unused and unmaintained ARM processors from the past.

ok bmercer@ jsg@

Remove support for the XScale 80200. We don't use it, it didn't compile
and the included headers didn't even exist.

ok jsg@

Remove support for IXP425. This is another architecture that is not
used and has probably never been used at all. Some included headers
do not even exist.

ok jsg@

Remove support for StrongARM (SA1) and IXP12x0. Both are ARMv4 and
are not used by any of the arm platforms.

ok jsg@

Remove support for ARM9T (armv4t). Not used by any of the arm platforms.
From Patrick Wildt.

Remove support for ARM8, an old armv4 processor without thumb that was
never supported by any arm port and wouldn't have built due to a missing
cpufunc_asm_arm8.S file.

From Patrick Wildt.

Switch from PSR_X_bit and X32_bit PSR macro names to just PSR_X.
This matches FreeBSD and makes things a bit more consistent.
Discussed with Patrick.

It's been a quarter century: we can assume volatile is present with that name.

ok dlg@ mpi@ deraadt@

Add a function to read the ARM MPCore base address. This let's us
dynamically determine where e.g. the interrupt controller is.

ok bmercer@

Remove duplicate prototypes.

Add prototypes for secondary cache operations.

ok miod@

Use different setup functions for ARM9E and ARM10 to fix an undefined
instruction fault on ARM9E caused by a coprocessor call.

ok miod@

Add instruction fault register functions, which will be needed for further
ARMv7 support.

ok miod@

Late spring cleaning of the arm code for old dusty bits we do not want to
keep:
- remove bootconfig parameter passing feature (unused).
- unifdef __PROG32 and remove all remains of arm26 code.
- remove ARMFPE support (unused).
- remove support for ARM2, ARM2AS, ARM3, ARM6, ARM7, ARM7TDMI and StrongARM
processor families, and the related silicon bug workarounds (especially
the SA-110 STM^ bug).
- remove cpu_functions no longer necessary after previous removals.
- remove ARM32_DISABLE_ALIGNMENT_FAULTS option (unused).
- make FIQ support conditional on option FIQ (unused, but may be eventually).

Discussed with drahn@ and jasper@ long ago, I was sitting on this commit for
no good reason.

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

Whitespace cleanup on generated asm code, so it is readable.

Pieces of arm11 and armv7 support for newer cpus. This is work in progress
and not complete.

add support for arm9e core, taken from NetBSD.
ok drahn@

cf_context_switch takes an u_int argument.

ok drahn@

Turn GetCPSR() into an inline get_cpsr(), and remove more dead code.

de __P of sys/arch/arm.

branches: 1.1.2;
Arm port, NetBSD codebase stripped down, 32bit only support.

Improve defense against branch predictor target injection (Spectre "variant 2")
attacks. OpenBSD/armv7 is already in pretty good shape as we have always
been flushing the branch predictor cache on context switches. This diff adds
additional flushes to page faults in kernel address space. The impact on
performance should be minimal as these page faults should only happen when
userland (deliberately or accidentally) tries to access kernel addres space
which would lead to a fatal signal (SIGSEGV or SIGBUS).

Loosely based on changes made by Marc Zyngier in Linux and based on
information in Arm Trusted Firmware Security Advisory TFV 6.

Note that for Cortex-A15 (and Cortex-A72) you will need firmware that sets
the ACTRL[0] bit for this diff to be effective. Also note that with this
diff Cortex-A57 is still vulnerable.

ok jsg@

unifdef CPU_ARMv7 and ARM_ARCH_7
ok kettenis@ patrick@

unifdef CPU_XSCALE_PXA2X0, ARM_MMU_XSCALE, ARM_MMU_GENERIC (armv3)
and remove some xscale definitions.

ok kettenis@

Before pmap7.c rev 1.35 and pmap.h rev 1.44 DMA'able memory with the
BUS_DMA_COHERENT flag was mapped as device memory which does not use the
store buffer. It is now mapped as normal inner and outer non-cacheable
which does.

While we drain the cpu store buffer for this case, on cortex a9 systems we
also need to explicitly drain the PL310 L2's store buffer. With PL310
revisions r3p2 and later this is done automatically after being present in
the store buffer for 256 cycles. On i.MX6 PL310 is rev r3p1 which does
not have this behaviour. This issue is i.MX6 errata ERR055199 and PL310
errata 769419.

This change restores io performance with a usb flash drive attached to
my cubox. Raw reads go from 3 MB/s to 19 MB/s for example.

Based on code written by patrick@ some time ago.
ok kettenis@ patrick@

Remove code for Intel 80219/80321 xscale processors used by armish.
Generic xscale support and support for pxa2x0 used by zaurus remains.

Add cpu_auxcontrol() to clear and set bits in the implementation/model
specific Auxiliary Control Register (ACTLR).

ok patrick@

Remove support for ARM11. This was the last unused and unmaintained
processor in our code. Now we're left with only armv7 and XScale for
armish and zaurus.

ok jsg@

Remove support for ARM10.

ok jsg@

Remove support for ARM9E. This is another step in the plan to remove
all unused and unmaintained ARM processors from the past.

ok bmercer@ jsg@

Remove support for the XScale 80200. We don't use it, it didn't compile
and the included headers didn't even exist.

ok jsg@

Remove support for IXP425. This is another architecture that is not
used and has probably never been used at all. Some included headers
do not even exist.

ok jsg@

Remove support for StrongARM (SA1) and IXP12x0. Both are ARMv4 and
are not used by any of the arm platforms.

ok jsg@

Remove support for ARM9T (armv4t). Not used by any of the arm platforms.
From Patrick Wildt.

Remove support for ARM8, an old armv4 processor without thumb that was
never supported by any arm port and wouldn't have built due to a missing
cpufunc_asm_arm8.S file.

From Patrick Wildt.

Switch from PSR_X_bit and X32_bit PSR macro names to just PSR_X.
This matches FreeBSD and makes things a bit more consistent.
Discussed with Patrick.

It's been a quarter century: we can assume volatile is present with that name.

ok dlg@ mpi@ deraadt@

Add a function to read the ARM MPCore base address. This let's us
dynamically determine where e.g. the interrupt controller is.

ok bmercer@

Remove duplicate prototypes.

Add prototypes for secondary cache operations.

ok miod@

Use different setup functions for ARM9E and ARM10 to fix an undefined
instruction fault on ARM9E caused by a coprocessor call.

ok miod@

Add instruction fault register functions, which will be needed for further
ARMv7 support.

ok miod@

Late spring cleaning of the arm code for old dusty bits we do not want to
keep:
- remove bootconfig parameter passing feature (unused).
- unifdef __PROG32 and remove all remains of arm26 code.
- remove ARMFPE support (unused).
- remove support for ARM2, ARM2AS, ARM3, ARM6, ARM7, ARM7TDMI and StrongARM
processor families, and the related silicon bug workarounds (especially
the SA-110 STM^ bug).
- remove cpu_functions no longer necessary after previous removals.
- remove ARM32_DISABLE_ALIGNMENT_FAULTS option (unused).
- make FIQ support conditional on option FIQ (unused, but may be eventually).

Discussed with drahn@ and jasper@ long ago, I was sitting on this commit for
no good reason.

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

Whitespace cleanup on generated asm code, so it is readable.

Pieces of arm11 and armv7 support for newer cpus. This is work in progress
and not complete.

add support for arm9e core, taken from NetBSD.
ok drahn@

cf_context_switch takes an u_int argument.

ok drahn@

Turn GetCPSR() into an inline get_cpsr(), and remove more dead code.

de __P of sys/arch/arm.

branches: 1.1.2;
Arm port, NetBSD codebase stripped down, 32bit only support.