cpufunc.h revision 1.11
1/* $OpenBSD: cpufunc.h,v 1.11 2013/03/22 21:24:11 patrick Exp $ */ 2/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 3 4/* 5 * Copyright (c) 1997 Mark Brinicombe. 6 * Copyright (c) 1997 Causality Limited 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Causality Limited. 20 * 4. The name of Causality Limited may not be used to endorse or promote 21 * products derived from this software without specific prior written 22 * permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 25 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * RiscBSD kernel project 37 * 38 * cpufunc.h 39 * 40 * Prototypes for cpu, mmu and tlb related functions. 41 */ 42 43#ifndef _ARM_CPUFUNC_H_ 44#define _ARM_CPUFUNC_H_ 45 46#ifdef _KERNEL 47 48#include <sys/types.h> 49#include <arm/cpuconf.h> 50 51struct cpu_functions { 52 53 /* CPU functions */ 54 55 u_int (*cf_id) (void); 56 void (*cf_cpwait) (void); 57 58 /* MMU functions */ 59 60 u_int (*cf_control) (u_int bic, u_int eor); 61 void (*cf_domains) (u_int domains); 62 void (*cf_setttb) (u_int ttb); 63 u_int (*cf_dfsr) (void); 64 u_int (*cf_dfar) (void); 65 u_int (*cf_ifsr) (void); 66 u_int (*cf_ifar) (void); 67 68 /* TLB functions */ 69 70 void (*cf_tlb_flushID) (void); 71 void (*cf_tlb_flushID_SE) (u_int va); 72 void (*cf_tlb_flushI) (void); 73 void (*cf_tlb_flushI_SE) (u_int va); 74 void (*cf_tlb_flushD) (void); 75 void (*cf_tlb_flushD_SE) (u_int va); 76 77 /* 78 * Cache operations: 79 * 80 * We define the following primitives: 81 * 82 * icache_sync_all Synchronize I-cache 83 * icache_sync_range Synchronize I-cache range 84 * 85 * dcache_wbinv_all Write-back and Invalidate D-cache 86 * dcache_wbinv_range Write-back and Invalidate D-cache range 87 * dcache_inv_range Invalidate D-cache range 88 * dcache_wb_range Write-back D-cache range 89 * 90 * idcache_wbinv_all Write-back and Invalidate D-cache, 91 * Invalidate I-cache 92 * idcache_wbinv_range Write-back and Invalidate D-cache, 93 * Invalidate I-cache range 94 * 95 * Note that the ARM term for "write-back" is "clean". We use 96 * the term "write-back" since it's a more common way to describe 97 * the operation. 98 * 99 * There are some rules that must be followed: 100 * 101 * I-cache Synch (all or range): 102 * The goal is to synchronize the instruction stream, 103 * so you may beed to write-back dirty D-cache blocks 104 * first. If a range is requested, and you can't 105 * synchronize just a range, you have to hit the whole 106 * thing. 107 * 108 * D-cache Write-Back and Invalidate range: 109 * If you can't WB-Inv a range, you must WB-Inv the 110 * entire D-cache. 111 * 112 * D-cache Invalidate: 113 * If you can't Inv the D-cache, you must Write-Back 114 * and Invalidate. Code that uses this operation 115 * MUST NOT assume that the D-cache will not be written 116 * back to memory. 117 * 118 * D-cache Write-Back: 119 * If you can't Write-back without doing an Inv, 120 * that's fine. Then treat this as a WB-Inv. 121 * Skipping the invalidate is merely an optimization. 122 * 123 * All operations: 124 * Valid virtual addresses must be passed to each 125 * cache operation. 126 */ 127 void (*cf_icache_sync_all) (void); 128 void (*cf_icache_sync_range) (vaddr_t, vsize_t); 129 130 void (*cf_dcache_wbinv_all) (void); 131 void (*cf_dcache_wbinv_range) (vaddr_t, vsize_t); 132 void (*cf_dcache_inv_range) (vaddr_t, vsize_t); 133 void (*cf_dcache_wb_range) (vaddr_t, vsize_t); 134 135 void (*cf_idcache_wbinv_all) (void); 136 void (*cf_idcache_wbinv_range) (vaddr_t, vsize_t); 137 138 /* Other functions */ 139 140 void (*cf_flush_prefetchbuf) (void); 141 void (*cf_drain_writebuf) (void); 142 143 void (*cf_sleep) (int mode); 144 145 /* Soft functions */ 146 void (*cf_context_switch) (u_int); 147 void (*cf_setup) (void); 148}; 149 150extern struct cpu_functions cpufuncs; 151extern u_int cputype; 152 153#define cpu_id() cpufuncs.cf_id() 154#define cpu_cpwait() cpufuncs.cf_cpwait() 155 156#define cpu_control(c, e) cpufuncs.cf_control(c, e) 157#define cpu_domains(d) cpufuncs.cf_domains(d) 158#define cpu_setttb(t) cpufuncs.cf_setttb(t) 159#define cpu_dfsr() cpufuncs.cf_dfsr() 160#define cpu_dfar() cpufuncs.cf_dfar() 161#define cpu_ifsr() cpufuncs.cf_ifsr() 162#define cpu_ifar() cpufuncs.cf_ifar() 163 164#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 165#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 166#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 167#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 168#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 169#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 170 171#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 172#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 173 174#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 175#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 176#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 177#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 178 179#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 180#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 181 182#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 183#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 184 185#define cpu_sleep(m) cpufuncs.cf_sleep(m) 186 187#define cpu_context_switch(a) cpufuncs.cf_context_switch(a) 188#define cpu_setup(a) cpufuncs.cf_setup(a) 189 190int set_cpufuncs (void); 191#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 192#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 193 194void cpufunc_nullop (void); 195int early_abort_fixup (void *); 196int late_abort_fixup (void *); 197u_int cpufunc_id (void); 198u_int cpufunc_control (u_int clear, u_int bic); 199void cpufunc_domains (u_int domains); 200u_int cpufunc_dfsr (void); 201u_int cpufunc_dfar (void); 202u_int cpufunc_ifsr (void); 203u_int cpufunc_ifar (void); 204 205#ifdef CPU_ARM8 206void arm8_setttb (u_int ttb); 207void arm8_tlb_flushID (void); 208void arm8_tlb_flushID_SE (u_int va); 209void arm8_cache_flushID (void); 210void arm8_cache_flushID_E (u_int entry); 211void arm8_cache_cleanID (void); 212void arm8_cache_cleanID_E (u_int entry); 213void arm8_cache_purgeID (void); 214void arm8_cache_purgeID_E (u_int entry); 215 216void arm8_cache_syncI (void); 217void arm8_cache_cleanID_rng (vaddr_t start, vsize_t end); 218void arm8_cache_cleanD_rng (vaddr_t start, vsize_t end); 219void arm8_cache_purgeID_rng (vaddr_t start, vsize_t end); 220void arm8_cache_purgeD_rng (vaddr_t start, vsize_t end); 221void arm8_cache_syncI_rng (vaddr_t start, vsize_t end); 222 223void arm8_context_switch (u_int); 224 225void arm8_setup (void); 226 227u_int arm8_clock_config (u_int, u_int); 228#endif 229 230#if defined(CPU_SA1100) || defined(CPU_SA1110) 231void sa11x0_drain_readbuf (void); 232 233void sa11x0_context_switch (u_int); 234void sa11x0_cpu_sleep (int mode); 235 236void sa11x0_setup (void); 237#endif 238 239#if defined(CPU_SA1100) || defined(CPU_SA1110) 240void sa1_setttb (u_int ttb); 241 242void sa1_tlb_flushID_SE (u_int va); 243 244void sa1_cache_flushID (void); 245void sa1_cache_flushI (void); 246void sa1_cache_flushD (void); 247void sa1_cache_flushD_SE (u_int entry); 248 249void sa1_cache_cleanID (void); 250void sa1_cache_cleanD (void); 251void sa1_cache_cleanD_E (u_int entry); 252 253void sa1_cache_purgeID (void); 254void sa1_cache_purgeID_E (u_int entry); 255void sa1_cache_purgeD (void); 256void sa1_cache_purgeD_E (u_int entry); 257 258void sa1_cache_syncI (void); 259void sa1_cache_cleanID_rng (vaddr_t start, vsize_t end); 260void sa1_cache_cleanD_rng (vaddr_t start, vsize_t end); 261void sa1_cache_purgeID_rng (vaddr_t start, vsize_t end); 262void sa1_cache_purgeD_rng (vaddr_t start, vsize_t end); 263void sa1_cache_syncI_rng (vaddr_t start, vsize_t end); 264 265#endif 266 267#ifdef CPU_ARM9 268void arm9_setttb (u_int); 269 270void arm9_tlb_flushID_SE (u_int); 271 272void arm9_icache_sync_all (void); 273void arm9_icache_sync_range (vaddr_t, vsize_t); 274 275void arm9_dcache_wbinv_all (void); 276void arm9_dcache_wbinv_range (vaddr_t, vsize_t); 277void arm9_dcache_inv_range (vaddr_t, vsize_t); 278void arm9_dcache_wb_range (vaddr_t, vsize_t); 279 280void arm9_idcache_wbinv_all (void); 281void arm9_idcache_wbinv_range (vaddr_t, vsize_t); 282 283void arm9_context_switch (u_int); 284 285void arm9_setup (void); 286 287extern unsigned arm9_dcache_sets_max; 288extern unsigned arm9_dcache_sets_inc; 289extern unsigned arm9_dcache_index_max; 290extern unsigned arm9_dcache_index_inc; 291#endif 292 293#if defined(CPU_ARM9E) || defined(CPU_ARM10) 294void arm10_tlb_flushID_SE (u_int); 295void arm10_tlb_flushI_SE (u_int); 296 297void arm10_context_switch (u_int); 298 299void arm9e_setup (void); 300void arm10_setup (void); 301#endif 302 303#if defined(CPU_ARM9E) || defined (CPU_ARM10) 304void armv5_ec_setttb (u_int); 305 306void armv5_ec_icache_sync_all (void); 307void armv5_ec_icache_sync_range (vaddr_t, vsize_t); 308 309void armv5_ec_dcache_wbinv_all (void); 310void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t); 311void armv5_ec_dcache_inv_range (vaddr_t, vsize_t); 312void armv5_ec_dcache_wb_range (vaddr_t, vsize_t); 313 314void armv5_ec_idcache_wbinv_all (void); 315void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t); 316#endif 317 318#ifdef CPU_ARM11 319void arm11_setttb (u_int); 320 321void arm11_tlb_flushID_SE (u_int); 322void arm11_tlb_flushI_SE (u_int); 323 324void arm11_context_switch (u_int); 325 326void arm11_setup (void); 327void arm11_tlb_flushID (void); 328void arm11_tlb_flushI (void); 329void arm11_tlb_flushD (void); 330void arm11_tlb_flushD_SE (u_int va); 331 332void arm11_drain_writebuf (void); 333void arm11_cpu_sleep (int mode); 334#endif 335 336 337#if defined (CPU_ARM10) || defined(CPU_ARM11) 338void armv5_setttb (u_int); 339 340void armv5_icache_sync_all (void); 341void armv5_icache_sync_range (vaddr_t, vsize_t); 342 343void armv5_dcache_wbinv_all (void); 344void armv5_dcache_wbinv_range (vaddr_t, vsize_t); 345void armv5_dcache_inv_range (vaddr_t, vsize_t); 346void armv5_dcache_wb_range (vaddr_t, vsize_t); 347 348void armv5_idcache_wbinv_all (void); 349void armv5_idcache_wbinv_range (vaddr_t, vsize_t); 350 351extern unsigned armv5_dcache_sets_max; 352extern unsigned armv5_dcache_sets_inc; 353extern unsigned armv5_dcache_index_max; 354extern unsigned armv5_dcache_index_inc; 355#endif 356 357#ifdef CPU_ARMv7 358void armv7_setttb (u_int); 359 360void armv7_tlb_flushID_SE (u_int); 361void armv7_tlb_flushI_SE (u_int); 362 363void armv7_context_switch (u_int); 364void armv7_context_switch (u_int); 365 366void armv7_setup (void); 367void armv7_tlb_flushID (void); 368void armv7_tlb_flushI (void); 369void armv7_tlb_flushD (void); 370void armv7_tlb_flushD_SE (u_int va); 371 372void armv7_drain_writebuf (void); 373void armv7_cpu_sleep (int mode); 374 375void armv7_setttb (u_int); 376 377void armv7_icache_sync_all (void); 378void armv7_icache_sync_range (vaddr_t, vsize_t); 379 380void armv7_dcache_wbinv_all (void); 381void armv7_dcache_wbinv_range (vaddr_t, vsize_t); 382void armv7_dcache_inv_range (vaddr_t, vsize_t); 383void armv7_dcache_wb_range (vaddr_t, vsize_t); 384 385void armv7_idcache_wbinv_all (void); 386void armv7_idcache_wbinv_range (vaddr_t, vsize_t); 387 388extern unsigned armv7_dcache_sets_max; 389extern unsigned armv7_dcache_sets_inc; 390extern unsigned armv7_dcache_index_max; 391extern unsigned armv7_dcache_index_inc; 392#endif 393 394 395#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 396 defined(CPU_SA1100) || defined(CPU_SA1110) || \ 397 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 398 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 399 400void armv4_tlb_flushID (void); 401void armv4_tlb_flushI (void); 402void armv4_tlb_flushD (void); 403void armv4_tlb_flushD_SE (u_int va); 404 405void armv4_drain_writebuf (void); 406#endif 407 408#if defined(CPU_IXP12X0) 409void ixp12x0_drain_readbuf (void); 410void ixp12x0_context_switch (u_int); 411void ixp12x0_setup (void); 412#endif 413 414#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 415 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 416 (ARM_MMU_XSCALE == 1) 417void xscale_cpwait (void); 418 419void xscale_cpu_sleep (int mode); 420 421u_int xscale_control (u_int clear, u_int bic); 422 423void xscale_setttb (u_int ttb); 424 425void xscale_tlb_flushID_SE (u_int va); 426 427void xscale_cache_flushID (void); 428void xscale_cache_flushI (void); 429void xscale_cache_flushD (void); 430void xscale_cache_flushD_SE (u_int entry); 431 432void xscale_cache_cleanID (void); 433void xscale_cache_cleanD (void); 434void xscale_cache_cleanD_E (u_int entry); 435 436void xscale_cache_clean_minidata (void); 437 438void xscale_cache_purgeID (void); 439void xscale_cache_purgeID_E (u_int entry); 440void xscale_cache_purgeD (void); 441void xscale_cache_purgeD_E (u_int entry); 442 443void xscale_cache_syncI (void); 444void xscale_cache_cleanID_rng (vaddr_t start, vsize_t end); 445void xscale_cache_cleanD_rng (vaddr_t start, vsize_t end); 446void xscale_cache_purgeID_rng (vaddr_t start, vsize_t end); 447void xscale_cache_purgeD_rng (vaddr_t start, vsize_t end); 448void xscale_cache_syncI_rng (vaddr_t start, vsize_t end); 449void xscale_cache_flushD_rng (vaddr_t start, vsize_t end); 450 451void xscale_context_switch (u_int); 452 453void xscale_setup (void); 454#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 455 456#define tlb_flush cpu_tlb_flushID 457#define setttb cpu_setttb 458#define drain_writebuf cpu_drain_writebuf 459 460/* 461 * Macros for manipulating CPU interrupts 462 */ 463/* Functions to manipulate the CPSR. */ 464static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor); 465static __inline u_int32_t __get_cpsr(void); 466 467static __inline u_int32_t 468__set_cpsr_c(u_int bic, u_int eor) 469{ 470 u_int32_t tmp, ret; 471 472 __asm __volatile( 473 "mrs %0, cpsr\n\t" /* Get the CPSR */ 474 "bic %1, %0, %2\n\t" /* Clear bits */ 475 "eor %1, %1, %3\n\t" /* XOR bits */ 476 "msr cpsr_c, %1" /* Set CPSR control field */ 477 : "=&r" (ret), "=&r" (tmp) 478 : "r" (bic), "r" (eor)); 479 480 return ret; 481} 482 483static __inline u_int32_t 484__get_cpsr() 485{ 486 u_int32_t ret; 487 488 __asm __volatile("mrs %0, cpsr" : "=&r" (ret)); 489 490 return ret; 491} 492 493#define disable_interrupts(mask) \ 494 (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ 495 (mask) & (I32_bit | F32_bit))) 496 497#define enable_interrupts(mask) \ 498 (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) 499 500#define restore_interrupts(old_cpsr) \ 501 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 502 503/* 504 * Functions to manipulate cpu r13 505 * (in arm/arm/setstack.S) 506 */ 507 508void set_stackptr (u_int mode, u_int address); 509u_int get_stackptr (u_int mode); 510 511/* 512 * Miscellany 513 */ 514 515int get_pc_str_offset (void); 516 517/* 518 * CPU functions from locore.S 519 */ 520 521void cpu_reset (void) __attribute__((__noreturn__)); 522 523/* 524 * Cache info variables. 525 */ 526 527/* PRIMARY CACHE VARIABLES */ 528extern int arm_picache_size; 529extern int arm_picache_line_size; 530extern int arm_picache_ways; 531 532extern int arm_pdcache_size; /* and unified */ 533extern int arm_pdcache_line_size; 534extern int arm_pdcache_ways; 535 536extern int arm_pcache_type; 537extern int arm_pcache_unified; 538 539extern int arm_dcache_align; 540extern int arm_dcache_align_mask; 541 542#endif /* _KERNEL */ 543#endif /* _ARM_CPUFUNC_H_ */ 544 545/* End of cpufunc.h */ 546