cpufunc.h revision 1.13
1/* $OpenBSD: cpufunc.h,v 1.13 2013/03/30 00:57:47 patrick Exp $ */ 2/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 3 4/* 5 * Copyright (c) 1997 Mark Brinicombe. 6 * Copyright (c) 1997 Causality Limited 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Causality Limited. 20 * 4. The name of Causality Limited may not be used to endorse or promote 21 * products derived from this software without specific prior written 22 * permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 25 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * RiscBSD kernel project 37 * 38 * cpufunc.h 39 * 40 * Prototypes for cpu, mmu and tlb related functions. 41 */ 42 43#ifndef _ARM_CPUFUNC_H_ 44#define _ARM_CPUFUNC_H_ 45 46#ifdef _KERNEL 47 48#include <sys/types.h> 49#include <arm/cpuconf.h> 50 51struct cpu_functions { 52 53 /* CPU functions */ 54 55 u_int (*cf_id) (void); 56 void (*cf_cpwait) (void); 57 58 /* MMU functions */ 59 60 u_int (*cf_control) (u_int bic, u_int eor); 61 void (*cf_domains) (u_int domains); 62 void (*cf_setttb) (u_int ttb); 63 u_int (*cf_dfsr) (void); 64 u_int (*cf_dfar) (void); 65 u_int (*cf_ifsr) (void); 66 u_int (*cf_ifar) (void); 67 68 /* TLB functions */ 69 70 void (*cf_tlb_flushID) (void); 71 void (*cf_tlb_flushID_SE) (u_int va); 72 void (*cf_tlb_flushI) (void); 73 void (*cf_tlb_flushI_SE) (u_int va); 74 void (*cf_tlb_flushD) (void); 75 void (*cf_tlb_flushD_SE) (u_int va); 76 77 /* 78 * Cache operations: 79 * 80 * We define the following primitives: 81 * 82 * icache_sync_all Synchronize I-cache 83 * icache_sync_range Synchronize I-cache range 84 * 85 * dcache_wbinv_all Write-back and Invalidate D-cache 86 * dcache_wbinv_range Write-back and Invalidate D-cache range 87 * dcache_inv_range Invalidate D-cache range 88 * dcache_wb_range Write-back D-cache range 89 * 90 * idcache_wbinv_all Write-back and Invalidate D-cache, 91 * Invalidate I-cache 92 * idcache_wbinv_range Write-back and Invalidate D-cache, 93 * Invalidate I-cache range 94 * 95 * Note that the ARM term for "write-back" is "clean". We use 96 * the term "write-back" since it's a more common way to describe 97 * the operation. 98 * 99 * There are some rules that must be followed: 100 * 101 * I-cache Synch (all or range): 102 * The goal is to synchronize the instruction stream, 103 * so you may beed to write-back dirty D-cache blocks 104 * first. If a range is requested, and you can't 105 * synchronize just a range, you have to hit the whole 106 * thing. 107 * 108 * D-cache Write-Back and Invalidate range: 109 * If you can't WB-Inv a range, you must WB-Inv the 110 * entire D-cache. 111 * 112 * D-cache Invalidate: 113 * If you can't Inv the D-cache, you must Write-Back 114 * and Invalidate. Code that uses this operation 115 * MUST NOT assume that the D-cache will not be written 116 * back to memory. 117 * 118 * D-cache Write-Back: 119 * If you can't Write-back without doing an Inv, 120 * that's fine. Then treat this as a WB-Inv. 121 * Skipping the invalidate is merely an optimization. 122 * 123 * All operations: 124 * Valid virtual addresses must be passed to each 125 * cache operation. 126 */ 127 void (*cf_icache_sync_all) (void); 128 void (*cf_icache_sync_range) (vaddr_t, vsize_t); 129 130 void (*cf_dcache_wbinv_all) (void); 131 void (*cf_dcache_wbinv_range) (vaddr_t, vsize_t); 132 void (*cf_dcache_inv_range) (vaddr_t, vsize_t); 133 void (*cf_dcache_wb_range) (vaddr_t, vsize_t); 134 135 void (*cf_idcache_wbinv_all) (void); 136 void (*cf_idcache_wbinv_range) (vaddr_t, vsize_t); 137 138 void (*cf_sdcache_wbinv_all) (void); 139 void (*cf_sdcache_wbinv_range) (vaddr_t, paddr_t, vsize_t); 140 void (*cf_sdcache_inv_range) (vaddr_t, paddr_t, vsize_t); 141 void (*cf_sdcache_wb_range) (vaddr_t, paddr_t, vsize_t); 142 143 /* Other functions */ 144 145 void (*cf_flush_prefetchbuf) (void); 146 void (*cf_drain_writebuf) (void); 147 148 void (*cf_sleep) (int mode); 149 150 /* Soft functions */ 151 void (*cf_context_switch) (u_int); 152 void (*cf_setup) (void); 153}; 154 155extern struct cpu_functions cpufuncs; 156extern u_int cputype; 157 158#define cpu_id() cpufuncs.cf_id() 159#define cpu_cpwait() cpufuncs.cf_cpwait() 160 161#define cpu_control(c, e) cpufuncs.cf_control(c, e) 162#define cpu_domains(d) cpufuncs.cf_domains(d) 163#define cpu_setttb(t) cpufuncs.cf_setttb(t) 164#define cpu_dfsr() cpufuncs.cf_dfsr() 165#define cpu_dfar() cpufuncs.cf_dfar() 166#define cpu_ifsr() cpufuncs.cf_ifsr() 167#define cpu_ifar() cpufuncs.cf_ifar() 168 169#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 170#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 171#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 172#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 173#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 174#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 175 176#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 177#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 178 179#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 180#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 181#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 182#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 183 184#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 185#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 186 187#define cpu_sdcache_enabled() (cpufuncs.cf_sdcache_wbinv_all != cpufunc_nullop) 188#define cpu_sdcache_wbinv_all() cpufuncs.cf_sdcache_wbinv_all() 189#define cpu_sdcache_wbinv_range(va, pa, s) cpufuncs.cf_sdcache_wbinv_range((va), (pa), (s)) 190#define cpu_sdcache_inv_range(va, pa, s) cpufuncs.cf_sdcache_inv_range((va), (pa), (s)) 191#define cpu_sdcache_wb_range(va, pa, s) cpufuncs.cf_sdcache_wb_range((va), (pa), (s)) 192 193#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 194#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 195 196#define cpu_sleep(m) cpufuncs.cf_sleep(m) 197 198#define cpu_context_switch(a) cpufuncs.cf_context_switch(a) 199#define cpu_setup(a) cpufuncs.cf_setup(a) 200 201int set_cpufuncs (void); 202#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 203#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 204 205void cpufunc_nullop (void); 206int early_abort_fixup (void *); 207int late_abort_fixup (void *); 208u_int cpufunc_id (void); 209u_int cpufunc_control (u_int clear, u_int bic); 210void cpufunc_domains (u_int domains); 211u_int cpufunc_dfsr (void); 212u_int cpufunc_dfar (void); 213u_int cpufunc_ifsr (void); 214u_int cpufunc_ifar (void); 215 216#ifdef CPU_ARM8 217void arm8_setttb (u_int ttb); 218void arm8_tlb_flushID (void); 219void arm8_tlb_flushID_SE (u_int va); 220void arm8_cache_flushID (void); 221void arm8_cache_flushID_E (u_int entry); 222void arm8_cache_cleanID (void); 223void arm8_cache_cleanID_E (u_int entry); 224void arm8_cache_purgeID (void); 225void arm8_cache_purgeID_E (u_int entry); 226 227void arm8_cache_syncI (void); 228void arm8_cache_cleanID_rng (vaddr_t start, vsize_t end); 229void arm8_cache_cleanD_rng (vaddr_t start, vsize_t end); 230void arm8_cache_purgeID_rng (vaddr_t start, vsize_t end); 231void arm8_cache_purgeD_rng (vaddr_t start, vsize_t end); 232void arm8_cache_syncI_rng (vaddr_t start, vsize_t end); 233 234void arm8_context_switch (u_int); 235 236void arm8_setup (void); 237 238u_int arm8_clock_config (u_int, u_int); 239#endif 240 241#if defined(CPU_SA1100) || defined(CPU_SA1110) 242void sa11x0_drain_readbuf (void); 243 244void sa11x0_context_switch (u_int); 245void sa11x0_cpu_sleep (int mode); 246 247void sa11x0_setup (void); 248#endif 249 250#if defined(CPU_SA1100) || defined(CPU_SA1110) 251void sa1_setttb (u_int ttb); 252 253void sa1_tlb_flushID_SE (u_int va); 254 255void sa1_cache_flushID (void); 256void sa1_cache_flushI (void); 257void sa1_cache_flushD (void); 258void sa1_cache_flushD_SE (u_int entry); 259 260void sa1_cache_cleanID (void); 261void sa1_cache_cleanD (void); 262void sa1_cache_cleanD_E (u_int entry); 263 264void sa1_cache_purgeID (void); 265void sa1_cache_purgeID_E (u_int entry); 266void sa1_cache_purgeD (void); 267void sa1_cache_purgeD_E (u_int entry); 268 269void sa1_cache_syncI (void); 270void sa1_cache_cleanID_rng (vaddr_t start, vsize_t end); 271void sa1_cache_cleanD_rng (vaddr_t start, vsize_t end); 272void sa1_cache_purgeID_rng (vaddr_t start, vsize_t end); 273void sa1_cache_purgeD_rng (vaddr_t start, vsize_t end); 274void sa1_cache_syncI_rng (vaddr_t start, vsize_t end); 275 276#endif 277 278#ifdef CPU_ARM9 279void arm9_setttb (u_int); 280 281void arm9_tlb_flushID_SE (u_int); 282 283void arm9_icache_sync_all (void); 284void arm9_icache_sync_range (vaddr_t, vsize_t); 285 286void arm9_dcache_wbinv_all (void); 287void arm9_dcache_wbinv_range (vaddr_t, vsize_t); 288void arm9_dcache_inv_range (vaddr_t, vsize_t); 289void arm9_dcache_wb_range (vaddr_t, vsize_t); 290 291void arm9_idcache_wbinv_all (void); 292void arm9_idcache_wbinv_range (vaddr_t, vsize_t); 293 294void arm9_context_switch (u_int); 295 296void arm9_setup (void); 297 298extern unsigned arm9_dcache_sets_max; 299extern unsigned arm9_dcache_sets_inc; 300extern unsigned arm9_dcache_index_max; 301extern unsigned arm9_dcache_index_inc; 302#endif 303 304#if defined(CPU_ARM9E) || defined(CPU_ARM10) 305void arm10_tlb_flushID_SE (u_int); 306void arm10_tlb_flushI_SE (u_int); 307 308void arm10_context_switch (u_int); 309 310void arm9e_setup (void); 311void arm10_setup (void); 312#endif 313 314#if defined(CPU_ARM9E) || defined (CPU_ARM10) 315void armv5_ec_setttb (u_int); 316 317void armv5_ec_icache_sync_all (void); 318void armv5_ec_icache_sync_range (vaddr_t, vsize_t); 319 320void armv5_ec_dcache_wbinv_all (void); 321void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t); 322void armv5_ec_dcache_inv_range (vaddr_t, vsize_t); 323void armv5_ec_dcache_wb_range (vaddr_t, vsize_t); 324 325void armv5_ec_idcache_wbinv_all (void); 326void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t); 327#endif 328 329#ifdef CPU_ARM11 330void arm11_setttb (u_int); 331 332void arm11_tlb_flushID_SE (u_int); 333void arm11_tlb_flushI_SE (u_int); 334 335void arm11_context_switch (u_int); 336 337void arm11_setup (void); 338void arm11_tlb_flushID (void); 339void arm11_tlb_flushI (void); 340void arm11_tlb_flushD (void); 341void arm11_tlb_flushD_SE (u_int va); 342 343void arm11_drain_writebuf (void); 344void arm11_cpu_sleep (int mode); 345#endif 346 347 348#if defined (CPU_ARM10) || defined(CPU_ARM11) 349void armv5_setttb (u_int); 350 351void armv5_icache_sync_all (void); 352void armv5_icache_sync_range (vaddr_t, vsize_t); 353 354void armv5_dcache_wbinv_all (void); 355void armv5_dcache_wbinv_range (vaddr_t, vsize_t); 356void armv5_dcache_inv_range (vaddr_t, vsize_t); 357void armv5_dcache_wb_range (vaddr_t, vsize_t); 358 359void armv5_idcache_wbinv_all (void); 360void armv5_idcache_wbinv_range (vaddr_t, vsize_t); 361 362extern unsigned armv5_dcache_sets_max; 363extern unsigned armv5_dcache_sets_inc; 364extern unsigned armv5_dcache_index_max; 365extern unsigned armv5_dcache_index_inc; 366#endif 367 368#ifdef CPU_ARMv7 369void armv7_setttb (u_int); 370 371void armv7_tlb_flushID_SE (u_int); 372void armv7_tlb_flushI_SE (u_int); 373 374void armv7_context_switch (u_int); 375 376void armv7_setup (void); 377void armv7_tlb_flushID (void); 378void armv7_tlb_flushI (void); 379void armv7_tlb_flushD (void); 380void armv7_tlb_flushD_SE (u_int va); 381 382void armv7_drain_writebuf (void); 383void armv7_cpu_sleep (int mode); 384 385void armv7_icache_sync_all (void); 386void armv7_icache_sync_range (vaddr_t, vsize_t); 387 388void armv7_dcache_wbinv_all (void); 389void armv7_dcache_wbinv_range (vaddr_t, vsize_t); 390void armv7_dcache_inv_range (vaddr_t, vsize_t); 391void armv7_dcache_wb_range (vaddr_t, vsize_t); 392 393void armv7_idcache_wbinv_all (void); 394void armv7_idcache_wbinv_range (vaddr_t, vsize_t); 395 396extern unsigned armv7_dcache_sets_max; 397extern unsigned armv7_dcache_sets_inc; 398extern unsigned armv7_dcache_index_max; 399extern unsigned armv7_dcache_index_inc; 400#endif 401 402 403#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 404 defined(CPU_SA1100) || defined(CPU_SA1110) || \ 405 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 406 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 407 408void armv4_tlb_flushID (void); 409void armv4_tlb_flushI (void); 410void armv4_tlb_flushD (void); 411void armv4_tlb_flushD_SE (u_int va); 412 413void armv4_drain_writebuf (void); 414#endif 415 416#if defined(CPU_IXP12X0) 417void ixp12x0_drain_readbuf (void); 418void ixp12x0_context_switch (u_int); 419void ixp12x0_setup (void); 420#endif 421 422#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 423 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 424 (ARM_MMU_XSCALE == 1) 425void xscale_cpwait (void); 426 427void xscale_cpu_sleep (int mode); 428 429u_int xscale_control (u_int clear, u_int bic); 430 431void xscale_setttb (u_int ttb); 432 433void xscale_tlb_flushID_SE (u_int va); 434 435void xscale_cache_flushID (void); 436void xscale_cache_flushI (void); 437void xscale_cache_flushD (void); 438void xscale_cache_flushD_SE (u_int entry); 439 440void xscale_cache_cleanID (void); 441void xscale_cache_cleanD (void); 442void xscale_cache_cleanD_E (u_int entry); 443 444void xscale_cache_clean_minidata (void); 445 446void xscale_cache_purgeID (void); 447void xscale_cache_purgeID_E (u_int entry); 448void xscale_cache_purgeD (void); 449void xscale_cache_purgeD_E (u_int entry); 450 451void xscale_cache_syncI (void); 452void xscale_cache_cleanID_rng (vaddr_t start, vsize_t end); 453void xscale_cache_cleanD_rng (vaddr_t start, vsize_t end); 454void xscale_cache_purgeID_rng (vaddr_t start, vsize_t end); 455void xscale_cache_purgeD_rng (vaddr_t start, vsize_t end); 456void xscale_cache_syncI_rng (vaddr_t start, vsize_t end); 457void xscale_cache_flushD_rng (vaddr_t start, vsize_t end); 458 459void xscale_context_switch (u_int); 460 461void xscale_setup (void); 462#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 463 464#define tlb_flush cpu_tlb_flushID 465#define setttb cpu_setttb 466#define drain_writebuf cpu_drain_writebuf 467 468/* 469 * Macros for manipulating CPU interrupts 470 */ 471/* Functions to manipulate the CPSR. */ 472static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor); 473static __inline u_int32_t __get_cpsr(void); 474 475static __inline u_int32_t 476__set_cpsr_c(u_int bic, u_int eor) 477{ 478 u_int32_t tmp, ret; 479 480 __asm __volatile( 481 "mrs %0, cpsr\n\t" /* Get the CPSR */ 482 "bic %1, %0, %2\n\t" /* Clear bits */ 483 "eor %1, %1, %3\n\t" /* XOR bits */ 484 "msr cpsr_c, %1" /* Set CPSR control field */ 485 : "=&r" (ret), "=&r" (tmp) 486 : "r" (bic), "r" (eor)); 487 488 return ret; 489} 490 491static __inline u_int32_t 492__get_cpsr() 493{ 494 u_int32_t ret; 495 496 __asm __volatile("mrs %0, cpsr" : "=&r" (ret)); 497 498 return ret; 499} 500 501#define disable_interrupts(mask) \ 502 (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ 503 (mask) & (I32_bit | F32_bit))) 504 505#define enable_interrupts(mask) \ 506 (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) 507 508#define restore_interrupts(old_cpsr) \ 509 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 510 511/* 512 * Functions to manipulate cpu r13 513 * (in arm/arm/setstack.S) 514 */ 515 516void set_stackptr (u_int mode, u_int address); 517u_int get_stackptr (u_int mode); 518 519/* 520 * Miscellany 521 */ 522 523int get_pc_str_offset (void); 524 525/* 526 * CPU functions from locore.S 527 */ 528 529void cpu_reset (void) __attribute__((__noreturn__)); 530 531/* 532 * Cache info variables. 533 */ 534 535/* PRIMARY CACHE VARIABLES */ 536extern int arm_picache_size; 537extern int arm_picache_line_size; 538extern int arm_picache_ways; 539 540extern int arm_pdcache_size; /* and unified */ 541extern int arm_pdcache_line_size; 542extern int arm_pdcache_ways; 543 544extern int arm_pcache_type; 545extern int arm_pcache_unified; 546 547extern int arm_dcache_align; 548extern int arm_dcache_align_mask; 549 550#endif /* _KERNEL */ 551#endif /* _ARM_CPUFUNC_H_ */ 552 553/* End of cpufunc.h */ 554