Use the architecture documented name ULR for the RDHWR user local
register.

Add some comments for the RDHWR register numbers.

Only need one #define for MIPS_HWR_CPUNUM.

fix typos, mainly in words minimum and maximum, but also few others.

s/definitons/definitions/

Update the FPU register names and bit definitions to something somewhat
modern (MIPS32/MIPS64) and convert to __BIT/__BITS.

branches: 1.110.4; 1.110.6;
Handle gas/gcc generating a break/trap 6 for integer overflow and
break/trap 7 for integer divide by zero and setting the SIGFPE
si_code of FPE_INTOVF or FPE_INTDIV respectively. The break/trap
6/7 seems to have existed since the early days of MIPS but not
well documented anywhere.

Fixes ATF lib/libc/gen/t_siginfo::sigfpe_int .

branches: 1.109.2;
Remove bogus duplicate MIPS_COP_0_CONTEXT definition, it's not a MIPS32/64
specific reg and we already define MIPS_COP_0_TLB_CONTEXT elsewhere.

Add a few more perfcnt CP0 registers.

Add two cnMIPS III COP0 register names.

Add definitions for the CP0 WatchLo/WatchHi registers.

#define<tab>
Nuke trailing whitespace.

Add CP0 Config Registers 6 and 7.

Remove mostly duplicate MIPS spec CP0 regs from octeon_corereg.h, move
the Cavium specific CP0 regs to <mips/cpuregs.h> as done for other core
specific regs.

Expose the width of the MIPS_EBASE_CPUNUM bitfield for asm code.

Add an extra bitfield in MIPS_COP_0_EBASE.

Remove a magic number.

Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.

Add CX73xx and CXF75xx Cavium Octeon PRIDs.

Add PRID definition for newer SiByte SB1 cores (rev 0x11).
Add a constant for SiByte/BCRM cacheable coherent TLB cache attribute.

Trailing whitespace

branches: 1.95.8;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Add a few MIPS32 R3 bits

Add MIPS 1074K

Define COP0 register that use select value in <mips/cpuregs.h>
Use those new definitions

Rework cavium support in preparation for MULTIPROCESSOR support

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

branches: 1.89.2;
deal with Ingenic XBurst CPUs

branches: 1.88.12;
Add Broadcom BCM3302 CPU to the table.

support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs

loongson2f support:
- Add some loongson2 definitions to cpuregs.h, from OpenBSD
- Make sure that the at register is useable before every jump register
instruction (exept when register is k0 or k1) because -mfix-loongson2f-btb
needs the at register for its workaround
- add code to mips_fixup.c to handle the instructions added by
-mfix-loongson2f-btb
- Add a ls2-specific tlb miss handler: it doesn't have separate handler
for the xtlbmiss exeption.
- Fixes for some #ifdef MIPS3_LOONGSON2 assembly code (using the wrong
register)

Add Loongson2 DIAG register definitions (partial)

Add define for loongson2 DIAG register

Fix some comments.

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.

branches: 1.78.2; 1.78.4; 1.78.6;
Spell "exception" properly.

branches: 1.77.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

LOONGSON2 is a MIPS III

Add Loongson2 chip ids

branches: 1.74.10; 1.74.28;
Add PrID's for MIPS's 24K, 24KE, 34K and 74K cores.

From Alexander Voropay in mail to port-mips@.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Recognise the R2000A cpu as found in some pmaxen.

From Dennis Grevenstein on port-pmax@.

branches: 1.71.6; 1.71.12; 1.71.20; 1.71.22; 1.71.30; 1.71.32; 1.71.34;
Don't cast pointers using unsigned and/or int. Use intptr_t or uintptr_t
as appropriate.

Fix typo in MIPS3_SR_EIE.
From Anders Gavare.

branches: 1.69.4; 1.69.6; 1.69.8; 1.69.12;
Add basic support for Alchemy Au1550 processor (CPU and devices).
Patch contributed by Garrett D'Amore in PR port-evbmips/32030.

merge ktrace-lwp.

Remove unused and incorrect MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2()
macro.

Check MIPS3_CONFIG_CS and adjust csizebase at runtime on MIPS_R4100 CPUs,
and remove "XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY" part
from cpuregs.h. Tested on gxemul.

BTW, cache.c doesn't have MIPS_RC32364 config which was added
in mips_machdep.c rev 1.101?

branches: 1.65.14; 1.65.16;
Add some more MTI CPU ids.

- Add MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2() macro.
- Add definitions of the MIPS4 config register.

From Christopher SEKIYA.

Add another R4000 CPU revision ID. From Christopher SEKIYA.

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.61.2;
Change MIPS3_SR_FR_32 to MIPS3_SR_FR. Both the old R4000 manual and the
current MIPS64 manuals don't use the "32" in the bit name.

Remove definitions and usage of MIPS_COP_0_STATUS_REG and
MIPS_COP_0_CAUSE_REG - use MIPS_COP_0_STATUS and MIPS_COP_0_CAUSE
instead.

Add the MIPS3_CONFIG_SE (name taken from Rm52xx manual) bit, which is the
external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k. If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.

Also, update sgimips code to use the new name.

Define COP0_HAZARD_FPUENABLE as four nops.
Include <mips/sb1regs.h> if MIPS64_SB1 is defined.

Add two PRiD values.
- 0x55 for NEC Vr5500. ISA might be MIPS64.
- 0x38 for Toshiba TX79. This has thirty-two 128bit GPRs while
maintaining 32bit only virtual address space. Any of pointer related
registers have 32bit.

Add the Toshiba TX4927 CPU.

Add support for detecting Alchemy Semiconductor CPUs. Alchemy use the
processor ID field to donote the CPU core revision and the company
options field do donate the SOC chip type, so we need to add an extra
field to the "pridtab" structure to identify these CPUs.

Overhaul the emulation facility. We do this by:

- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
emulated instructions
- cleaning up emulation dispatch in trap()

Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.

Tested on r3k with and without SOFTFLOAT enabled.

Add the 20Kc processor ID.

For the CP0 status register bit definitions- add the MX, PX and NMI bits
and rename TLB_SHUTDOWN and SOFT_RESET to TS and SR (the abbreviations
in the MIPS documentation).

XXX: this file really needs to be cleaned up one day...

Standardise on the name "MIPS_SR_BEV" instead of a couple of different
#defines for the same status bit.

branches: 1.50.4;
Add R4400 reg 0x60 to the MIPS CPU table.
From PR port-mips/15894 from Thilo Manske.

Add support for MIPS32 and MIPS64 architectures:
- Add XKPHYS macros (from Broadcom Corp).
- Add some r5900 register bit definitions.
- Add extra exception vector addresses for mips32/mips64 and r5900.
- Make the mips cp0 register definitions available from both asm and C.
- Add some Alchemy and Sandcraft CPU ids.
- Add r3000, tx39xx and r4x00 CPU revision ids.
- Remove defines for the number of TLBs on some CPUs.

R4000/R4400 always detects virtual alias as if
primary cache size is 32KB. Actual primary cache size
is ignored wrt VCED/VCEI.

branches: 1.47.4;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.

Describe the widths of various coprocessor 0 registers (for mips1,
mips3, mips32 and mips64).

_Never_ make a cosmetic change to a comment without test-compiling...

Add some MIPS, Alchemy and SiByte CPU PRIDs (from oss.sgi.com).

branches: 1.43.2;
PRiD 0x18 is shared by RC32334, 332 and 355. These SoCs are
distinguished by SYSID register in the system controller. Note
that PRiD 0x20 is for a standalone RC32364 processor which has the
same 32300 core inside. Rather better to name them MIPS32 ISA.

Pasto.

Add PRiD 0x18 for IDT RC32332/RC32334 processors.

Add the processor IDs for the 4Kc and 5Kc CPUs and some MIPS32/64
coprocessor 0 registers.

Add PRiD register imp value 0x2d for Toshiba TX4900 family.

branches: 1.38.2;
Correct a few cpu/fpu ids.

Use only one TLB entry to wire down process's USPACE since it's
now guranteed to be aligned on 8KB boundary in kernel virutal
address. Retain one more free TLB entry.

IDT32364's Config register uses a different base for IC/DC (instruction
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).

abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).

XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h

if MIPS3_ENABLE_CLOCK_INTR is defined, set MIPS3_[HARD_]INT_MASK
appropriately. This supports ports that use the internal clock.
Add 2 diag register defines that are specific to QED processors.

branches: 1.34.2;
Decrease MIPS3_TLB_WIRED_ENTRIES from 8 to 2,
and rename it to MIPS3_TLB_WIRED_UPAGES.
The value of wired register becomes variable on arc port,
and arc is the only mips3 port which uses the wired TLB entries 2..7.

Typo.

branches: 1.32.2;
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.

Add R12K PRID.

Add QED RM7000 PrID.

Remove FPU PRIDs that are identical to the CPU ones.

Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.

Garbage collect MIPS_SR_INT_ENAB/MIPS_SR_INT_ENA_CUR definitions.

Add macro for MIPS_PHYS_MASK and document use of bits in system status
registers.

FIX:
port-mips/9016 [serious/medium]:
MIPS FPU emulator points wrong epc on exception case

Responsible: port-mips-maintainer (NetBSD/mips Portmasters)
State: open
Class: sw-bug
Originator: Shuichiro URATA
Release: current 12/11/1999
Arrival-Date: Fri Dec 17 10:18:00 1999
commit patch
http://www.a-r.org/~ur/softfloat1211.diff.gz
by Shuichiro URATA (ur@a-r.org)

TX3912/22 support. ENABLE_MIPS_TX3900 enables it.

branches: 1.23.2; 1.23.8;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */

- Redefine symbols and parameters to represent CPU design with MIPS
nomenclature, retaining the old heritage.
- Remove API-related definitions for now obsolete utiltity routines.

- MIPS processors do not impose inclusive (nesting) interrupt levels with
their interrupt lines. The notion and implemention of 'spl' are left
for how target ports approach to it.

Nuke register and remove trailling white space.

branches: 1.19.4;
- Add NEC Vr5400 processor ID.

- Update 'cpuregs.h' and decline 'cpuarch.h'.

- Fix an error in primary cache line size detection logic; when IC and/or DC
bit is 1, then line size is 32. Otherwise, 16.

branches: 1.16.2;
More patches for ARC from Noriyuki Soda:
* commit isapnpvar.h changes required for ARC to support plain isa.
* fixup mistake over mips/include/cpuregs.h.
* mips/mips_machdep.c:
set L2 cache-size for arc, cleanup use of L2cache present
vs L2 cache-size variables. check for no L2 cache on kernels
configured to require one. misc cleanups.
* mips/mpis/trap.c: more locore stack-traceback label cleanup.
XXX Locore callbacks for mips3, mips4, r4600 cacheflush need more work.

Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.

define mips3 COUNT and COMPARE cp0 registers (onchip cycle counter)

* Change Sprite MACH_xxx prefix to MIPS_xxx.

* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
(more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).

Final changes for configuring MIPS1 and MIPS3 in a single kernel.

* cpuregs.h:
rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
Add compile-time MIPS3-only, compile-time MIPS1-only, and
runtime (both) definitions for number of TLB ASIDs (tlb pids)
and shift count to extract a TLB pid.

* locore.h:
Delete unused vector slot for indexed TLB writes.
mips1 and mips3 TLBs are different enough that we have
to break them out at the caller anyway.

* Add compile-time MIPS3-only andcompile-time MIPS1-only
macros to call locore functions directly by name.
Use the existing method table only if

* mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
Use MIPS3_ or MIPS1_ specific names for TLB pids in
mips3 and mips1 specific code paths (e.g., creating the kernel stack
for process 0).

Add `options MIPS3' to pmax/conf/GENERIC.

More mips1/mips3 changes to cpuregs.h and psl.h:
* cpuregs.h:
Delete unused VMMACH_ names (e.g., duplicates of PTE bits in pte.h).
Change remaining VMMACH_xxx names to MIPS1_xxx or MIPS3_xx.
Fold remaining compile-time definitions into a single #ifdef MIPS3.

* Use MIPS1_ names in locore_r2000.S, mips3_ names in locore_r4000.S

* Garbage-collect MachHitFlushDCache()

* psl.h:
use MIPS1_, MIPS3_ symbolic names for Cause register bits.
change _R3K to MIPS1_, _R4K to MIPS3. Conditionalize for mips1 only,
mips3 only, or when both are defined, use runtime CPUISMIPS3 test.

Fix idempotent inclusion test macro: _MACHCONST -> _MIPS_CPUREGS_H_
to avoid collision with obsolete Sprite-derived NetBSD/pica header file.

Garbage-collect MIPS_3K_xxx, MIPS_4K_xxx outidde mips/include/cpuregs.h:
MIPS_3K_xxx -> MIPS1_xxx
MIPS_4K_xxx -> MIPS3_xxx

More merged MIPS1/MIPS3 support: still only allows single-architecture
support.

Fix typo.

Add defines for increasing SPL levels, assuming devices are wired up
in to CPU interrupt pins in order of increasing priority.

Resolve all differences between the Pica and pmax versions of machConst.h:
* add "MIPS_3k_" for the MIPS-I r[23]000-specific register definitions.
* add "MIPS_4k_" for the MIPS-II/III r4000-specific register definitions.
* add #defines that provide the old values for locore and user
code, so the existing code continues to compile.

Regression-tested against the old headers by grepping for #define's,
editing out the defined symbols, and preprocessing with both the previous
machConst.h headers and this version.

Some unused symbols (CPU and FPU must-be-zero constants) are no longer defined.
Pica interrupt masks are now constant expressions instead of constant
values.

TODO:
* factor out the common #defines into src/sys/arch/mips.
* Get rid of the Sprite coding-style names (MACH_xxx).
* Separate out the r3k/r4k differences from the Pica/pmax differences.
* Figure out how to have a run-time choice of r3k vs. r4k support,
instead of a compile-time choice.

new RCS ID format.

bsd 4.4-lite pmax port as ported to NetBSD

upgrade to bsd 4.4-lite code base. only mod is rcsids

branches: 1.1.1;
Initial revision

fix typos, mainly in words minimum and maximum, but also few others.

s/definitons/definitions/

Update the FPU register names and bit definitions to something somewhat
modern (MIPS32/MIPS64) and convert to __BIT/__BITS.

branches: 1.110.4; 1.110.6;
Handle gas/gcc generating a break/trap 6 for integer overflow and
break/trap 7 for integer divide by zero and setting the SIGFPE
si_code of FPE_INTOVF or FPE_INTDIV respectively. The break/trap
6/7 seems to have existed since the early days of MIPS but not
well documented anywhere.

Fixes ATF lib/libc/gen/t_siginfo::sigfpe_int .

branches: 1.109.2;
Remove bogus duplicate MIPS_COP_0_CONTEXT definition, it's not a MIPS32/64
specific reg and we already define MIPS_COP_0_TLB_CONTEXT elsewhere.

Add a few more perfcnt CP0 registers.

Add two cnMIPS III COP0 register names.

Add definitions for the CP0 WatchLo/WatchHi registers.

#define<tab>
Nuke trailing whitespace.

Add CP0 Config Registers 6 and 7.

Remove mostly duplicate MIPS spec CP0 regs from octeon_corereg.h, move
the Cavium specific CP0 regs to <mips/cpuregs.h> as done for other core
specific regs.

Expose the width of the MIPS_EBASE_CPUNUM bitfield for asm code.

Add an extra bitfield in MIPS_COP_0_EBASE.

Remove a magic number.

Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.

Add CX73xx and CXF75xx Cavium Octeon PRIDs.

Add PRID definition for newer SiByte SB1 cores (rev 0x11).
Add a constant for SiByte/BCRM cacheable coherent TLB cache attribute.

Trailing whitespace

branches: 1.95.8;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Add a few MIPS32 R3 bits

Add MIPS 1074K

Define COP0 register that use select value in <mips/cpuregs.h>
Use those new definitions

Rework cavium support in preparation for MULTIPROCESSOR support

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

branches: 1.89.2;
deal with Ingenic XBurst CPUs

branches: 1.88.12;
Add Broadcom BCM3302 CPU to the table.

support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs

loongson2f support:
- Add some loongson2 definitions to cpuregs.h, from OpenBSD
- Make sure that the at register is useable before every jump register
instruction (exept when register is k0 or k1) because -mfix-loongson2f-btb
needs the at register for its workaround
- add code to mips_fixup.c to handle the instructions added by
-mfix-loongson2f-btb
- Add a ls2-specific tlb miss handler: it doesn't have separate handler
for the xtlbmiss exeption.
- Fixes for some #ifdef MIPS3_LOONGSON2 assembly code (using the wrong
register)

Add Loongson2 DIAG register definitions (partial)

Add define for loongson2 DIAG register

Fix some comments.

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.

branches: 1.78.2; 1.78.4; 1.78.6;
Spell "exception" properly.

branches: 1.77.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

LOONGSON2 is a MIPS III

Add Loongson2 chip ids

branches: 1.74.10; 1.74.28;
Add PrID's for MIPS's 24K, 24KE, 34K and 74K cores.

From Alexander Voropay in mail to port-mips@.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Recognise the R2000A cpu as found in some pmaxen.

From Dennis Grevenstein on port-pmax@.

branches: 1.71.6; 1.71.12; 1.71.20; 1.71.22; 1.71.30; 1.71.32; 1.71.34;
Don't cast pointers using unsigned and/or int. Use intptr_t or uintptr_t
as appropriate.

Fix typo in MIPS3_SR_EIE.
From Anders Gavare.

branches: 1.69.4; 1.69.6; 1.69.8; 1.69.12;
Add basic support for Alchemy Au1550 processor (CPU and devices).
Patch contributed by Garrett D'Amore in PR port-evbmips/32030.

merge ktrace-lwp.

Remove unused and incorrect MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2()
macro.

Check MIPS3_CONFIG_CS and adjust csizebase at runtime on MIPS_R4100 CPUs,
and remove "XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY" part
from cpuregs.h. Tested on gxemul.

BTW, cache.c doesn't have MIPS_RC32364 config which was added
in mips_machdep.c rev 1.101?

branches: 1.65.14; 1.65.16;
Add some more MTI CPU ids.

- Add MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2() macro.
- Add definitions of the MIPS4 config register.

From Christopher SEKIYA.

Add another R4000 CPU revision ID. From Christopher SEKIYA.

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.61.2;
Change MIPS3_SR_FR_32 to MIPS3_SR_FR. Both the old R4000 manual and the
current MIPS64 manuals don't use the "32" in the bit name.

Remove definitions and usage of MIPS_COP_0_STATUS_REG and
MIPS_COP_0_CAUSE_REG - use MIPS_COP_0_STATUS and MIPS_COP_0_CAUSE
instead.

Add the MIPS3_CONFIG_SE (name taken from Rm52xx manual) bit, which is the
external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k. If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.

Also, update sgimips code to use the new name.

Define COP0_HAZARD_FPUENABLE as four nops.
Include <mips/sb1regs.h> if MIPS64_SB1 is defined.

Add two PRiD values.
- 0x55 for NEC Vr5500. ISA might be MIPS64.
- 0x38 for Toshiba TX79. This has thirty-two 128bit GPRs while
maintaining 32bit only virtual address space. Any of pointer related
registers have 32bit.

Add the Toshiba TX4927 CPU.

Add support for detecting Alchemy Semiconductor CPUs. Alchemy use the
processor ID field to donote the CPU core revision and the company
options field do donate the SOC chip type, so we need to add an extra
field to the "pridtab" structure to identify these CPUs.

Overhaul the emulation facility. We do this by:

- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
emulated instructions
- cleaning up emulation dispatch in trap()

Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.

Tested on r3k with and without SOFTFLOAT enabled.

Add the 20Kc processor ID.

For the CP0 status register bit definitions- add the MX, PX and NMI bits
and rename TLB_SHUTDOWN and SOFT_RESET to TS and SR (the abbreviations
in the MIPS documentation).

XXX: this file really needs to be cleaned up one day...

Standardise on the name "MIPS_SR_BEV" instead of a couple of different
#defines for the same status bit.

branches: 1.50.4;
Add R4400 reg 0x60 to the MIPS CPU table.
From PR port-mips/15894 from Thilo Manske.

Add support for MIPS32 and MIPS64 architectures:
- Add XKPHYS macros (from Broadcom Corp).
- Add some r5900 register bit definitions.
- Add extra exception vector addresses for mips32/mips64 and r5900.
- Make the mips cp0 register definitions available from both asm and C.
- Add some Alchemy and Sandcraft CPU ids.
- Add r3000, tx39xx and r4x00 CPU revision ids.
- Remove defines for the number of TLBs on some CPUs.

R4000/R4400 always detects virtual alias as if
primary cache size is 32KB. Actual primary cache size
is ignored wrt VCED/VCEI.

branches: 1.47.4;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.

Describe the widths of various coprocessor 0 registers (for mips1,
mips3, mips32 and mips64).

_Never_ make a cosmetic change to a comment without test-compiling...

Add some MIPS, Alchemy and SiByte CPU PRIDs (from oss.sgi.com).

branches: 1.43.2;
PRiD 0x18 is shared by RC32334, 332 and 355. These SoCs are
distinguished by SYSID register in the system controller. Note
that PRiD 0x20 is for a standalone RC32364 processor which has the
same 32300 core inside. Rather better to name them MIPS32 ISA.

Pasto.

Add PRiD 0x18 for IDT RC32332/RC32334 processors.

Add the processor IDs for the 4Kc and 5Kc CPUs and some MIPS32/64
coprocessor 0 registers.

Add PRiD register imp value 0x2d for Toshiba TX4900 family.

branches: 1.38.2;
Correct a few cpu/fpu ids.

Use only one TLB entry to wire down process's USPACE since it's
now guranteed to be aligned on 8KB boundary in kernel virutal
address. Retain one more free TLB entry.

IDT32364's Config register uses a different base for IC/DC (instruction
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).

abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).

XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h

if MIPS3_ENABLE_CLOCK_INTR is defined, set MIPS3_[HARD_]INT_MASK
appropriately. This supports ports that use the internal clock.
Add 2 diag register defines that are specific to QED processors.

branches: 1.34.2;
Decrease MIPS3_TLB_WIRED_ENTRIES from 8 to 2,
and rename it to MIPS3_TLB_WIRED_UPAGES.
The value of wired register becomes variable on arc port,
and arc is the only mips3 port which uses the wired TLB entries 2..7.

Typo.

branches: 1.32.2;
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.

Add R12K PRID.

Add QED RM7000 PrID.

Remove FPU PRIDs that are identical to the CPU ones.

Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.

Garbage collect MIPS_SR_INT_ENAB/MIPS_SR_INT_ENA_CUR definitions.

Add macro for MIPS_PHYS_MASK and document use of bits in system status
registers.

FIX:
port-mips/9016 [serious/medium]:
MIPS FPU emulator points wrong epc on exception case

Responsible: port-mips-maintainer (NetBSD/mips Portmasters)
State: open
Class: sw-bug
Originator: Shuichiro URATA
Release: current 12/11/1999
Arrival-Date: Fri Dec 17 10:18:00 1999
commit patch
http://www.a-r.org/~ur/softfloat1211.diff.gz
by Shuichiro URATA (ur@a-r.org)

TX3912/22 support. ENABLE_MIPS_TX3900 enables it.

branches: 1.23.2; 1.23.8;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */

- Redefine symbols and parameters to represent CPU design with MIPS
nomenclature, retaining the old heritage.
- Remove API-related definitions for now obsolete utiltity routines.

- MIPS processors do not impose inclusive (nesting) interrupt levels with
their interrupt lines. The notion and implemention of 'spl' are left
for how target ports approach to it.

Nuke register and remove trailling white space.

branches: 1.19.4;
- Add NEC Vr5400 processor ID.

- Update 'cpuregs.h' and decline 'cpuarch.h'.

- Fix an error in primary cache line size detection logic; when IC and/or DC
bit is 1, then line size is 32. Otherwise, 16.

branches: 1.16.2;
More patches for ARC from Noriyuki Soda:
* commit isapnpvar.h changes required for ARC to support plain isa.
* fixup mistake over mips/include/cpuregs.h.
* mips/mips_machdep.c:
set L2 cache-size for arc, cleanup use of L2cache present
vs L2 cache-size variables. check for no L2 cache on kernels
configured to require one. misc cleanups.
* mips/mpis/trap.c: more locore stack-traceback label cleanup.
XXX Locore callbacks for mips3, mips4, r4600 cacheflush need more work.

Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.

define mips3 COUNT and COMPARE cp0 registers (onchip cycle counter)

* Change Sprite MACH_xxx prefix to MIPS_xxx.

* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
(more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).

Final changes for configuring MIPS1 and MIPS3 in a single kernel.

* cpuregs.h:
rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
Add compile-time MIPS3-only, compile-time MIPS1-only, and
runtime (both) definitions for number of TLB ASIDs (tlb pids)
and shift count to extract a TLB pid.

* locore.h:
Delete unused vector slot for indexed TLB writes.
mips1 and mips3 TLBs are different enough that we have
to break them out at the caller anyway.

* Add compile-time MIPS3-only andcompile-time MIPS1-only
macros to call locore functions directly by name.
Use the existing method table only if

* mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
Use MIPS3_ or MIPS1_ specific names for TLB pids in
mips3 and mips1 specific code paths (e.g., creating the kernel stack
for process 0).

Add `options MIPS3' to pmax/conf/GENERIC.

More mips1/mips3 changes to cpuregs.h and psl.h:
* cpuregs.h:
Delete unused VMMACH_ names (e.g., duplicates of PTE bits in pte.h).
Change remaining VMMACH_xxx names to MIPS1_xxx or MIPS3_xx.
Fold remaining compile-time definitions into a single #ifdef MIPS3.

* Use MIPS1_ names in locore_r2000.S, mips3_ names in locore_r4000.S

* Garbage-collect MachHitFlushDCache()

* psl.h:
use MIPS1_, MIPS3_ symbolic names for Cause register bits.
change _R3K to MIPS1_, _R4K to MIPS3. Conditionalize for mips1 only,
mips3 only, or when both are defined, use runtime CPUISMIPS3 test.

Fix idempotent inclusion test macro: _MACHCONST -> _MIPS_CPUREGS_H_
to avoid collision with obsolete Sprite-derived NetBSD/pica header file.

Garbage-collect MIPS_3K_xxx, MIPS_4K_xxx outidde mips/include/cpuregs.h:
MIPS_3K_xxx -> MIPS1_xxx
MIPS_4K_xxx -> MIPS3_xxx

More merged MIPS1/MIPS3 support: still only allows single-architecture
support.

Fix typo.

Add defines for increasing SPL levels, assuming devices are wired up
in to CPU interrupt pins in order of increasing priority.

Resolve all differences between the Pica and pmax versions of machConst.h:
* add "MIPS_3k_" for the MIPS-I r[23]000-specific register definitions.
* add "MIPS_4k_" for the MIPS-II/III r4000-specific register definitions.
* add #defines that provide the old values for locore and user
code, so the existing code continues to compile.

Regression-tested against the old headers by grepping for #define's,
editing out the defined symbols, and preprocessing with both the previous
machConst.h headers and this version.

Some unused symbols (CPU and FPU must-be-zero constants) are no longer defined.
Pica interrupt masks are now constant expressions instead of constant
values.

TODO:
* factor out the common #defines into src/sys/arch/mips.
* Get rid of the Sprite coding-style names (MACH_xxx).
* Separate out the r3k/r4k differences from the Pica/pmax differences.
* Figure out how to have a run-time choice of r3k vs. r4k support,
instead of a compile-time choice.

new RCS ID format.

bsd 4.4-lite pmax port as ported to NetBSD

upgrade to bsd 4.4-lite code base. only mod is rcsids

branches: 1.1.1;
Initial revision

s/definitons/definitions/

Update the FPU register names and bit definitions to something somewhat
modern (MIPS32/MIPS64) and convert to __BIT/__BITS.

branches: 1.110.4; 1.110.6;
Handle gas/gcc generating a break/trap 6 for integer overflow and
break/trap 7 for integer divide by zero and setting the SIGFPE
si_code of FPE_INTOVF or FPE_INTDIV respectively. The break/trap
6/7 seems to have existed since the early days of MIPS but not
well documented anywhere.

Fixes ATF lib/libc/gen/t_siginfo::sigfpe_int .

branches: 1.109.2;
Remove bogus duplicate MIPS_COP_0_CONTEXT definition, it's not a MIPS32/64
specific reg and we already define MIPS_COP_0_TLB_CONTEXT elsewhere.

Add a few more perfcnt CP0 registers.

Add two cnMIPS III COP0 register names.

Add definitions for the CP0 WatchLo/WatchHi registers.

#define<tab>
Nuke trailing whitespace.

Add CP0 Config Registers 6 and 7.

Remove mostly duplicate MIPS spec CP0 regs from octeon_corereg.h, move
the Cavium specific CP0 regs to <mips/cpuregs.h> as done for other core
specific regs.

Expose the width of the MIPS_EBASE_CPUNUM bitfield for asm code.

Add an extra bitfield in MIPS_COP_0_EBASE.

Remove a magic number.

Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.

Add CX73xx and CXF75xx Cavium Octeon PRIDs.

Add PRID definition for newer SiByte SB1 cores (rev 0x11).
Add a constant for SiByte/BCRM cacheable coherent TLB cache attribute.

Trailing whitespace

branches: 1.95.8;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Add a few MIPS32 R3 bits

Add MIPS 1074K

Define COP0 register that use select value in <mips/cpuregs.h>
Use those new definitions

Rework cavium support in preparation for MULTIPROCESSOR support

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

branches: 1.89.2;
deal with Ingenic XBurst CPUs

branches: 1.88.12;
Add Broadcom BCM3302 CPU to the table.

support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs

loongson2f support:
- Add some loongson2 definitions to cpuregs.h, from OpenBSD
- Make sure that the at register is useable before every jump register
instruction (exept when register is k0 or k1) because -mfix-loongson2f-btb
needs the at register for its workaround
- add code to mips_fixup.c to handle the instructions added by
-mfix-loongson2f-btb
- Add a ls2-specific tlb miss handler: it doesn't have separate handler
for the xtlbmiss exeption.
- Fixes for some #ifdef MIPS3_LOONGSON2 assembly code (using the wrong
register)

Add Loongson2 DIAG register definitions (partial)

Add define for loongson2 DIAG register

Fix some comments.

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.

branches: 1.78.2; 1.78.4; 1.78.6;
Spell "exception" properly.

branches: 1.77.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

LOONGSON2 is a MIPS III

Add Loongson2 chip ids

branches: 1.74.10; 1.74.28;
Add PrID's for MIPS's 24K, 24KE, 34K and 74K cores.

From Alexander Voropay in mail to port-mips@.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Recognise the R2000A cpu as found in some pmaxen.

From Dennis Grevenstein on port-pmax@.

branches: 1.71.6; 1.71.12; 1.71.20; 1.71.22; 1.71.30; 1.71.32; 1.71.34;
Don't cast pointers using unsigned and/or int. Use intptr_t or uintptr_t
as appropriate.

Fix typo in MIPS3_SR_EIE.
From Anders Gavare.

branches: 1.69.4; 1.69.6; 1.69.8; 1.69.12;
Add basic support for Alchemy Au1550 processor (CPU and devices).
Patch contributed by Garrett D'Amore in PR port-evbmips/32030.

merge ktrace-lwp.

Remove unused and incorrect MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2()
macro.

Check MIPS3_CONFIG_CS and adjust csizebase at runtime on MIPS_R4100 CPUs,
and remove "XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY" part
from cpuregs.h. Tested on gxemul.

BTW, cache.c doesn't have MIPS_RC32364 config which was added
in mips_machdep.c rev 1.101?

branches: 1.65.14; 1.65.16;
Add some more MTI CPU ids.

- Add MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2() macro.
- Add definitions of the MIPS4 config register.

From Christopher SEKIYA.

Add another R4000 CPU revision ID. From Christopher SEKIYA.

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.61.2;
Change MIPS3_SR_FR_32 to MIPS3_SR_FR. Both the old R4000 manual and the
current MIPS64 manuals don't use the "32" in the bit name.

Remove definitions and usage of MIPS_COP_0_STATUS_REG and
MIPS_COP_0_CAUSE_REG - use MIPS_COP_0_STATUS and MIPS_COP_0_CAUSE
instead.

Add the MIPS3_CONFIG_SE (name taken from Rm52xx manual) bit, which is the
external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k. If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.

Also, update sgimips code to use the new name.

Define COP0_HAZARD_FPUENABLE as four nops.
Include <mips/sb1regs.h> if MIPS64_SB1 is defined.

Add two PRiD values.
- 0x55 for NEC Vr5500. ISA might be MIPS64.
- 0x38 for Toshiba TX79. This has thirty-two 128bit GPRs while
maintaining 32bit only virtual address space. Any of pointer related
registers have 32bit.

Add the Toshiba TX4927 CPU.

Add support for detecting Alchemy Semiconductor CPUs. Alchemy use the
processor ID field to donote the CPU core revision and the company
options field do donate the SOC chip type, so we need to add an extra
field to the "pridtab" structure to identify these CPUs.

Overhaul the emulation facility. We do this by:

- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
emulated instructions
- cleaning up emulation dispatch in trap()

Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.

Tested on r3k with and without SOFTFLOAT enabled.

Add the 20Kc processor ID.

For the CP0 status register bit definitions- add the MX, PX and NMI bits
and rename TLB_SHUTDOWN and SOFT_RESET to TS and SR (the abbreviations
in the MIPS documentation).

XXX: this file really needs to be cleaned up one day...

Standardise on the name "MIPS_SR_BEV" instead of a couple of different
#defines for the same status bit.

branches: 1.50.4;
Add R4400 reg 0x60 to the MIPS CPU table.
From PR port-mips/15894 from Thilo Manske.

Add support for MIPS32 and MIPS64 architectures:
- Add XKPHYS macros (from Broadcom Corp).
- Add some r5900 register bit definitions.
- Add extra exception vector addresses for mips32/mips64 and r5900.
- Make the mips cp0 register definitions available from both asm and C.
- Add some Alchemy and Sandcraft CPU ids.
- Add r3000, tx39xx and r4x00 CPU revision ids.
- Remove defines for the number of TLBs on some CPUs.

R4000/R4400 always detects virtual alias as if
primary cache size is 32KB. Actual primary cache size
is ignored wrt VCED/VCEI.

branches: 1.47.4;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.

Describe the widths of various coprocessor 0 registers (for mips1,
mips3, mips32 and mips64).

_Never_ make a cosmetic change to a comment without test-compiling...

Add some MIPS, Alchemy and SiByte CPU PRIDs (from oss.sgi.com).

branches: 1.43.2;
PRiD 0x18 is shared by RC32334, 332 and 355. These SoCs are
distinguished by SYSID register in the system controller. Note
that PRiD 0x20 is for a standalone RC32364 processor which has the
same 32300 core inside. Rather better to name them MIPS32 ISA.

Pasto.

Add PRiD 0x18 for IDT RC32332/RC32334 processors.

Add the processor IDs for the 4Kc and 5Kc CPUs and some MIPS32/64
coprocessor 0 registers.

Add PRiD register imp value 0x2d for Toshiba TX4900 family.

branches: 1.38.2;
Correct a few cpu/fpu ids.

Use only one TLB entry to wire down process's USPACE since it's
now guranteed to be aligned on 8KB boundary in kernel virutal
address. Retain one more free TLB entry.

IDT32364's Config register uses a different base for IC/DC (instruction
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).

abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).

XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h

if MIPS3_ENABLE_CLOCK_INTR is defined, set MIPS3_[HARD_]INT_MASK
appropriately. This supports ports that use the internal clock.
Add 2 diag register defines that are specific to QED processors.

branches: 1.34.2;
Decrease MIPS3_TLB_WIRED_ENTRIES from 8 to 2,
and rename it to MIPS3_TLB_WIRED_UPAGES.
The value of wired register becomes variable on arc port,
and arc is the only mips3 port which uses the wired TLB entries 2..7.

Typo.

branches: 1.32.2;
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.

Add R12K PRID.

Add QED RM7000 PrID.

Remove FPU PRIDs that are identical to the CPU ones.

Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.

Garbage collect MIPS_SR_INT_ENAB/MIPS_SR_INT_ENA_CUR definitions.

Add macro for MIPS_PHYS_MASK and document use of bits in system status
registers.

FIX:
port-mips/9016 [serious/medium]:
MIPS FPU emulator points wrong epc on exception case

Responsible: port-mips-maintainer (NetBSD/mips Portmasters)
State: open
Class: sw-bug
Originator: Shuichiro URATA
Release: current 12/11/1999
Arrival-Date: Fri Dec 17 10:18:00 1999
commit patch
http://www.a-r.org/~ur/softfloat1211.diff.gz
by Shuichiro URATA (ur@a-r.org)

TX3912/22 support. ENABLE_MIPS_TX3900 enables it.

branches: 1.23.2; 1.23.8;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */

- Redefine symbols and parameters to represent CPU design with MIPS
nomenclature, retaining the old heritage.
- Remove API-related definitions for now obsolete utiltity routines.

- MIPS processors do not impose inclusive (nesting) interrupt levels with
their interrupt lines. The notion and implemention of 'spl' are left
for how target ports approach to it.

Nuke register and remove trailling white space.

branches: 1.19.4;
- Add NEC Vr5400 processor ID.

- Update 'cpuregs.h' and decline 'cpuarch.h'.

- Fix an error in primary cache line size detection logic; when IC and/or DC
bit is 1, then line size is 32. Otherwise, 16.

branches: 1.16.2;
More patches for ARC from Noriyuki Soda:
* commit isapnpvar.h changes required for ARC to support plain isa.
* fixup mistake over mips/include/cpuregs.h.
* mips/mips_machdep.c:
set L2 cache-size for arc, cleanup use of L2cache present
vs L2 cache-size variables. check for no L2 cache on kernels
configured to require one. misc cleanups.
* mips/mpis/trap.c: more locore stack-traceback label cleanup.
XXX Locore callbacks for mips3, mips4, r4600 cacheflush need more work.

Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.

define mips3 COUNT and COMPARE cp0 registers (onchip cycle counter)

* Change Sprite MACH_xxx prefix to MIPS_xxx.

* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
(more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).

Final changes for configuring MIPS1 and MIPS3 in a single kernel.

* cpuregs.h:
rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
Add compile-time MIPS3-only, compile-time MIPS1-only, and
runtime (both) definitions for number of TLB ASIDs (tlb pids)
and shift count to extract a TLB pid.

* locore.h:
Delete unused vector slot for indexed TLB writes.
mips1 and mips3 TLBs are different enough that we have
to break them out at the caller anyway.

* Add compile-time MIPS3-only andcompile-time MIPS1-only
macros to call locore functions directly by name.
Use the existing method table only if

* mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
Use MIPS3_ or MIPS1_ specific names for TLB pids in
mips3 and mips1 specific code paths (e.g., creating the kernel stack
for process 0).

Add `options MIPS3' to pmax/conf/GENERIC.

More mips1/mips3 changes to cpuregs.h and psl.h:
* cpuregs.h:
Delete unused VMMACH_ names (e.g., duplicates of PTE bits in pte.h).
Change remaining VMMACH_xxx names to MIPS1_xxx or MIPS3_xx.
Fold remaining compile-time definitions into a single #ifdef MIPS3.

* Use MIPS1_ names in locore_r2000.S, mips3_ names in locore_r4000.S

* Garbage-collect MachHitFlushDCache()

* psl.h:
use MIPS1_, MIPS3_ symbolic names for Cause register bits.
change _R3K to MIPS1_, _R4K to MIPS3. Conditionalize for mips1 only,
mips3 only, or when both are defined, use runtime CPUISMIPS3 test.

Fix idempotent inclusion test macro: _MACHCONST -> _MIPS_CPUREGS_H_
to avoid collision with obsolete Sprite-derived NetBSD/pica header file.

Garbage-collect MIPS_3K_xxx, MIPS_4K_xxx outidde mips/include/cpuregs.h:
MIPS_3K_xxx -> MIPS1_xxx
MIPS_4K_xxx -> MIPS3_xxx

More merged MIPS1/MIPS3 support: still only allows single-architecture
support.

Fix typo.

Add defines for increasing SPL levels, assuming devices are wired up
in to CPU interrupt pins in order of increasing priority.

Resolve all differences between the Pica and pmax versions of machConst.h:
* add "MIPS_3k_" for the MIPS-I r[23]000-specific register definitions.
* add "MIPS_4k_" for the MIPS-II/III r4000-specific register definitions.
* add #defines that provide the old values for locore and user
code, so the existing code continues to compile.

Regression-tested against the old headers by grepping for #define's,
editing out the defined symbols, and preprocessing with both the previous
machConst.h headers and this version.

Some unused symbols (CPU and FPU must-be-zero constants) are no longer defined.
Pica interrupt masks are now constant expressions instead of constant
values.

TODO:
* factor out the common #defines into src/sys/arch/mips.
* Get rid of the Sprite coding-style names (MACH_xxx).
* Separate out the r3k/r4k differences from the Pica/pmax differences.
* Figure out how to have a run-time choice of r3k vs. r4k support,
instead of a compile-time choice.

new RCS ID format.

bsd 4.4-lite pmax port as ported to NetBSD

upgrade to bsd 4.4-lite code base. only mod is rcsids

branches: 1.1.1;
Initial revision

Update the FPU register names and bit definitions to something somewhat
modern (MIPS32/MIPS64) and convert to __BIT/__BITS.

Handle gas/gcc generating a break/trap 6 for integer overflow and
break/trap 7 for integer divide by zero and setting the SIGFPE
si_code of FPE_INTOVF or FPE_INTDIV respectively. The break/trap
6/7 seems to have existed since the early days of MIPS but not
well documented anywhere.

Fixes ATF lib/libc/gen/t_siginfo::sigfpe_int .

branches: 1.109.2;
Remove bogus duplicate MIPS_COP_0_CONTEXT definition, it's not a MIPS32/64
specific reg and we already define MIPS_COP_0_TLB_CONTEXT elsewhere.

Add a few more perfcnt CP0 registers.

Add two cnMIPS III COP0 register names.

Add definitions for the CP0 WatchLo/WatchHi registers.

#define<tab>
Nuke trailing whitespace.

Add CP0 Config Registers 6 and 7.

Remove mostly duplicate MIPS spec CP0 regs from octeon_corereg.h, move
the Cavium specific CP0 regs to <mips/cpuregs.h> as done for other core
specific regs.

Expose the width of the MIPS_EBASE_CPUNUM bitfield for asm code.

Add an extra bitfield in MIPS_COP_0_EBASE.

Remove a magic number.

Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.

Add CX73xx and CXF75xx Cavium Octeon PRIDs.

Add PRID definition for newer SiByte SB1 cores (rev 0x11).
Add a constant for SiByte/BCRM cacheable coherent TLB cache attribute.

Trailing whitespace

branches: 1.95.8;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Add a few MIPS32 R3 bits

Add MIPS 1074K

Define COP0 register that use select value in <mips/cpuregs.h>
Use those new definitions

Rework cavium support in preparation for MULTIPROCESSOR support

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

branches: 1.89.2;
deal with Ingenic XBurst CPUs

branches: 1.88.12;
Add Broadcom BCM3302 CPU to the table.

support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs

loongson2f support:
- Add some loongson2 definitions to cpuregs.h, from OpenBSD
- Make sure that the at register is useable before every jump register
instruction (exept when register is k0 or k1) because -mfix-loongson2f-btb
needs the at register for its workaround
- add code to mips_fixup.c to handle the instructions added by
-mfix-loongson2f-btb
- Add a ls2-specific tlb miss handler: it doesn't have separate handler
for the xtlbmiss exeption.
- Fixes for some #ifdef MIPS3_LOONGSON2 assembly code (using the wrong
register)

Add Loongson2 DIAG register definitions (partial)

Add define for loongson2 DIAG register

Fix some comments.

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.

branches: 1.78.2; 1.78.4; 1.78.6;
Spell "exception" properly.

branches: 1.77.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

LOONGSON2 is a MIPS III

Add Loongson2 chip ids

branches: 1.74.10; 1.74.28;
Add PrID's for MIPS's 24K, 24KE, 34K and 74K cores.

From Alexander Voropay in mail to port-mips@.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Recognise the R2000A cpu as found in some pmaxen.

From Dennis Grevenstein on port-pmax@.

branches: 1.71.6; 1.71.12; 1.71.20; 1.71.22; 1.71.30; 1.71.32; 1.71.34;
Don't cast pointers using unsigned and/or int. Use intptr_t or uintptr_t
as appropriate.

Fix typo in MIPS3_SR_EIE.
From Anders Gavare.

branches: 1.69.4; 1.69.6; 1.69.8; 1.69.12;
Add basic support for Alchemy Au1550 processor (CPU and devices).
Patch contributed by Garrett D'Amore in PR port-evbmips/32030.

merge ktrace-lwp.

Remove unused and incorrect MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2()
macro.

Check MIPS3_CONFIG_CS and adjust csizebase at runtime on MIPS_R4100 CPUs,
and remove "XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY" part
from cpuregs.h. Tested on gxemul.

BTW, cache.c doesn't have MIPS_RC32364 config which was added
in mips_machdep.c rev 1.101?

branches: 1.65.14; 1.65.16;
Add some more MTI CPU ids.

- Add MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2() macro.
- Add definitions of the MIPS4 config register.

From Christopher SEKIYA.

Add another R4000 CPU revision ID. From Christopher SEKIYA.

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.61.2;
Change MIPS3_SR_FR_32 to MIPS3_SR_FR. Both the old R4000 manual and the
current MIPS64 manuals don't use the "32" in the bit name.

Remove definitions and usage of MIPS_COP_0_STATUS_REG and
MIPS_COP_0_CAUSE_REG - use MIPS_COP_0_STATUS and MIPS_COP_0_CAUSE
instead.

Add the MIPS3_CONFIG_SE (name taken from Rm52xx manual) bit, which is the
external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k. If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.

Also, update sgimips code to use the new name.

Define COP0_HAZARD_FPUENABLE as four nops.
Include <mips/sb1regs.h> if MIPS64_SB1 is defined.

Add two PRiD values.
- 0x55 for NEC Vr5500. ISA might be MIPS64.
- 0x38 for Toshiba TX79. This has thirty-two 128bit GPRs while
maintaining 32bit only virtual address space. Any of pointer related
registers have 32bit.

Add the Toshiba TX4927 CPU.

Add support for detecting Alchemy Semiconductor CPUs. Alchemy use the
processor ID field to donote the CPU core revision and the company
options field do donate the SOC chip type, so we need to add an extra
field to the "pridtab" structure to identify these CPUs.

Overhaul the emulation facility. We do this by:

- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
emulated instructions
- cleaning up emulation dispatch in trap()

Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.

Tested on r3k with and without SOFTFLOAT enabled.

Add the 20Kc processor ID.

For the CP0 status register bit definitions- add the MX, PX and NMI bits
and rename TLB_SHUTDOWN and SOFT_RESET to TS and SR (the abbreviations
in the MIPS documentation).

XXX: this file really needs to be cleaned up one day...

Standardise on the name "MIPS_SR_BEV" instead of a couple of different
#defines for the same status bit.

branches: 1.50.4;
Add R4400 reg 0x60 to the MIPS CPU table.
From PR port-mips/15894 from Thilo Manske.

Add support for MIPS32 and MIPS64 architectures:
- Add XKPHYS macros (from Broadcom Corp).
- Add some r5900 register bit definitions.
- Add extra exception vector addresses for mips32/mips64 and r5900.
- Make the mips cp0 register definitions available from both asm and C.
- Add some Alchemy and Sandcraft CPU ids.
- Add r3000, tx39xx and r4x00 CPU revision ids.
- Remove defines for the number of TLBs on some CPUs.

R4000/R4400 always detects virtual alias as if
primary cache size is 32KB. Actual primary cache size
is ignored wrt VCED/VCEI.

branches: 1.47.4;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.

Describe the widths of various coprocessor 0 registers (for mips1,
mips3, mips32 and mips64).

_Never_ make a cosmetic change to a comment without test-compiling...

Add some MIPS, Alchemy and SiByte CPU PRIDs (from oss.sgi.com).

branches: 1.43.2;
PRiD 0x18 is shared by RC32334, 332 and 355. These SoCs are
distinguished by SYSID register in the system controller. Note
that PRiD 0x20 is for a standalone RC32364 processor which has the
same 32300 core inside. Rather better to name them MIPS32 ISA.

Pasto.

Add PRiD 0x18 for IDT RC32332/RC32334 processors.