cpuregs.h revision 1.26
1/* $NetBSD: cpuregs.h,v 1.26 1999/12/27 20:05:06 castor Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 39 * 40 * machConst.h -- 41 * 42 * Machine dependent constants. 43 * 44 * Copyright (C) 1989 Digital Equipment Corporation. 45 * Permission to use, copy, modify, and distribute this software and 46 * its documentation for any purpose and without fee is hereby granted, 47 * provided that the above copyright notice appears in all copies. 48 * Digital Equipment Corporation makes no representations about the 49 * suitability of this software for any purpose. It is provided "as is" 50 * without express or implied warranty. 51 * 52 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 53 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 54 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 55 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 56 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 57 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 58 */ 59 60#ifndef _MIPS_CPUREGS_H_ 61#define _MIPS_CPUREGS_H_ 62 63/* 64 * Address space. 65 * 32-bit mips CPUS partition their 32-bit address space into four segments: 66 * 67 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 68 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 69 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 70 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 71 * 72 * mips1 physical memory is limited to 512Mbytes, which is 73 * doubly mapped in kseg0 (cached) and kseg1 (uncached.) 74 * Caching of mapped addresses is controlled by bits in the TLB entry. 75 */ 76 77#define MIPS_KUSEG_START 0x0 78#define MIPS_KSEG0_START 0x80000000 79#define MIPS_KSEG1_START 0xa0000000 80#define MIPS_KSEG2_START 0xc0000000 81#define MIPS_MAX_MEM_ADDR 0xbe000000 82#define MIPS_RESERVED_ADDR 0xbfc80000 83 84#define MIPS_PHYS_MASK 0x1fffffff 85 86#define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 87#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START) 88#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 89#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START) 90 91/* Map virtual address to index in mips3 r4k virtually-indexed cache */ 92#define MIPS3_VA_TO_CINDEX(x) \ 93 ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START) 94 95 96/* 97 * The bits in the cause register. 98 * 99 * Bits common to r3000 and r4000: 100 * 101 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 102 * MIPS_CR_COP_ERR Coprocessor error. 103 * MIPS_CR_IP Interrupt pending bits defined below. 104 * (same meaning as in CAUSE register). 105 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 106 * 107 * Differences: 108 * r3k has 4 bits of execption type, r4k has 5 bits. 109 */ 110#define MIPS_CR_BR_DELAY 0x80000000 111#define MIPS_CR_COP_ERR 0x30000000 112#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 113#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 114#define MIPS_CR_IP 0x0000FF00 115#define MIPS_CR_EXC_CODE_SHIFT 2 116 117/* 118 * The bits in the status register. All bits are active when set to 1. 119 * 120 * R3000 status register fields: 121 * MIPS_SR_CO_USABILITY Control the usability of the four coprocessors. 122 * MIPS_SR_BOOT_EXC_VEC Use alternate exception vectors. 123 * MIPS_SR_TLB_SHUTDOWN TLB disabled. 124 * 125 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 126 * 127 * Differences: 128 * r3k has cache control is via frobbing SR register bits, whereas the 129 * r4k cache control is via explicit instructions. 130 * r3k has a 3-entry stack of kernel/user bits, whereas the 131 * r4k has kernel/supervisor/user. 132 */ 133#define MIPS_SR_COP_USABILITY 0xf0000000 134#define MIPS_SR_COP_0_BIT 0x10000000 135#define MIPS_SR_COP_1_BIT 0x20000000 136 137 /* r4k and r3k differences, see below */ 138 139#define MIPS_SR_BOOT_EXC_VEC 0x00400000 140#define MIPS_SR_TLB_SHUTDOWN 0x00200000 141 142 /* r4k and r3k differences, see below */ 143 144#define MIPS_SR_INT_IE 0x00000001 145/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 146/*#define MIPS_SR_INT_MASK 0x0000ff00*/ 147 148#define MIPS_SR_INT_ENAB MIPS_SR_INT_IE /* backwards compatibility */ 149#define MIPS_SR_INT_ENA_CUR MIPS_SR_INT_IE /* backwards compatibility */ 150 151 152 153/* 154 * The R2000/R3000-specific status register bit definitions. 155 * all bits are active when set to 1. 156 * 157 * MIPS_SR_PARITY_ERR Parity error. 158 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 159 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 160 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 161 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 162 * Interrupt enable bits defined below. 163 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 164 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 165 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 166 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 167 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 168 */ 169 170#define MIPS1_PARITY_ERR 0x00100000 171#define MIPS1_CACHE_MISS 0x00080000 172#define MIPS1_PARITY_ZERO 0x00040000 173#define MIPS1_SWAP_CACHES 0x00020000 174#define MIPS1_ISOL_CACHES 0x00010000 175 176#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 177#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 178#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 179#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 180#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 181 182/* backwards compatibility */ 183#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 184#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 185#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 186#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 187#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 188 189#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 190#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 191#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 192#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 193#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 194 195/* 196 * R4000 status register bit definitons, 197 * where different from r2000/r3000. 198 */ 199#define MIPS3_SR_XX 0x80000000 200#define MIPS3_SR_RP 0x08000000 201#define MIPS3_SR_FR_32 0x04000000 202#define MIPS3_SR_RE 0x02000000 203 204#define MIPS3_SR_SOFT_RESET 0x00100000 205#define MIPS3_SR_DIAG_CH 0x00040000 206#define MIPS3_SR_DIAG_CE 0x00020000 207#define MIPS3_SR_DIAG_PE 0x00010000 208#define MIPS3_SR_KX 0x00000080 209#define MIPS3_SR_SX 0x00000040 210#define MIPS3_SR_UX 0x00000020 211#define MIPS3_SR_KSU_MASK 0x00000018 212#define MIPS3_SR_KSU_USER 0x00000010 213#define MIPS3_SR_KSU_SUPER 0x00000008 214#define MIPS3_SR_KSU_KERNEL 0x00000000 215#define MIPS3_SR_ERL 0x00000004 216#define MIPS3_SR_EXL 0x00000002 217 218#define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET 219#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 220#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 221#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 222#define MIPS_SR_KX MIPS3_SR_KX 223#define MIPS_SR_SX MIPS3_SR_SX 224#define MIPS_SR_UX MIPS3_SR_UX 225 226#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 227#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 228#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 229#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 230#define MIPS_SR_ERL MIPS3_SR_ERL 231#define MIPS_SR_EXL MIPS3_SR_EXL 232 233 234/* 235 * The interrupt masks. 236 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 237 */ 238#define MIPS_INT_MASK 0xff00 239#define MIPS_INT_MASK_5 0x8000 240#define MIPS_INT_MASK_4 0x4000 241#define MIPS_INT_MASK_3 0x2000 242#define MIPS_INT_MASK_2 0x1000 243#define MIPS_INT_MASK_1 0x0800 244#define MIPS_INT_MASK_0 0x0400 245#define MIPS_HARD_INT_MASK 0xfc00 246#define MIPS_SOFT_INT_MASK_1 0x0200 247#define MIPS_SOFT_INT_MASK_0 0x0100 248 249/* 250 * mips3 CPUs have on-chip timer at INT_MASK_5. We don't support it yet. 251 */ 252#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 253#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 254 255 256/* 257 * The bits in the context register. 258 */ 259#define MIPS1_CNTXT_PTE_BASE 0xFFE00000 260#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 261 262#define MIPS3_CNTXT_PTE_BASE 0xFF800000 263#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 264 265/* 266 * The bits in the MIPS3 config register. 267 * 268 * bit 0..5: R/W, Bit 6..31: R/O 269 */ 270 271/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 272#define MIPS3_CONFIG_K0_MASK 0x00000007 273 274/* 275 * R/W Update on Store Conditional 276 * 0: Store Conditional uses coherency algorithm specified by TLB 277 * 1: Store Conditional uses cacheable coherent update on write 278 */ 279#define MIPS3_CONFIG_CU 0x00000008 280 281#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 282#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 283#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 284 (((config) & (bit)) ? 32 : 16) 285 286#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 287#define MIPS3_CONFIG_DC_SHIFT 6 288#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 289#define MIPS3_CONFIG_IC_SHIFT 9 290#ifdef MIPS3_4100 /* VR4100 core */ 291#define MIPS3_CONFIG_CS 0x00001000 /* cache size mode indication*/ 292#define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \ 293 ((((config)&MIPS3_CONFIG_CS)?0x400:0x1000) << (((config) & (mask)) >> (shift))) 294#else 295#define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \ 296 (0x1000 << (((config) & (mask)) >> (shift))) 297#endif 298 299/* Block ordering: 0: sequential, 1: sub-block */ 300#define MIPS3_CONFIG_EB 0x00002000 301 302/* ECC mode - 0: ECC mode, 1: parity mode */ 303#define MIPS3_CONFIG_EM 0x00004000 304 305/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 306#define MIPS3_CONFIG_BE 0x00008000 307 308/* Dirty Shared coherency state - 0: enabled, 1: disabled */ 309#define MIPS3_CONFIG_SM 0x00010000 310 311/* Secondary Cache - 0: present, 1: not present */ 312#define MIPS3_CONFIG_SC 0x00020000 313 314/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 315#define MIPS3_CONFIG_EW_MASK 0x000c0000 316#define MIPS3_CONFIG_EW_SHIFT 18 317 318/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 319#define MIPS3_CONFIG_SW 0x00100000 320 321/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 322#define MIPS3_CONFIG_SS 0x00200000 323 324/* Secondary Cache line size */ 325#define MIPS3_CONFIG_SB_MASK 0x00c00000 326#define MIPS3_CONFIG_SB_SHIFT 22 327#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 328 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 329 330/* write back data rate */ 331#define MIPS3_CONFIG_EP_MASK 0x0f000000 332#define MIPS3_CONFIG_EP_SHIFT 24 333 334/* System clock ratio - this value is CPU dependent */ 335#define MIPS3_CONFIG_EC_MASK 0x70000000 336#define MIPS3_CONFIG_EC_SHIFT 28 337 338/* Master-Checker Mode - 1: enabled */ 339#define MIPS3_CONFIG_CM 0x80000000 340 341/* 342 * Location of exception vectors. 343 * 344 * Common vectors: reset and UTLB miss. 345 */ 346#define MIPS_RESET_EXC_VEC 0xBFC00000 347#define MIPS_UTLB_MISS_EXC_VEC 0x80000000 348 349/* 350 * R3000 general exception vector (everything else) 351 */ 352#define MIPS1_GEN_EXC_VEC 0x80000080 353 354/* 355 * R4000 MIPS-III exception vectors 356 */ 357#define MIPS3_XTLB_MISS_EXC_VEC 0x80000080 358#define MIPS3_CACHE_ERR_EXC_VEC 0x80000100 359#define MIPS3_GEN_EXC_VEC 0x80000180 360 361/* 362 * Coprocessor 0 registers: 363 * 364 * MIPS_COP_0_TLB_INDEX TLB index. 365 * MIPS_COP_0_TLB_RANDOM TLB random. 366 * MIPS_COP_0_TLB_LOW r3k TLB entry low. 367 * MIPS_COP_0_TLB_LO0 r4k TLB entry low. 368 * MIPS_COP_0_TLB_LO1 r4k TLB entry low, extended. 369 * MIPS_COP_0_TLB_CONTEXT TLB context. 370 * MIPS_COP_0_BAD_VADDR Bad virtual address. 371 * MIPS_COP_0_TLB_HI TLB entry high. 372 * MIPS_COP_0_STATUS Status register. 373 * MIPS_COP_0_CAUSE Exception cause register. 374 * MIPS_COP_0_EXC_PC Exception PC. 375 * MIPS_COP_0_PRID Processor revision identifier. 376 */ 377#define MIPS_COP_0_TLB_INDEX $0 378#define MIPS_COP_0_TLB_RANDOM $1 379 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 380 381#define MIPS_COP_0_TLB_CONTEXT $4 382 /* $5 and $6 new with MIPS-III */ 383#define MIPS_COP_0_BAD_VADDR $8 384#define MIPS_COP_0_TLB_HI $10 385#define MIPS_COP_0_STATUS_REG $12 386#define MIPS_COP_0_CAUSE_REG $13 387#define MIPS_COP_0_STATUS $12 388#define MIPS_COP_0_CAUSE $13 389#define MIPS_COP_0_EXC_PC $14 390#define MIPS_COP_0_PRID $15 391 392 393/* MIPS-I */ 394#define MIPS_COP_0_TLB_LOW $2 395 396/* MIPS-III */ 397#define MIPS_COP_0_TLB_LO0 $2 398#define MIPS_COP_0_TLB_LO1 $3 399 400#define MIPS_COP_0_TLB_PG_MASK $5 401#define MIPS_COP_0_TLB_WIRED $6 402 403#define MIPS_COP_0_COUNT $9 404#define MIPS_COP_0_COMPARE $11 405 406#define MIPS_COP_0_CONFIG $16 407#define MIPS_COP_0_LLADDR $17 408#define MIPS_COP_0_WATCH_LO $18 409#define MIPS_COP_0_WATCH_HI $19 410#define MIPS_COP_0_TLB_XCONTEXT $20 411#define MIPS_COP_0_ECC $26 412#define MIPS_COP_0_CACHE_ERR $27 413#define MIPS_COP_0_TAG_LO $28 414#define MIPS_COP_0_TAG_HI $29 415#define MIPS_COP_0_ERROR_PC $30 416 417 418 419/* 420 * Values for the code field in a break instruction. 421 */ 422#define MIPS_BREAK_INSTR 0x0000000d 423#define MIPS_BREAK_VAL_MASK 0x03ff0000 424#define MIPS_BREAK_VAL_SHIFT 16 425#define MIPS_BREAK_KDB_VAL 512 426#define MIPS_BREAK_SSTEP_VAL 513 427#define MIPS_BREAK_BRKPT_VAL 514 428#define MIPS_BREAK_SOVER_VAL 515 429#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 430 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 431#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 432 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 433#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 434 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 435#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 436 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 437 438/* 439 * Mininum and maximum cache sizes. 440 */ 441#define MIPS_MIN_CACHE_SIZE (16 * 1024) 442#define MIPS_MAX_CACHE_SIZE (256 * 1024) 443 444/* 445 * The floating point version and status registers. 446 */ 447#define MIPS_FPU_ID $0 448#define MIPS_FPU_CSR $31 449 450/* 451 * The floating point coprocessor status register bits. 452 */ 453#define MIPS_FPU_ROUNDING_BITS 0x00000003 454#define MIPS_FPU_ROUND_RN 0x00000000 455#define MIPS_FPU_ROUND_RZ 0x00000001 456#define MIPS_FPU_ROUND_RP 0x00000002 457#define MIPS_FPU_ROUND_RM 0x00000003 458#define MIPS_FPU_STICKY_BITS 0x0000007c 459#define MIPS_FPU_STICKY_INEXACT 0x00000004 460#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 461#define MIPS_FPU_STICKY_OVERFLOW 0x00000010 462#define MIPS_FPU_STICKY_DIV0 0x00000020 463#define MIPS_FPU_STICKY_INVALID 0x00000040 464#define MIPS_FPU_ENABLE_BITS 0x00000f80 465#define MIPS_FPU_ENABLE_INEXACT 0x00000080 466#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 467#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 468#define MIPS_FPU_ENABLE_DIV0 0x00000400 469#define MIPS_FPU_ENABLE_INVALID 0x00000800 470#define MIPS_FPU_EXCEPTION_BITS 0x0003f000 471#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 472#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 473#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 474#define MIPS_FPU_EXCEPTION_DIV0 0x00008000 475#define MIPS_FPU_EXCEPTION_INVALID 0x00010000 476#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 477#define MIPS_FPU_COND_BIT 0x00800000 478#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 479#define MIPS1_FPC_MBZ_BITS 0xff7c0000 480#define MIPS3_FPC_MBZ_BITS 0xfe7c0000 481 482 483/* 484 * Constants to determine if have a floating point instruction. 485 */ 486#define MIPS_OPCODE_SHIFT 26 487#define MIPS_OPCODE_C1 0x11 488#define MIPS_OPCODE_LWC1 0x31 489#define MIPS_OPCODE_LDC1 0x35 490#define MIPS_OPCODE_SWC1 0x39 491#define MIPS_OPCODE_SDC1 0x3d 492 493 494 495/* 496 * The low part of the TLB entry. 497 */ 498#define MIPS1_TLB_PFN 0xfffff000 499#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 500#define MIPS1_TLB_DIRTY_BIT 0x00000400 501#define MIPS1_TLB_VALID_BIT 0x00000200 502#define MIPS1_TLB_GLOBAL_BIT 0x00000100 503 504#define MIPS3_TLB_PFN 0x3fffffc0 505#define MIPS3_TLB_ATTR_MASK 0x00000038 506#define MIPS3_TLB_ATTR_SHIFT 3 507#define MIPS3_TLB_DIRTY_BIT 0x00000004 508#define MIPS3_TLB_VALID_BIT 0x00000002 509#define MIPS3_TLB_GLOBAL_BIT 0x00000001 510 511/* XXX XXX XXX */ 512#define MIPS1_TLB_PHYS_PAGE_SHIFT 12 513#define MIPS3_TLB_PHYS_PAGE_SHIFT 6 514#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 515#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 516#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 517#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 518/* XXX XXX XXX */ 519 520/* 521 * MIPS3_TLB_ATTR values - coherency algorithm: 522 * 0: cacheable, noncoherent, write-through, no write allocate 523 * 1: cacheable, noncoherent, write-through, write allocate 524 * 2: uncached 525 * 3: cacheable, noncoherent, write-back (noncoherent) 526 * 4: cacheable, coherent, write-back, exclusive (exclusive) 527 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 528 * 6: cacheable, coherent, write-back, update on write (update) 529 * 7: uncached, accelerated (gather STORE operations) 530 */ 531#define MIPS3_TLB_ATTR_WT 0 /* IDT */ 532#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 533#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 534#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 535#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 536#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 537#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 538#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 539 540 541/* 542 * The high part of the TLB entry. 543 */ 544#define MIPS1_TLB_VPN 0xfffff000 545#define MIPS1_TLB_PID 0x00000fc0 546#define MIPS1_TLB_PID_SHIFT 6 547 548#define MIPS3_TLB_VPN2 0xffffe000 549#define MIPS3_TLB_ASID 0x000000ff 550 551/* XXX XXX XXX */ 552#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 553#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 554#define MIPS3_TLB_PID MIPS3_TLB_ASID 555#define MIPS_TLB_VIRT_PAGE_SHIFT 12 556/* XXX XXX XXX */ 557 558/* 559 * r3000: shift count to put the index in the right spot. 560 */ 561#define MIPS1_TLB_INDEX_SHIFT 8 562 563/* 564 * The number of TLB entries and the first one that write random hits. 565 */ 566#define MIPS1_TLB_NUM_TLB_ENTRIES 64 567#define MIPS1_TLB_FIRST_RAND_ENTRY 8 568 569#define MIPS3_TLB_NUM_TLB_ENTRIES 48 570#define MIPS_R4300_TLB_NUM_TLB_ENTRIES 32 571#define MIPS3_TLB_WIRED_ENTRIES 8 /* XXX gross XXX */ 572 573 574/* 575 * The number of process id entries. 576 */ 577#define MIPS1_TLB_NUM_PIDS 64 578#define MIPS3_TLB_NUM_ASIDS 256 579 580/* 581 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 582 * 583 * XXX INT_MASK and HARD_INT_MASK are here only because we dont 584 * support the mips3 on-chip timer which is tied to INT_5. 585 */ 586 587#if !defined(MIPS3) && defined(MIPS1) 588#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 589#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 590#endif 591 592#if defined(MIPS3) && !defined(MIPS1) 593#define MIPS_TLB_PID_SHIFT 0 594#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 595#endif 596 597 598#if defined(MIPS1) && defined(MIPS3) 599#define MIPS_TLB_PID_SHIFT \ 600 ((CPUISMIPS3)? 0 : MIPS1_TLB_PID_SHIFT) 601 602#define MIPS_TLB_NUM_PIDS \ 603 ((CPUISMIPS3)? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 604 605#endif 606 607/* 608 * CPU processor revision ID 609 */ 610#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 611#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 612#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 613#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 614#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 615#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 616#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 CPU ISA I */ 617#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 618#define MIPS_R4200 0x0a /* NEC VR4200 CPU ISA III */ 619#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 620#define MIPS_R4100 0x0c /* NEC VR4100 CPU ISA III */ 621#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 622#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 623#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 624#define MIPS_R4650 0x22 /* !ID crash! QED R4650 CPU ISA III */ 625#define MIPS_TX3900 0x22 /* !ID crash! Toshiba R3000 CPU ISA I */ 626#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 627#define MIPS_RC32364 0x26 /* IDT RC32364 CPU ISA II */ 628#define MIPS_RM5230 0x28 /* QED RM5230 CPU ISA IV */ 629#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 CPU ISA III */ 630#define MIPS_R3SONY 0x21 /* ? Sony R3000 based CPU ISA I */ 631#define MIPS_R3NKK 0x23 /* ? NKK R3000 based CPU ISA I */ 632#define MIPS_R5400 0x54 /* NEC VR5400 CPU ISA IV */ 633 634/* 635 * FPU processor revision ID 636 */ 637#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 638#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 639#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 640#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 641#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 642#define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 643#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 644#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ 645#define MIPS_R4210 0x0a /* NEC VR4210 FPC ISA III */ 646#define MIPS_R4300 0x0b /* NEC VR4300 FPC ISA III */ 647#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 648#define MIPS_R4600 0x20 /* QED R4600 Orion FPU ISA III */ 649#define MIPS_R5010 0x23 /* MIPS R5000 FPU ISA IV */ 650#define MIPS_RC32364 0x26 /* IDT RC32364 FPU ISA II */ 651#define MIPS_RM5230 0x28 /* QED RM5230 FPU ISA IV */ 652#define MIPS_R3SONY 0x21 /* ? Sony R3000 based FPU ISA I */ 653#define MIPS_R3TOSH 0x22 /* ? Toshiba R3000 based FPU ISA I */ 654#define MIPS_R3NKK 0x23 /* ? NKK R3000 based FPU ISA I */ 655 656#ifdef ENABLE_MIPS_TX3900 657#include <mips/r3900regs.h> 658#endif 659 660#endif /* _MIPS_CPUREGS_H_ */ 661