cpuregs.h revision 1.74
1/* $NetBSD: cpuregs.h,v 1.74 2008/02/19 11:26:40 simonb Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 35 * 36 * machConst.h -- 37 * 38 * Machine dependent constants. 39 * 40 * Copyright (C) 1989 Digital Equipment Corporation. 41 * Permission to use, copy, modify, and distribute this software and 42 * its documentation for any purpose and without fee is hereby granted, 43 * provided that the above copyright notice appears in all copies. 44 * Digital Equipment Corporation makes no representations about the 45 * suitability of this software for any purpose. It is provided "as is" 46 * without express or implied warranty. 47 * 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54 */ 55 56#ifndef _MIPS_CPUREGS_H_ 57#define _MIPS_CPUREGS_H_ 58 59#include <sys/cdefs.h> /* For __CONCAT() */ 60 61#if defined(_KERNEL_OPT) 62#include "opt_cputype.h" 63#endif 64 65/* 66 * Address space. 67 * 32-bit mips CPUS partition their 32-bit address space into four segments: 68 * 69 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 70 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 71 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 72 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 73 * 74 * mips1 physical memory is limited to 512Mbytes, which is 75 * doubly mapped in kseg0 (cached) and kseg1 (uncached.) 76 * Caching of mapped addresses is controlled by bits in the TLB entry. 77 */ 78 79#define MIPS_KUSEG_START 0x0 80#define MIPS_KSEG0_START 0x80000000 81#define MIPS_KSEG1_START 0xa0000000 82#define MIPS_KSEG2_START 0xc0000000 83#define MIPS_MAX_MEM_ADDR 0xbe000000 84#define MIPS_RESERVED_ADDR 0xbfc80000 85 86#define MIPS_PHYS_MASK 0x1fffffff 87 88#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 89#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) 90#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 91#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) 92 93/* Map virtual address to index in mips3 r4k virtually-indexed cache */ 94#define MIPS3_VA_TO_CINDEX(x) \ 95 ((uintptr_t)(x) & 0xffffff | MIPS_KSEG0_START) 96 97#define MIPS_PHYS_TO_XKPHYS(cca,x) \ 98 ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) 99#define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL) 100 101/* CPU dependent mtc0 hazard hook */ 102#define COP0_SYNC /* nothing */ 103#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; 104 105/* 106 * The bits in the cause register. 107 * 108 * Bits common to r3000 and r4000: 109 * 110 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 111 * MIPS_CR_COP_ERR Coprocessor error. 112 * MIPS_CR_IP Interrupt pending bits defined below. 113 * (same meaning as in CAUSE register). 114 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 115 * 116 * Differences: 117 * r3k has 4 bits of execption type, r4k has 5 bits. 118 */ 119#define MIPS_CR_BR_DELAY 0x80000000 120#define MIPS_CR_COP_ERR 0x30000000 121#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 122#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 123#define MIPS_CR_IP 0x0000FF00 124#define MIPS_CR_EXC_CODE_SHIFT 2 125 126/* 127 * The bits in the status register. All bits are active when set to 1. 128 * 129 * R3000 status register fields: 130 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. 131 * MIPS_SR_TS TLB shutdown. 132 * 133 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 134 * 135 * Differences: 136 * r3k has cache control is via frobbing SR register bits, whereas the 137 * r4k cache control is via explicit instructions. 138 * r3k has a 3-entry stack of kernel/user bits, whereas the 139 * r4k has kernel/supervisor/user. 140 */ 141#define MIPS_SR_COP_USABILITY 0xf0000000 142#define MIPS_SR_COP_0_BIT 0x10000000 143#define MIPS_SR_COP_1_BIT 0x20000000 144 145 /* r4k and r3k differences, see below */ 146 147#define MIPS_SR_MX 0x01000000 /* MIPS64 */ 148#define MIPS_SR_PX 0x00800000 /* MIPS64 */ 149#define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ 150#define MIPS_SR_TS 0x00200000 151 152 /* r4k and r3k differences, see below */ 153 154#define MIPS_SR_INT_IE 0x00000001 155/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 156/*#define MIPS_SR_INT_MASK 0x0000ff00*/ 157 158 159/* 160 * The R2000/R3000-specific status register bit definitions. 161 * all bits are active when set to 1. 162 * 163 * MIPS_SR_PARITY_ERR Parity error. 164 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 165 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 166 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 167 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 168 * Interrupt enable bits defined below. 169 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 170 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 171 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 172 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 173 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 174 */ 175 176#define MIPS1_PARITY_ERR 0x00100000 177#define MIPS1_CACHE_MISS 0x00080000 178#define MIPS1_PARITY_ZERO 0x00040000 179#define MIPS1_SWAP_CACHES 0x00020000 180#define MIPS1_ISOL_CACHES 0x00010000 181 182#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 183#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 184#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 185#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 186#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 187 188/* backwards compatibility */ 189#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 190#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 191#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 192#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 193#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 194 195#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 196#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 197#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 198#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 199#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 200 201/* 202 * R4000 status register bit definitons, 203 * where different from r2000/r3000. 204 */ 205#define MIPS3_SR_XX 0x80000000 206#define MIPS3_SR_RP 0x08000000 207#define MIPS3_SR_FR 0x04000000 208#define MIPS3_SR_RE 0x02000000 209 210#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 211#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 212#define MIPS3_SR_SR 0x00100000 213#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */ 214#define MIPS3_SR_DIAG_CH 0x00040000 215#define MIPS3_SR_DIAG_CE 0x00020000 216#define MIPS3_SR_DIAG_PE 0x00010000 217#define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */ 218#define MIPS3_SR_KX 0x00000080 219#define MIPS3_SR_SX 0x00000040 220#define MIPS3_SR_UX 0x00000020 221#define MIPS3_SR_KSU_MASK 0x00000018 222#define MIPS3_SR_KSU_USER 0x00000010 223#define MIPS3_SR_KSU_SUPER 0x00000008 224#define MIPS3_SR_KSU_KERNEL 0x00000000 225#define MIPS3_SR_ERL 0x00000004 226#define MIPS3_SR_EXL 0x00000002 227 228#ifdef MIPS3_5900 229#undef MIPS_SR_INT_IE 230#define MIPS_SR_INT_IE 0x00010001 /* XXX */ 231#endif 232 233#define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET 234#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 235#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 236#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 237#define MIPS_SR_KX MIPS3_SR_KX 238#define MIPS_SR_SX MIPS3_SR_SX 239#define MIPS_SR_UX MIPS3_SR_UX 240 241#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 242#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 243#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 244#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 245#define MIPS_SR_ERL MIPS3_SR_ERL 246#define MIPS_SR_EXL MIPS3_SR_EXL 247 248 249/* 250 * The interrupt masks. 251 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 252 */ 253#define MIPS_INT_MASK 0xff00 254#define MIPS_INT_MASK_5 0x8000 255#define MIPS_INT_MASK_4 0x4000 256#define MIPS_INT_MASK_3 0x2000 257#define MIPS_INT_MASK_2 0x1000 258#define MIPS_INT_MASK_1 0x0800 259#define MIPS_INT_MASK_0 0x0400 260#define MIPS_HARD_INT_MASK 0xfc00 261#define MIPS_SOFT_INT_MASK_1 0x0200 262#define MIPS_SOFT_INT_MASK_0 0x0100 263 264/* 265 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can 266 * choose to enable this interrupt. 267 */ 268#if defined(MIPS3_ENABLE_CLOCK_INTR) 269#define MIPS3_INT_MASK MIPS_INT_MASK 270#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 271#else 272#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 273#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 274#endif 275 276/* 277 * The bits in the context register. 278 */ 279#define MIPS1_CNTXT_PTE_BASE 0xFFE00000 280#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 281 282#define MIPS3_CNTXT_PTE_BASE 0xFF800000 283#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 284 285/* 286 * The bits in the MIPS3 config register. 287 * 288 * bit 0..5: R/W, Bit 6..31: R/O 289 */ 290 291/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 292#define MIPS3_CONFIG_K0_MASK 0x00000007 293 294/* 295 * R/W Update on Store Conditional 296 * 0: Store Conditional uses coherency algorithm specified by TLB 297 * 1: Store Conditional uses cacheable coherent update on write 298 */ 299#define MIPS3_CONFIG_CU 0x00000008 300 301#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 302#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 303#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 304 (((config) & (bit)) ? 32 : 16) 305 306#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 307#define MIPS3_CONFIG_DC_SHIFT 6 308#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 309#define MIPS3_CONFIG_IC_SHIFT 9 310#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 311 312/* Cache size mode indication: available only on Vr41xx CPUs */ 313#define MIPS3_CONFIG_CS 0x00001000 314#define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ 315#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 316 ((base) << (((config) & (mask)) >> (shift))) 317 318/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ 319#define MIPS3_CONFIG_SE 0x00001000 320 321/* Block ordering: 0: sequential, 1: sub-block */ 322#define MIPS3_CONFIG_EB 0x00002000 323 324/* ECC mode - 0: ECC mode, 1: parity mode */ 325#define MIPS3_CONFIG_EM 0x00004000 326 327/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 328#define MIPS3_CONFIG_BE 0x00008000 329 330/* Dirty Shared coherency state - 0: enabled, 1: disabled */ 331#define MIPS3_CONFIG_SM 0x00010000 332 333/* Secondary Cache - 0: present, 1: not present */ 334#define MIPS3_CONFIG_SC 0x00020000 335 336/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 337#define MIPS3_CONFIG_EW_MASK 0x000c0000 338#define MIPS3_CONFIG_EW_SHIFT 18 339 340/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 341#define MIPS3_CONFIG_SW 0x00100000 342 343/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 344#define MIPS3_CONFIG_SS 0x00200000 345 346/* Secondary Cache line size */ 347#define MIPS3_CONFIG_SB_MASK 0x00c00000 348#define MIPS3_CONFIG_SB_SHIFT 22 349#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 350 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 351 352/* Write back data rate */ 353#define MIPS3_CONFIG_EP_MASK 0x0f000000 354#define MIPS3_CONFIG_EP_SHIFT 24 355 356/* System clock ratio - this value is CPU dependent */ 357#define MIPS3_CONFIG_EC_MASK 0x70000000 358#define MIPS3_CONFIG_EC_SHIFT 28 359 360/* Master-Checker Mode - 1: enabled */ 361#define MIPS3_CONFIG_CM 0x80000000 362 363/* 364 * The bits in the MIPS4 config register. 365 */ 366 367/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 368#define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK 369#define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */ 370#define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */ 371#define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */ 372#define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */ 373#define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */ 374#define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */ 375#define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */ 376#define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */ 377#define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */ 378#define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */ 379#define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */ 380#define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */ 381#define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */ 382 383#define MIPS4_CONFIG_DC_SHIFT 26 384#define MIPS4_CONFIG_IC_SHIFT 29 385 386#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 387 ((base) << (((config) & (mask)) >> (shift))) 388 389#define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \ 390 (((config) & MIPS4_CONFIG_SB) ? 128 : 64) 391 392/* 393 * Location of exception vectors. 394 * 395 * Common vectors: reset and UTLB miss. 396 */ 397#define MIPS_RESET_EXC_VEC 0xBFC00000 398#define MIPS_UTLB_MISS_EXC_VEC 0x80000000 399 400/* 401 * MIPS-1 general exception vector (everything else) 402 */ 403#define MIPS1_GEN_EXC_VEC 0x80000080 404 405/* 406 * MIPS-III exception vectors 407 */ 408#define MIPS3_XTLB_MISS_EXC_VEC 0x80000080 409#define MIPS3_CACHE_ERR_EXC_VEC 0x80000100 410#define MIPS3_GEN_EXC_VEC 0x80000180 411 412/* 413 * TX79 (R5900) exception vectors 414 */ 415#define MIPS_R5900_COUNTER_EXC_VEC 0x80000080 416#define MIPS_R5900_DEBUG_EXC_VEC 0x80000100 417 418/* 419 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 420 */ 421#define MIPS3_INTR_EXC_VEC 0x80000200 422 423/* 424 * Coprocessor 0 registers: 425 * 426 * v--- width for mips I,III,32,64 427 * (3=32bit, 6=64bit, i=impl dep) 428 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 429 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. 430 * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low. 431 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. 432 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. 433 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. 434 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. 435 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. 436 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. 437 * 9 MIPS_COP_0_COUNT .333 Count register. 438 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. 439 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). 440 * 12 MIPS_COP_0_STATUS 3333 Status register. 441 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. 442 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. 443 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 444 * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 445 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 446 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 447 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 448 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 449 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 450 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 451 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 452 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 453 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 454 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 455 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 456 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 457 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 458 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 459 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 460 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 461 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 462 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 463 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 464 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 465 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. 466 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. 467 */ 468#ifdef _LOCORE 469#define _(n) __CONCAT($,n) 470#else 471#define _(n) n 472#endif 473#define MIPS_COP_0_TLB_INDEX _(0) 474#define MIPS_COP_0_TLB_RANDOM _(1) 475 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 476 477#define MIPS_COP_0_TLB_CONTEXT _(4) 478 /* $5 and $6 new with MIPS-III */ 479#define MIPS_COP_0_BAD_VADDR _(8) 480#define MIPS_COP_0_TLB_HI _(10) 481#define MIPS_COP_0_STATUS _(12) 482#define MIPS_COP_0_CAUSE _(13) 483#define MIPS_COP_0_EXC_PC _(14) 484#define MIPS_COP_0_PRID _(15) 485 486 487/* MIPS-I */ 488#define MIPS_COP_0_TLB_LOW _(2) 489 490/* MIPS-III */ 491#define MIPS_COP_0_TLB_LO0 _(2) 492#define MIPS_COP_0_TLB_LO1 _(3) 493 494#define MIPS_COP_0_TLB_PG_MASK _(5) 495#define MIPS_COP_0_TLB_WIRED _(6) 496 497#define MIPS_COP_0_COUNT _(9) 498#define MIPS_COP_0_COMPARE _(11) 499 500#define MIPS_COP_0_CONFIG _(16) 501#define MIPS_COP_0_LLADDR _(17) 502#define MIPS_COP_0_WATCH_LO _(18) 503#define MIPS_COP_0_WATCH_HI _(19) 504#define MIPS_COP_0_TLB_XCONTEXT _(20) 505#define MIPS_COP_0_ECC _(26) 506#define MIPS_COP_0_CACHE_ERR _(27) 507#define MIPS_COP_0_TAG_LO _(28) 508#define MIPS_COP_0_TAG_HI _(29) 509#define MIPS_COP_0_ERROR_PC _(30) 510 511/* MIPS32/64 */ 512#define MIPS_COP_0_DEBUG _(23) 513#define MIPS_COP_0_DEPC _(24) 514#define MIPS_COP_0_PERFCNT _(25) 515#define MIPS_COP_0_DATA_LO _(28) 516#define MIPS_COP_0_DATA_HI _(29) 517#define MIPS_COP_0_DESAVE _(31) 518 519/* 520 * Values for the code field in a break instruction. 521 */ 522#define MIPS_BREAK_INSTR 0x0000000d 523#define MIPS_BREAK_VAL_MASK 0x03ff0000 524#define MIPS_BREAK_VAL_SHIFT 16 525#define MIPS_BREAK_KDB_VAL 512 526#define MIPS_BREAK_SSTEP_VAL 513 527#define MIPS_BREAK_BRKPT_VAL 514 528#define MIPS_BREAK_SOVER_VAL 515 529#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 530 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 531#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 532 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 533#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 534 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 535#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 536 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 537 538/* 539 * Mininum and maximum cache sizes. 540 */ 541#define MIPS_MIN_CACHE_SIZE (16 * 1024) 542#define MIPS_MAX_CACHE_SIZE (256 * 1024) 543#define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ 544 545/* 546 * The floating point version and status registers. 547 */ 548#define MIPS_FPU_ID $0 549#define MIPS_FPU_CSR $31 550 551/* 552 * The floating point coprocessor status register bits. 553 */ 554#define MIPS_FPU_ROUNDING_BITS 0x00000003 555#define MIPS_FPU_ROUND_RN 0x00000000 556#define MIPS_FPU_ROUND_RZ 0x00000001 557#define MIPS_FPU_ROUND_RP 0x00000002 558#define MIPS_FPU_ROUND_RM 0x00000003 559#define MIPS_FPU_STICKY_BITS 0x0000007c 560#define MIPS_FPU_STICKY_INEXACT 0x00000004 561#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 562#define MIPS_FPU_STICKY_OVERFLOW 0x00000010 563#define MIPS_FPU_STICKY_DIV0 0x00000020 564#define MIPS_FPU_STICKY_INVALID 0x00000040 565#define MIPS_FPU_ENABLE_BITS 0x00000f80 566#define MIPS_FPU_ENABLE_INEXACT 0x00000080 567#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 568#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 569#define MIPS_FPU_ENABLE_DIV0 0x00000400 570#define MIPS_FPU_ENABLE_INVALID 0x00000800 571#define MIPS_FPU_EXCEPTION_BITS 0x0003f000 572#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 573#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 574#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 575#define MIPS_FPU_EXCEPTION_DIV0 0x00008000 576#define MIPS_FPU_EXCEPTION_INVALID 0x00010000 577#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 578#define MIPS_FPU_COND_BIT 0x00800000 579#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 580#define MIPS1_FPC_MBZ_BITS 0xff7c0000 581#define MIPS3_FPC_MBZ_BITS 0xfe7c0000 582 583 584/* 585 * Constants to determine if have a floating point instruction. 586 */ 587#define MIPS_OPCODE_SHIFT 26 588#define MIPS_OPCODE_C1 0x11 589 590 591/* 592 * The low part of the TLB entry. 593 */ 594#define MIPS1_TLB_PFN 0xfffff000 595#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 596#define MIPS1_TLB_DIRTY_BIT 0x00000400 597#define MIPS1_TLB_VALID_BIT 0x00000200 598#define MIPS1_TLB_GLOBAL_BIT 0x00000100 599 600#define MIPS3_TLB_PFN 0x3fffffc0 601#define MIPS3_TLB_ATTR_MASK 0x00000038 602#define MIPS3_TLB_ATTR_SHIFT 3 603#define MIPS3_TLB_DIRTY_BIT 0x00000004 604#define MIPS3_TLB_VALID_BIT 0x00000002 605#define MIPS3_TLB_GLOBAL_BIT 0x00000001 606 607#define MIPS1_TLB_PHYS_PAGE_SHIFT 12 608#define MIPS3_TLB_PHYS_PAGE_SHIFT 6 609#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 610#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 611#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 612#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 613 614/* 615 * MIPS3_TLB_ATTR values - coherency algorithm: 616 * 0: cacheable, noncoherent, write-through, no write allocate 617 * 1: cacheable, noncoherent, write-through, write allocate 618 * 2: uncached 619 * 3: cacheable, noncoherent, write-back (noncoherent) 620 * 4: cacheable, coherent, write-back, exclusive (exclusive) 621 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 622 * 6: cacheable, coherent, write-back, update on write (update) 623 * 7: uncached, accelerated (gather STORE operations) 624 */ 625#define MIPS3_TLB_ATTR_WT 0 /* IDT */ 626#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 627#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 628#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 629#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 630#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 631#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 632#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 633 634 635/* 636 * The high part of the TLB entry. 637 */ 638#define MIPS1_TLB_VPN 0xfffff000 639#define MIPS1_TLB_PID 0x00000fc0 640#define MIPS1_TLB_PID_SHIFT 6 641 642#define MIPS3_TLB_VPN2 0xffffe000 643#define MIPS3_TLB_ASID 0x000000ff 644 645#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 646#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 647#define MIPS3_TLB_PID MIPS3_TLB_ASID 648#define MIPS_TLB_VIRT_PAGE_SHIFT 12 649 650/* 651 * r3000: shift count to put the index in the right spot. 652 */ 653#define MIPS1_TLB_INDEX_SHIFT 8 654 655/* 656 * The first TLB that write random hits. 657 */ 658#define MIPS1_TLB_FIRST_RAND_ENTRY 8 659#define MIPS3_TLB_WIRED_UPAGES 1 660 661/* 662 * The number of process id entries. 663 */ 664#define MIPS1_TLB_NUM_PIDS 64 665#define MIPS3_TLB_NUM_ASIDS 256 666 667/* 668 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 669 */ 670 671/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */ 672 673#if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 674 && defined(MIPS1) /* XXX simonb must be neater! */ 675#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 676#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 677#endif 678 679#if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 680 && !defined(MIPS1) /* XXX simonb must be neater! */ 681#define MIPS_TLB_PID_SHIFT 0 682#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 683#endif 684 685 686#if !defined(MIPS_TLB_PID_SHIFT) 687#define MIPS_TLB_PID_SHIFT \ 688 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) 689 690#define MIPS_TLB_NUM_PIDS \ 691 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 692#endif 693 694/* 695 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) 696 */ 697#define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ 698#define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ 699#define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ 700#define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ 701#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ 702#define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ 703#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ 704#define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ 705#define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ 706#define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ 707#define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ 708#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 709#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 710#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 711#define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ 712#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 713#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 714#define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ 715#define MIPS_R4650 0x22 /* QED R4650 ISA III */ 716#define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ 717#define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ 718#define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ 719#define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ 720#define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ 721#define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ 722#define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ 723#define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ 724#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ 725#define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/ 726#define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ 727#define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */ 728 729/* 730 * CPU revision IDs for some prehistoric processors. 731 */ 732 733/* For MIPS_R3000 */ 734#define MIPS_REV_R2000A 0x16 /* R2000A uses R3000 proc revision */ 735#define MIPS_REV_R3000 0x20 736#define MIPS_REV_R3000A 0x30 737 738/* For MIPS_TX3900 */ 739#define MIPS_REV_TX3912 0x10 740#define MIPS_REV_TX3922 0x30 741#define MIPS_REV_TX3927 0x40 742 743/* For MIPS_R4000 */ 744#define MIPS_REV_R4000_A 0x00 745#define MIPS_REV_R4000_B 0x22 746#define MIPS_REV_R4000_C 0x30 747#define MIPS_REV_R4400_A 0x40 748#define MIPS_REV_R4400_B 0x50 749#define MIPS_REV_R4400_C 0x60 750 751/* For MIPS_TX4900 */ 752#define MIPS_REV_TX4927 0x22 753 754/* 755 * CPU processor revision IDs for company ID == 1 (MIPS) 756 */ 757#define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ 758#define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ 759#define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */ 760#define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */ 761#define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ 762#define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */ 763#define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ 764#define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */ 765#define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */ 766#define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */ 767#define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */ 768#define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */ 769#define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */ 770#define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */ 771#define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */ 772#define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */ 773#define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */ 774 775/* 776 * Alchemy (company ID 3) use the processor ID field to donote the CPU core 777 * revision and the company options field do donate the SOC chip type. 778 */ 779/* CPU processor revision IDs */ 780#define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */ 781#define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */ 782/* CPU company options IDs */ 783#define MIPS_AU1000 0x00 784#define MIPS_AU1500 0x01 785#define MIPS_AU1100 0x02 786#define MIPS_AU1550 0x03 787 788/* 789 * CPU processor revision IDs for company ID == 4 (SiByte) 790 */ 791#define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 792 793/* 794 * CPU processor revision IDs for company ID == 5 (SandCraft) 795 */ 796#define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */ 797 798/* 799 * FPU processor revision ID 800 */ 801#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 802#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 803#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 804#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 805#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 806#define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 807#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 808#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 809 810#ifdef ENABLE_MIPS_TX3900 811#include <mips/r3900regs.h> 812#endif 813#ifdef MIPS3_5900 814#include <mips/r5900regs.h> 815#endif 816#ifdef MIPS64_SB1 817#include <mips/sb1regs.h> 818#endif 819 820#endif /* _MIPS_CPUREGS_H_ */ 821