Remove unnecessary <sys/malloc.h>.

Merge thorpej-cfargs2.

branches: 1.33.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.32.4;
Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

The PCI I/O space extent map needs to reflect the BUS_{START,END}
not the SYS_{START,END}.

This fixes mapping of the viaide DMA registers on my Qube2.

branches: 1.29.4; 1.29.8;
Switch cobalt to common bus_space.

Tested on raq 2

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.27.2; 1.27.6;
Cleanup kernel files to use sys variants for bus.h, cpu.h, and intr.h
Use <mips/..> for db_machdep.h and psl.h

#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Don't set pba.pba_flags twice. No functional change intended.

Merge forward from matt-nb5-mips64.
(XXX generic kernels on raq2 die after interrupts are enabled but gxemul
works fine).

branches: 1.22.4; 1.22.6; 1.22.8;
- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

branches: 1.21.16;
Split softc/device_t, with misc related changes.

branches: 1.20.54; 1.20.56; 1.20.58; 1.20.60;
Remove or comment out now unused code after MI mips3_clockintr migration.

branches: 1.19.6;
Initialize the GT64x11 PCI timeout and retry register with a value taken
from Linux/MIPS, which improves viaide xfer performance significantly.

Change range of PCI I/O space for pci_configure_bus(9)
so that viaide(4) works with PCI fixup (not enabled yet).

branches: 1.17.2;
Explicitly mask timer0 interrupt until cpu_initclocks(9).

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

ANSIfy, KNF

branches: 1.14.4; 1.14.6; 1.14.8; 1.14.10; 1.14.12;
merge ktrace-lwp.

branches: 1.13.2;
Switch cobalt port to use MI pci_configure_bus(9)
with options PCI_NETBSD_CONFIGURE.
Patch from KIYOHARA Takashi on port-cobalt.

This change makes siop(4) (and maybe all other PCI devices
using pci mem space) work on cobalt.

branches: 1.12.4; 1.12.6; 1.12.10;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

- Use bus_space(9) to access PCI configuration registers on GT64111.
- Remove unused pci stuff from mainbus.c.

- Reset timer0 of GT64111 in gt_attach() and start it
in cpu_initclocks(9) via a callback function.
Fixes the "hardclock(9) is called before cpu_initclocks(9)" problem
reported by KIYOHARA Takashi on port-cobalt.
- Use bus_space(9) functions to access GT64111 registers and
add register definitions for GT64111 in gtreg.h.
(XXX this could be in sys/dev/marvell?)
- Move microtime(9) from machdep.c to clock.c, and read timer0 register
via a callback function. Also change microtime(9) like other ports
to guarantee that the time will be greater than the value obtained
by a previous call.

__KERNEL_RCSID()

branches: 1.8.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use CFATTACH_DECL().

Declare all cfattach structures const.

branches: 1.5.2;
* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.4.4; 1.4.8; 1.4.12;
Static poisoning.

branches: 1.3.2;
Disabling PCI Memory Read Multiple improves Tulip transmit performance 30%.

Some cleanups.

NetBSD/cobalt. Work-in-progress.

Merge thorpej-cfargs2.

branches: 1.33.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.32.4;
Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

The PCI I/O space extent map needs to reflect the BUS_{START,END}
not the SYS_{START,END}.

This fixes mapping of the viaide DMA registers on my Qube2.

branches: 1.29.4; 1.29.8;
Switch cobalt to common bus_space.

Tested on raq 2

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.27.2; 1.27.6;
Cleanup kernel files to use sys variants for bus.h, cpu.h, and intr.h
Use <mips/..> for db_machdep.h and psl.h

#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Don't set pba.pba_flags twice. No functional change intended.

Merge forward from matt-nb5-mips64.
(XXX generic kernels on raq2 die after interrupts are enabled but gxemul
works fine).

branches: 1.22.4; 1.22.6; 1.22.8;
- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

branches: 1.21.16;
Split softc/device_t, with misc related changes.

branches: 1.20.54; 1.20.56; 1.20.58; 1.20.60;
Remove or comment out now unused code after MI mips3_clockintr migration.

branches: 1.19.6;
Initialize the GT64x11 PCI timeout and retry register with a value taken
from Linux/MIPS, which improves viaide xfer performance significantly.

Change range of PCI I/O space for pci_configure_bus(9)
so that viaide(4) works with PCI fixup (not enabled yet).

branches: 1.17.2;
Explicitly mask timer0 interrupt until cpu_initclocks(9).

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

ANSIfy, KNF

branches: 1.14.4; 1.14.6; 1.14.8; 1.14.10; 1.14.12;
merge ktrace-lwp.

branches: 1.13.2;
Switch cobalt port to use MI pci_configure_bus(9)
with options PCI_NETBSD_CONFIGURE.
Patch from KIYOHARA Takashi on port-cobalt.

This change makes siop(4) (and maybe all other PCI devices
using pci mem space) work on cobalt.

branches: 1.12.4; 1.12.6; 1.12.10;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

- Use bus_space(9) to access PCI configuration registers on GT64111.
- Remove unused pci stuff from mainbus.c.

- Reset timer0 of GT64111 in gt_attach() and start it
in cpu_initclocks(9) via a callback function.
Fixes the "hardclock(9) is called before cpu_initclocks(9)" problem
reported by KIYOHARA Takashi on port-cobalt.
- Use bus_space(9) functions to access GT64111 registers and
add register definitions for GT64111 in gtreg.h.
(XXX this could be in sys/dev/marvell?)
- Move microtime(9) from machdep.c to clock.c, and read timer0 register
via a callback function. Also change microtime(9) like other ports
to guarantee that the time will be greater than the value obtained
by a previous call.

__KERNEL_RCSID()

branches: 1.8.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use CFATTACH_DECL().

Declare all cfattach structures const.

branches: 1.5.2;
* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.4.4; 1.4.8; 1.4.12;
Static poisoning.

branches: 1.3.2;
Disabling PCI Memory Read Multiple improves Tulip transmit performance 30%.

Some cleanups.

NetBSD/cobalt. Work-in-progress.

Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.32.4;
Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

The PCI I/O space extent map needs to reflect the BUS_{START,END}
not the SYS_{START,END}.

This fixes mapping of the viaide DMA registers on my Qube2.

branches: 1.29.4; 1.29.8;
Switch cobalt to common bus_space.

Tested on raq 2

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.27.2; 1.27.6;
Cleanup kernel files to use sys variants for bus.h, cpu.h, and intr.h
Use <mips/..> for db_machdep.h and psl.h

#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Don't set pba.pba_flags twice. No functional change intended.

Merge forward from matt-nb5-mips64.
(XXX generic kernels on raq2 die after interrupts are enabled but gxemul
works fine).

branches: 1.22.4; 1.22.6; 1.22.8;
- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

branches: 1.21.16;
Split softc/device_t, with misc related changes.

branches: 1.20.54; 1.20.56; 1.20.58; 1.20.60;
Remove or comment out now unused code after MI mips3_clockintr migration.

branches: 1.19.6;
Initialize the GT64x11 PCI timeout and retry register with a value taken
from Linux/MIPS, which improves viaide xfer performance significantly.

Change range of PCI I/O space for pci_configure_bus(9)
so that viaide(4) works with PCI fixup (not enabled yet).

branches: 1.17.2;
Explicitly mask timer0 interrupt until cpu_initclocks(9).

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

ANSIfy, KNF

branches: 1.14.4; 1.14.6; 1.14.8; 1.14.10; 1.14.12;
merge ktrace-lwp.

branches: 1.13.2;
Switch cobalt port to use MI pci_configure_bus(9)
with options PCI_NETBSD_CONFIGURE.
Patch from KIYOHARA Takashi on port-cobalt.

This change makes siop(4) (and maybe all other PCI devices
using pci mem space) work on cobalt.

branches: 1.12.4; 1.12.6; 1.12.10;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

- Use bus_space(9) to access PCI configuration registers on GT64111.
- Remove unused pci stuff from mainbus.c.

- Reset timer0 of GT64111 in gt_attach() and start it
in cpu_initclocks(9) via a callback function.
Fixes the "hardclock(9) is called before cpu_initclocks(9)" problem
reported by KIYOHARA Takashi on port-cobalt.
- Use bus_space(9) functions to access GT64111 registers and
add register definitions for GT64111 in gtreg.h.
(XXX this could be in sys/dev/marvell?)
- Move microtime(9) from machdep.c to clock.c, and read timer0 register
via a callback function. Also change microtime(9) like other ports
to guarantee that the time will be greater than the value obtained
by a previous call.

__KERNEL_RCSID()

branches: 1.8.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use CFATTACH_DECL().

Declare all cfattach structures const.

branches: 1.5.2;
* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.4.4; 1.4.8; 1.4.12;
Static poisoning.

branches: 1.3.2;
Disabling PCI Memory Read Multiple improves Tulip transmit performance 30%.

Some cleanups.

NetBSD/cobalt. Work-in-progress.

Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

The PCI I/O space extent map needs to reflect the BUS_{START,END}
not the SYS_{START,END}.

This fixes mapping of the viaide DMA registers on my Qube2.

branches: 1.29.4; 1.29.8;
Switch cobalt to common bus_space.

Tested on raq 2

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.27.2; 1.27.6;
Cleanup kernel files to use sys variants for bus.h, cpu.h, and intr.h
Use <mips/..> for db_machdep.h and psl.h

#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Don't set pba.pba_flags twice. No functional change intended.

Merge forward from matt-nb5-mips64.
(XXX generic kernels on raq2 die after interrupts are enabled but gxemul
works fine).

branches: 1.22.4; 1.22.6; 1.22.8;
- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

branches: 1.21.16;
Split softc/device_t, with misc related changes.

branches: 1.20.54; 1.20.56; 1.20.58; 1.20.60;
Remove or comment out now unused code after MI mips3_clockintr migration.

branches: 1.19.6;
Initialize the GT64x11 PCI timeout and retry register with a value taken
from Linux/MIPS, which improves viaide xfer performance significantly.

Change range of PCI I/O space for pci_configure_bus(9)
so that viaide(4) works with PCI fixup (not enabled yet).

branches: 1.17.2;
Explicitly mask timer0 interrupt until cpu_initclocks(9).

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

ANSIfy, KNF

branches: 1.14.4; 1.14.6; 1.14.8; 1.14.10; 1.14.12;
merge ktrace-lwp.

branches: 1.13.2;
Switch cobalt port to use MI pci_configure_bus(9)
with options PCI_NETBSD_CONFIGURE.
Patch from KIYOHARA Takashi on port-cobalt.

This change makes siop(4) (and maybe all other PCI devices
using pci mem space) work on cobalt.

branches: 1.12.4; 1.12.6; 1.12.10;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

- Use bus_space(9) to access PCI configuration registers on GT64111.
- Remove unused pci stuff from mainbus.c.

- Reset timer0 of GT64111 in gt_attach() and start it
in cpu_initclocks(9) via a callback function.
Fixes the "hardclock(9) is called before cpu_initclocks(9)" problem
reported by KIYOHARA Takashi on port-cobalt.
- Use bus_space(9) functions to access GT64111 registers and
add register definitions for GT64111 in gtreg.h.
(XXX this could be in sys/dev/marvell?)
- Move microtime(9) from machdep.c to clock.c, and read timer0 register
via a callback function. Also change microtime(9) like other ports
to guarantee that the time will be greater than the value obtained
by a previous call.

__KERNEL_RCSID()

branches: 1.8.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use CFATTACH_DECL().

Declare all cfattach structures const.

branches: 1.5.2;
* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.4.4; 1.4.8; 1.4.12;
Static poisoning.

branches: 1.3.2;
Disabling PCI Memory Read Multiple improves Tulip transmit performance 30%.

Some cleanups.

NetBSD/cobalt. Work-in-progress.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

The PCI I/O space extent map needs to reflect the BUS_{START,END}
not the SYS_{START,END}.

This fixes mapping of the viaide DMA registers on my Qube2.

branches: 1.29.4; 1.29.8;
Switch cobalt to common bus_space.

Tested on raq 2

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.27.2; 1.27.6;
Cleanup kernel files to use sys variants for bus.h, cpu.h, and intr.h
Use <mips/..> for db_machdep.h and psl.h

#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Don't set pba.pba_flags twice. No functional change intended.

Merge forward from matt-nb5-mips64.
(XXX generic kernels on raq2 die after interrupts are enabled but gxemul
works fine).

branches: 1.22.4; 1.22.6; 1.22.8;
- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

branches: 1.21.16;
Split softc/device_t, with misc related changes.

branches: 1.20.54; 1.20.56; 1.20.58; 1.20.60;
Remove or comment out now unused code after MI mips3_clockintr migration.

branches: 1.19.6;
Initialize the GT64x11 PCI timeout and retry register with a value taken
from Linux/MIPS, which improves viaide xfer performance significantly.

Change range of PCI I/O space for pci_configure_bus(9)
so that viaide(4) works with PCI fixup (not enabled yet).

branches: 1.17.2;
Explicitly mask timer0 interrupt until cpu_initclocks(9).

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

ANSIfy, KNF

branches: 1.14.4; 1.14.6; 1.14.8; 1.14.10; 1.14.12;
merge ktrace-lwp.

branches: 1.13.2;
Switch cobalt port to use MI pci_configure_bus(9)
with options PCI_NETBSD_CONFIGURE.
Patch from KIYOHARA Takashi on port-cobalt.

This change makes siop(4) (and maybe all other PCI devices
using pci mem space) work on cobalt.

branches: 1.12.4; 1.12.6; 1.12.10;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

- Use bus_space(9) to access PCI configuration registers on GT64111.
- Remove unused pci stuff from mainbus.c.

- Reset timer0 of GT64111 in gt_attach() and start it
in cpu_initclocks(9) via a callback function.
Fixes the "hardclock(9) is called before cpu_initclocks(9)" problem
reported by KIYOHARA Takashi on port-cobalt.
- Use bus_space(9) functions to access GT64111 registers and
add register definitions for GT64111 in gtreg.h.
(XXX this could be in sys/dev/marvell?)
- Move microtime(9) from machdep.c to clock.c, and read timer0 register
via a callback function. Also change microtime(9) like other ports
to guarantee that the time will be greater than the value obtained
by a previous call.

__KERNEL_RCSID()

branches: 1.8.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use CFATTACH_DECL().

Declare all cfattach structures const.

branches: 1.5.2;
* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.4.4; 1.4.8; 1.4.12;
Static poisoning.

branches: 1.3.2;
Disabling PCI Memory Read Multiple improves Tulip transmit performance 30%.

Some cleanups.

NetBSD/cobalt. Work-in-progress.

The PCI I/O space extent map needs to reflect the BUS_{START,END}
not the SYS_{START,END}.

This fixes mapping of the viaide DMA registers on my Qube2.

branches: 1.29.8;
Switch cobalt to common bus_space.

Tested on raq 2

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.27.2; 1.27.6;
Cleanup kernel files to use sys variants for bus.h, cpu.h, and intr.h
Use <mips/..> for db_machdep.h and psl.h

#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Don't set pba.pba_flags twice. No functional change intended.

Merge forward from matt-nb5-mips64.
(XXX generic kernels on raq2 die after interrupts are enabled but gxemul
works fine).

branches: 1.22.4; 1.22.6; 1.22.8;
- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

branches: 1.21.16;
Split softc/device_t, with misc related changes.

branches: 1.20.54; 1.20.56; 1.20.58; 1.20.60;
Remove or comment out now unused code after MI mips3_clockintr migration.

branches: 1.19.6;
Initialize the GT64x11 PCI timeout and retry register with a value taken
from Linux/MIPS, which improves viaide xfer performance significantly.

Change range of PCI I/O space for pci_configure_bus(9)
so that viaide(4) works with PCI fixup (not enabled yet).

branches: 1.17.2;
Explicitly mask timer0 interrupt until cpu_initclocks(9).

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

ANSIfy, KNF

branches: 1.14.4; 1.14.6; 1.14.8; 1.14.10; 1.14.12;
merge ktrace-lwp.

branches: 1.13.2;
Switch cobalt port to use MI pci_configure_bus(9)
with options PCI_NETBSD_CONFIGURE.
Patch from KIYOHARA Takashi on port-cobalt.

This change makes siop(4) (and maybe all other PCI devices
using pci mem space) work on cobalt.

branches: 1.12.4; 1.12.6; 1.12.10;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

- Use bus_space(9) to access PCI configuration registers on GT64111.
- Remove unused pci stuff from mainbus.c.

- Reset timer0 of GT64111 in gt_attach() and start it
in cpu_initclocks(9) via a callback function.
Fixes the "hardclock(9) is called before cpu_initclocks(9)" problem
reported by KIYOHARA Takashi on port-cobalt.
- Use bus_space(9) functions to access GT64111 registers and
add register definitions for GT64111 in gtreg.h.
(XXX this could be in sys/dev/marvell?)
- Move microtime(9) from machdep.c to clock.c, and read timer0 register
via a callback function. Also change microtime(9) like other ports
to guarantee that the time will be greater than the value obtained
by a previous call.

__KERNEL_RCSID()

branches: 1.8.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use CFATTACH_DECL().

Declare all cfattach structures const.

branches: 1.5.2;
* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.4.4; 1.4.8; 1.4.12;
Static poisoning.

branches: 1.3.2;
Disabling PCI Memory Read Multiple improves Tulip transmit performance 30%.

Some cleanups.

NetBSD/cobalt. Work-in-progress.

Switch cobalt to common bus_space.

Tested on raq 2

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.27.2; 1.27.6;
Cleanup kernel files to use sys variants for bus.h, cpu.h, and intr.h
Use <mips/..> for db_machdep.h and psl.h

#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Don't set pba.pba_flags twice. No functional change intended.

Merge forward from matt-nb5-mips64.
(XXX generic kernels on raq2 die after interrupts are enabled but gxemul
works fine).

branches: 1.22.4; 1.22.6; 1.22.8;
- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

branches: 1.21.16;
Split softc/device_t, with misc related changes.

branches: 1.20.54; 1.20.56; 1.20.58; 1.20.60;
Remove or comment out now unused code after MI mips3_clockintr migration.

branches: 1.19.6;
Initialize the GT64x11 PCI timeout and retry register with a value taken
from Linux/MIPS, which improves viaide xfer performance significantly.

Change range of PCI I/O space for pci_configure_bus(9)
so that viaide(4) works with PCI fixup (not enabled yet).

branches: 1.17.2;
Explicitly mask timer0 interrupt until cpu_initclocks(9).

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

ANSIfy, KNF

branches: 1.14.4; 1.14.6; 1.14.8; 1.14.10; 1.14.12;
merge ktrace-lwp.

branches: 1.13.2;
Switch cobalt port to use MI pci_configure_bus(9)
with options PCI_NETBSD_CONFIGURE.
Patch from KIYOHARA Takashi on port-cobalt.

This change makes siop(4) (and maybe all other PCI devices
using pci mem space) work on cobalt.

branches: 1.12.4; 1.12.6; 1.12.10;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

- Use bus_space(9) to access PCI configuration registers on GT64111.
- Remove unused pci stuff from mainbus.c.

- Reset timer0 of GT64111 in gt_attach() and start it
in cpu_initclocks(9) via a callback function.
Fixes the "hardclock(9) is called before cpu_initclocks(9)" problem
reported by KIYOHARA Takashi on port-cobalt.
- Use bus_space(9) functions to access GT64111 registers and
add register definitions for GT64111 in gtreg.h.
(XXX this could be in sys/dev/marvell?)
- Move microtime(9) from machdep.c to clock.c, and read timer0 register
via a callback function. Also change microtime(9) like other ports
to guarantee that the time will be greater than the value obtained
by a previous call.

__KERNEL_RCSID()

branches: 1.8.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use CFATTACH_DECL().

Declare all cfattach structures const.

branches: 1.5.2;
* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.4.4; 1.4.8; 1.4.12;
Static poisoning.

branches: 1.3.2;
Disabling PCI Memory Read Multiple improves Tulip transmit performance 30%.

Some cleanups.

NetBSD/cobalt. Work-in-progress.