gt.c revision 1.33
1/* $NetBSD: gt.c,v 1.33 2021/04/24 23:36:31 thorpej Exp $ */ 2 3/* 4 * Copyright (c) 2000 Soren S. Jorvang. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.33 2021/04/24 23:36:31 thorpej Exp $"); 30 31#include "opt_pci.h" 32#include "pci.h" 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/device.h> 38#include <sys/file.h> 39#include <sys/intr.h> 40#include <sys/ioctl.h> 41#include <sys/kernel.h> 42#include <sys/malloc.h> 43#include <sys/proc.h> 44#include <sys/select.h> 45#include <sys/syslog.h> 46#include <sys/systm.h> 47#include <sys/tty.h> 48#include <sys/uio.h> 49 50#include <machine/autoconf.h> 51 52#include <mips/cache.h> 53 54#include <dev/pci/pcivar.h> 55#ifdef PCI_NETBSD_CONFIGURE 56#include <dev/pci/pciconf.h> 57#endif 58 59#include <cobalt/dev/gtvar.h> 60#include <cobalt/dev/gtreg.h> 61 62struct gt_softc { 63 device_t sc_dev; 64 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; 67 struct cobalt_pci_chipset sc_pc; 68}; 69 70static int gt_match(device_t, cfdata_t, void *); 71static void gt_attach(device_t, device_t, void *); 72static int gt_print(void *aux, const char *pnp); 73 74static void gt_timer_init(struct gt_softc *sc); 75#if 0 /* unused */ 76static void gt_timer0_init(void *); 77static long gt_timer0_read(void *); 78#endif 79 80struct mips_bus_space gt_iot; 81struct mips_bus_space gt_memt; 82 83CFATTACH_DECL_NEW(gt, sizeof(struct gt_softc), 84 gt_match, gt_attach, NULL, NULL); 85 86#define PCI_IO_START 0x00001000 87#define PCI_IO_END 0x01ffffff 88#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1) 89 90#define PCI_MEM_START 0x12000000 91#define PCI_MEM_END 0x13ffffff 92#define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1) 93 94static int 95gt_match(device_t parent, cfdata_t cf, void *aux) 96{ 97 98 return 1; 99} 100 101#define GT_REG_REGION 0x1000 102 103static void 104gt_attach(device_t parent, device_t self, void *aux) 105{ 106 struct gt_softc *sc = device_private(self); 107 struct mainbus_attach_args *ma = aux; 108#if NPCI > 0 109 pci_chipset_tag_t pc; 110 struct pcibus_attach_args pba; 111#endif 112 113 sc->sc_dev = self; 114 sc->sc_bst = ma->ma_iot; 115 if (bus_space_map(sc->sc_bst, ma->ma_addr, GT_REG_REGION, 116 0, &sc->sc_bsh)) { 117 aprint_error(": unable to map GT64111 registers\n"); 118 return; 119 } 120 121 aprint_normal("\n"); 122 123 gt_timer_init(sc); 124 125 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND, 126 (bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND) & 127 ~PCI_SYNCMODE) | PCI_PCLK_HIGH); 128 129 (void)bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_TIMEOUT_RETRY); 130 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_TIMEOUT_RETRY, 131 0x00 << PCI_RETRYCTR_SHIFT | 0xff << PCI_TIMEOUT1_SHIFT | 0xff); 132 133 gt_bus_mem_init(>_memt, NULL); 134 gt_bus_io_init(>_iot, NULL); 135 136#if NPCI > 0 137 pc = &sc->sc_pc; 138 pc->pc_bst = sc->sc_bst; 139 pc->pc_bsh = sc->sc_bsh; 140 141#ifdef PCI_NETBSD_CONFIGURE 142 struct pciconf_resources *pcires = pciconf_resource_init(); 143 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 144 PCI_IO_START, PCI_IO_SIZE); 145 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 146 PCI_MEM_START, PCI_MEM_SIZE); 147 pci_configure_bus(pc, pcires, 0, mips_cache_info.mci_dcache_align); 148 pciconf_resource_fini(pcires); 149#endif 150 memset(&pba, 0, sizeof(pba)); 151 pba.pba_memt = >_memt; 152 pba.pba_iot = >_iot; 153 pba.pba_dmat = &pci_bus_dma_tag; 154 pba.pba_dmat64 = NULL; 155 pba.pba_bus = 0; 156 pba.pba_bridgetag = NULL; 157 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 158 PCI_FLAGS_MRL_OKAY | /*PCI_FLAGS_MRM_OKAY|*/ PCI_FLAGS_MWI_OKAY; 159 pba.pba_pc = pc; 160 config_found(self, &pba, gt_print, CFARG_EOL); 161#endif 162} 163 164static int 165gt_print(void *aux, const char *pnp) 166{ 167 168 /* XXX */ 169 return 0; 170} 171 172static void 173gt_timer_init(struct gt_softc *sc) 174{ 175 176 /* stop timer0 */ 177 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL, 178 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) & ~ENTC0); 179 /* mask timer0 interrupt */ 180 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK, 181 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK) & ~T0EXP); 182} 183 184#if 0 /* unused; now NetBSD/cobalt uses CPU INT5 for hardclock(9) */ 185#define TIMER0_INIT_VALUE 500000 186 187static void 188gt_timer0_init(void *cookie) 189{ 190 struct gt_softc *sc = cookie; 191 192 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 193 GT_TIMER_COUNTER0, TIMER0_INIT_VALUE); 194 /* start timer0 */ 195 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL, 196 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) | ENTC0); 197 /* unmask timer0 interrupt */ 198 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK, 199 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK) | T0EXP); 200} 201 202static long 203gt_timer0_read(void *cookie) 204{ 205 struct gt_softc *sc = cookie; 206 uint32_t counter0; 207 208 counter0 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_COUNTER0); 209 counter0 = TIMER0_INIT_VALUE - counter0; 210#if 0 211 counter /= 50; 212#else 213 /* 214 * From pmax/pmax/dec_3min.c: 215 * 1/64 + 1/256 + 1/2048 = 41/2048 = 1/49.9512... 216 */ 217 counter0 = (counter0 >> 6) + (counter0 >> 8) + (counter0 >> 11); 218#endif 219 return counter0; 220} 221#endif 222