arm/gic: Check l_blcnt, not l_biglocks.

l_biglocks is a now-defunct temporary storage used only when
sleeping; l_blcnt is the number of kernel locks held by the lwp when
not sleeping.

Should fix arm builds.

build fix: remove includes of opt_gic.h

Remove GIC_SPLFUNCS.

pic: Update ci_cpl in pic_set_priority callback.

Not all ICs need interrupts disabled to update the priority. DAIF accesses
are not cheap, so push the update of ci_cpl from pic_set_priority to the
IC's pic_set_priority callback, and let the IC driver determine whether
or not it needs interrupts disabled.

arm: Use device_set_private for various drivers.

arm: Remove #ifdef DIAGNOSTIC now wrong after KASSERT change.

Objects in question aren't volatile here so access is flushable.

Fix some conditionals to match gicv3 and add some comments to describe
what's going on.

Fixes PR port-evbarm/56420

If an SGI or PPI is established after interrupts are enabled, make sure
we unblock the source on _all_ CPUs and not just the CPU that is
establishing the interrupt.

Make gic_splfuncs optional and disable it by default until it has had
more testing.

Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.

Only target the boot cpu for real with SPI interrupts. I tried to do
this back in 2014, but somehow I missed a spot.

This is a quick-and-dirty fix for the USB stack which expects transfer
completions to be in-order. If interrupts happen across the CPUs then
this isn't guaranteed (yet).

kern/55243 panic at usb_transfer_complete() on raspberry pi 4

branches: 1.46.2;
If we are committing a deferred splhigh() to hardware, no need to continue.

Apply PMR optimizations from gicv3

Avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.

Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.

branches: 1.42.2;
G/C arm/atomic.h

Remove CPU ID test in armgic_match. Perfectly normal to have GIC in
non-Cortex cores.

Avoid undefined behaviour. Detected by KUBSAN.

Fix "left shift of 255 by 24 places cannot be represented in type 'int'"
warning from UBSan.

branches: 1.38.4; 1.38.10;
Use intr_establish_xname

armgic_ipi_send: use GIC interface number, not CPU index, when setting
the target(s) for an IPI.

Update sc_mptargets atomically, as PEs will be started up in parallel w/o locking here

Support pic_set_affinity and pic_get_affinity

branches: 1.34.2;
Cover all pic_maxsources lines for armgic_cpu_init_priorities() and
armgic_cpu_update_priorities().

Previously only the first 32 lines were covered, which is significantly
less than the 1000-some interrupt lines possible.

Only relevant to MULTIPROCESSOR configurations.

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.32.2;
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC

The priority level is changed by writing to GICC_PMR with interrupts
disabled. However, interrupts are enabled/disabled downstream of the GICC
at the CPU. When raising priority level, there is a window between the time
that interrupts are disabled and the GICC_PMR register is written. If an
interrupt occurs at a previously allowed priority before GICC_PMR is
changed, the CPU will receive the signal when interrupts are re-enabled.
At this time, GICC_PMR is now the new priority level, so reads of
GICC_IAR will report a spurious IRQ.

Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
there is at least one pending IRQ.

KNF

ARM Trusted Firmware reserves SGIs 8-15 for secure use. Even without ATF,
U-Boot on some platforms may use SGIs in this range for the PSCI
implementation.

Change ARMGIC_IPI_BASE to 0 from (16 - NIPI) and add a compile-time assert
to ensure that we don't end up with a conflict.

Revert the KERNHIST for now it causes problems

If we see GICC_IAR_IRQ_SSPURIOUS we should also stop looking for irqs

Wrap long line

Print the GICC_IIDR when AB_DEBUG

Add 'armgichist' KERNHIST for (future) debugging.

Don't assume that CPU index = GIC CPU interface number. We can determine
the current CPU interface number by reading from the read-only
GICD_ITARGETSR0 through GICD_ITARGETSR7 registers.

This gets interrupts working on Exynos 5422, where the boot processor has
GIC CPU interface #4.

Clean out some #if 0'ed or //'ed code

Initialise all the SGI/PPI priorities for all CPUs to mask the interrupts

branches: 1.21.2;
Use an FDT-based ARM_INTR_IMPL for Tegra.

Adjust some of IPLs of various IPIs.

Add separate IPI routines for IPI_AST and IPI_KPREEMPT.

Add a pic_cpus to the softc which specifies which cpus the pic can send
IPIs to. For GIC, initialize pic_cpus to kcpuset_running since it can handle
all the cpus.

All SGIs are MPSAFE so establish them as such.

Trailing whitespace

G/C armgic_last_priority

in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn when setting irq type (IST_LEVEL/IST_EDGE)

sc_gic_lines is the total number of valid lines but pic_sources[] is sparse; when initializing mpsafe targets make sure to go all the way to the end (sc_pic.pic_maxsources) instead

branches: 1.12.2;
Only target boot cpu for SPIs atm. Fix a couple of bugs in the now
disabled code.

Sprinkle #include "opt_multiprocessor.h"

branches: 1.10.2;
Implement MI IPI interface with cross-call support.

When dealing with the PMR register, only use non-secure priority values.

Move aprint to print sooner.

branches: 1.7.2;
Various MP changes.

Don't byte swap the data, assume the bus_space will do it.

branches: 1.5.2;
armgic_priority_to_ipl is only used in #if 0'd code, so apply that as
well.

branches: 1.4.2;
Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.
Modify the list of devices to include the offset(s) from PERIPHBASE.

branches: 1.3.2; 1.3.4;
Rename kcpuset_copybits() to kcpuset_export_u32() and thus be more specific
about the interface.

Verify the source isn't a dummy source.

branches: 1.1.2;
Add Cortex-A9 support including the ARM Generic Interrupt Controller
and the A9 Global Timer / Watchdog.

build fix: remove includes of opt_gic.h

Remove GIC_SPLFUNCS.

pic: Update ci_cpl in pic_set_priority callback.

Not all ICs need interrupts disabled to update the priority. DAIF accesses
are not cheap, so push the update of ci_cpl from pic_set_priority to the
IC's pic_set_priority callback, and let the IC driver determine whether
or not it needs interrupts disabled.

arm: Use device_set_private for various drivers.

arm: Remove #ifdef DIAGNOSTIC now wrong after KASSERT change.

Objects in question aren't volatile here so access is flushable.

Fix some conditionals to match gicv3 and add some comments to describe
what's going on.

Fixes PR port-evbarm/56420

If an SGI or PPI is established after interrupts are enabled, make sure
we unblock the source on _all_ CPUs and not just the CPU that is
establishing the interrupt.

Make gic_splfuncs optional and disable it by default until it has had
more testing.

Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.

Only target the boot cpu for real with SPI interrupts. I tried to do
this back in 2014, but somehow I missed a spot.

This is a quick-and-dirty fix for the USB stack which expects transfer
completions to be in-order. If interrupts happen across the CPUs then
this isn't guaranteed (yet).

kern/55243 panic at usb_transfer_complete() on raspberry pi 4

branches: 1.46.2;
If we are committing a deferred splhigh() to hardware, no need to continue.

Apply PMR optimizations from gicv3

Avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.

Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.

branches: 1.42.2;
G/C arm/atomic.h

Remove CPU ID test in armgic_match. Perfectly normal to have GIC in
non-Cortex cores.

Avoid undefined behaviour. Detected by KUBSAN.

Fix "left shift of 255 by 24 places cannot be represented in type 'int'"
warning from UBSan.

branches: 1.38.4; 1.38.10;
Use intr_establish_xname

armgic_ipi_send: use GIC interface number, not CPU index, when setting
the target(s) for an IPI.

Update sc_mptargets atomically, as PEs will be started up in parallel w/o locking here

Support pic_set_affinity and pic_get_affinity

branches: 1.34.2;
Cover all pic_maxsources lines for armgic_cpu_init_priorities() and
armgic_cpu_update_priorities().

Previously only the first 32 lines were covered, which is significantly
less than the 1000-some interrupt lines possible.

Only relevant to MULTIPROCESSOR configurations.

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.32.2;
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC

The priority level is changed by writing to GICC_PMR with interrupts
disabled. However, interrupts are enabled/disabled downstream of the GICC
at the CPU. When raising priority level, there is a window between the time
that interrupts are disabled and the GICC_PMR register is written. If an
interrupt occurs at a previously allowed priority before GICC_PMR is
changed, the CPU will receive the signal when interrupts are re-enabled.
At this time, GICC_PMR is now the new priority level, so reads of
GICC_IAR will report a spurious IRQ.

Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
there is at least one pending IRQ.

KNF

ARM Trusted Firmware reserves SGIs 8-15 for secure use. Even without ATF,
U-Boot on some platforms may use SGIs in this range for the PSCI
implementation.

Change ARMGIC_IPI_BASE to 0 from (16 - NIPI) and add a compile-time assert
to ensure that we don't end up with a conflict.

Revert the KERNHIST for now it causes problems

If we see GICC_IAR_IRQ_SSPURIOUS we should also stop looking for irqs

Wrap long line

Print the GICC_IIDR when AB_DEBUG

Add 'armgichist' KERNHIST for (future) debugging.

Don't assume that CPU index = GIC CPU interface number. We can determine
the current CPU interface number by reading from the read-only
GICD_ITARGETSR0 through GICD_ITARGETSR7 registers.

This gets interrupts working on Exynos 5422, where the boot processor has
GIC CPU interface #4.

Clean out some #if 0'ed or //'ed code

Initialise all the SGI/PPI priorities for all CPUs to mask the interrupts

branches: 1.21.2;
Use an FDT-based ARM_INTR_IMPL for Tegra.

Adjust some of IPLs of various IPIs.

Add separate IPI routines for IPI_AST and IPI_KPREEMPT.

Add a pic_cpus to the softc which specifies which cpus the pic can send
IPIs to. For GIC, initialize pic_cpus to kcpuset_running since it can handle
all the cpus.

All SGIs are MPSAFE so establish them as such.

Trailing whitespace

G/C armgic_last_priority

in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn when setting irq type (IST_LEVEL/IST_EDGE)

sc_gic_lines is the total number of valid lines but pic_sources[] is sparse; when initializing mpsafe targets make sure to go all the way to the end (sc_pic.pic_maxsources) instead

branches: 1.12.2;
Only target boot cpu for SPIs atm. Fix a couple of bugs in the now
disabled code.

Sprinkle #include "opt_multiprocessor.h"

branches: 1.10.2;
Implement MI IPI interface with cross-call support.

When dealing with the PMR register, only use non-secure priority values.

Move aprint to print sooner.

branches: 1.7.2;
Various MP changes.

Don't byte swap the data, assume the bus_space will do it.

branches: 1.5.2;
armgic_priority_to_ipl is only used in #if 0'd code, so apply that as
well.

branches: 1.4.2;
Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.
Modify the list of devices to include the offset(s) from PERIPHBASE.

branches: 1.3.2; 1.3.4;
Rename kcpuset_copybits() to kcpuset_export_u32() and thus be more specific
about the interface.

Verify the source isn't a dummy source.

branches: 1.1.2;
Add Cortex-A9 support including the ARM Generic Interrupt Controller
and the A9 Global Timer / Watchdog.

arm: Use device_set_private for various drivers.

arm: Remove #ifdef DIAGNOSTIC now wrong after KASSERT change.

Objects in question aren't volatile here so access is flushable.

Fix some conditionals to match gicv3 and add some comments to describe
what's going on.

Fixes PR port-evbarm/56420

If an SGI or PPI is established after interrupts are enabled, make sure
we unblock the source on _all_ CPUs and not just the CPU that is
establishing the interrupt.

Make gic_splfuncs optional and disable it by default until it has had
more testing.

Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.

Only target the boot cpu for real with SPI interrupts. I tried to do
this back in 2014, but somehow I missed a spot.

This is a quick-and-dirty fix for the USB stack which expects transfer
completions to be in-order. If interrupts happen across the CPUs then
this isn't guaranteed (yet).

kern/55243 panic at usb_transfer_complete() on raspberry pi 4

branches: 1.46.2;
If we are committing a deferred splhigh() to hardware, no need to continue.

Apply PMR optimizations from gicv3

Avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.

Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.

branches: 1.42.2;
G/C arm/atomic.h

Remove CPU ID test in armgic_match. Perfectly normal to have GIC in
non-Cortex cores.

Avoid undefined behaviour. Detected by KUBSAN.

Fix "left shift of 255 by 24 places cannot be represented in type 'int'"
warning from UBSan.

branches: 1.38.4; 1.38.10;
Use intr_establish_xname

armgic_ipi_send: use GIC interface number, not CPU index, when setting
the target(s) for an IPI.

Update sc_mptargets atomically, as PEs will be started up in parallel w/o locking here

Support pic_set_affinity and pic_get_affinity

branches: 1.34.2;
Cover all pic_maxsources lines for armgic_cpu_init_priorities() and
armgic_cpu_update_priorities().

Previously only the first 32 lines were covered, which is significantly
less than the 1000-some interrupt lines possible.

Only relevant to MULTIPROCESSOR configurations.

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.32.2;
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC

The priority level is changed by writing to GICC_PMR with interrupts
disabled. However, interrupts are enabled/disabled downstream of the GICC
at the CPU. When raising priority level, there is a window between the time
that interrupts are disabled and the GICC_PMR register is written. If an
interrupt occurs at a previously allowed priority before GICC_PMR is
changed, the CPU will receive the signal when interrupts are re-enabled.
At this time, GICC_PMR is now the new priority level, so reads of
GICC_IAR will report a spurious IRQ.

Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
there is at least one pending IRQ.

KNF

ARM Trusted Firmware reserves SGIs 8-15 for secure use. Even without ATF,
U-Boot on some platforms may use SGIs in this range for the PSCI
implementation.

Change ARMGIC_IPI_BASE to 0 from (16 - NIPI) and add a compile-time assert
to ensure that we don't end up with a conflict.

Revert the KERNHIST for now it causes problems

If we see GICC_IAR_IRQ_SSPURIOUS we should also stop looking for irqs

Wrap long line

Print the GICC_IIDR when AB_DEBUG

Add 'armgichist' KERNHIST for (future) debugging.

Don't assume that CPU index = GIC CPU interface number. We can determine
the current CPU interface number by reading from the read-only
GICD_ITARGETSR0 through GICD_ITARGETSR7 registers.

This gets interrupts working on Exynos 5422, where the boot processor has
GIC CPU interface #4.

Clean out some #if 0'ed or //'ed code

Initialise all the SGI/PPI priorities for all CPUs to mask the interrupts

branches: 1.21.2;
Use an FDT-based ARM_INTR_IMPL for Tegra.

Adjust some of IPLs of various IPIs.

Add separate IPI routines for IPI_AST and IPI_KPREEMPT.

Add a pic_cpus to the softc which specifies which cpus the pic can send
IPIs to. For GIC, initialize pic_cpus to kcpuset_running since it can handle
all the cpus.

All SGIs are MPSAFE so establish them as such.

Trailing whitespace

G/C armgic_last_priority

in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn when setting irq type (IST_LEVEL/IST_EDGE)

sc_gic_lines is the total number of valid lines but pic_sources[] is sparse; when initializing mpsafe targets make sure to go all the way to the end (sc_pic.pic_maxsources) instead

branches: 1.12.2;
Only target boot cpu for SPIs atm. Fix a couple of bugs in the now
disabled code.

Sprinkle #include "opt_multiprocessor.h"

branches: 1.10.2;
Implement MI IPI interface with cross-call support.

When dealing with the PMR register, only use non-secure priority values.

Move aprint to print sooner.

branches: 1.7.2;
Various MP changes.

Don't byte swap the data, assume the bus_space will do it.

branches: 1.5.2;
armgic_priority_to_ipl is only used in #if 0'd code, so apply that as
well.

branches: 1.4.2;
Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.
Modify the list of devices to include the offset(s) from PERIPHBASE.

branches: 1.3.2; 1.3.4;
Rename kcpuset_copybits() to kcpuset_export_u32() and thus be more specific
about the interface.

Verify the source isn't a dummy source.

branches: 1.1.2;
Add Cortex-A9 support including the ARM Generic Interrupt Controller
and the A9 Global Timer / Watchdog.

arm: Remove #ifdef DIAGNOSTIC now wrong after KASSERT change.

Objects in question aren't volatile here so access is flushable.

Fix some conditionals to match gicv3 and add some comments to describe
what's going on.

Fixes PR port-evbarm/56420

If an SGI or PPI is established after interrupts are enabled, make sure
we unblock the source on _all_ CPUs and not just the CPU that is
establishing the interrupt.

Make gic_splfuncs optional and disable it by default until it has had
more testing.

Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.

Only target the boot cpu for real with SPI interrupts. I tried to do
this back in 2014, but somehow I missed a spot.

This is a quick-and-dirty fix for the USB stack which expects transfer
completions to be in-order. If interrupts happen across the CPUs then
this isn't guaranteed (yet).

kern/55243 panic at usb_transfer_complete() on raspberry pi 4

branches: 1.46.2;
If we are committing a deferred splhigh() to hardware, no need to continue.

Apply PMR optimizations from gicv3

Avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.

Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.

branches: 1.42.2;
G/C arm/atomic.h

Remove CPU ID test in armgic_match. Perfectly normal to have GIC in
non-Cortex cores.

Avoid undefined behaviour. Detected by KUBSAN.

Fix "left shift of 255 by 24 places cannot be represented in type 'int'"
warning from UBSan.

branches: 1.38.4; 1.38.10;
Use intr_establish_xname

armgic_ipi_send: use GIC interface number, not CPU index, when setting
the target(s) for an IPI.

Update sc_mptargets atomically, as PEs will be started up in parallel w/o locking here

Support pic_set_affinity and pic_get_affinity

branches: 1.34.2;
Cover all pic_maxsources lines for armgic_cpu_init_priorities() and
armgic_cpu_update_priorities().

Previously only the first 32 lines were covered, which is significantly
less than the 1000-some interrupt lines possible.

Only relevant to MULTIPROCESSOR configurations.

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.32.2;
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC

The priority level is changed by writing to GICC_PMR with interrupts
disabled. However, interrupts are enabled/disabled downstream of the GICC
at the CPU. When raising priority level, there is a window between the time
that interrupts are disabled and the GICC_PMR register is written. If an
interrupt occurs at a previously allowed priority before GICC_PMR is
changed, the CPU will receive the signal when interrupts are re-enabled.
At this time, GICC_PMR is now the new priority level, so reads of
GICC_IAR will report a spurious IRQ.

Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
there is at least one pending IRQ.

KNF

ARM Trusted Firmware reserves SGIs 8-15 for secure use. Even without ATF,
U-Boot on some platforms may use SGIs in this range for the PSCI
implementation.

Change ARMGIC_IPI_BASE to 0 from (16 - NIPI) and add a compile-time assert
to ensure that we don't end up with a conflict.

Revert the KERNHIST for now it causes problems

If we see GICC_IAR_IRQ_SSPURIOUS we should also stop looking for irqs

Wrap long line

Print the GICC_IIDR when AB_DEBUG

Add 'armgichist' KERNHIST for (future) debugging.

Don't assume that CPU index = GIC CPU interface number. We can determine
the current CPU interface number by reading from the read-only
GICD_ITARGETSR0 through GICD_ITARGETSR7 registers.

This gets interrupts working on Exynos 5422, where the boot processor has
GIC CPU interface #4.

Clean out some #if 0'ed or //'ed code

Initialise all the SGI/PPI priorities for all CPUs to mask the interrupts

branches: 1.21.2;
Use an FDT-based ARM_INTR_IMPL for Tegra.

Adjust some of IPLs of various IPIs.

Add separate IPI routines for IPI_AST and IPI_KPREEMPT.

Add a pic_cpus to the softc which specifies which cpus the pic can send
IPIs to. For GIC, initialize pic_cpus to kcpuset_running since it can handle
all the cpus.

All SGIs are MPSAFE so establish them as such.

Trailing whitespace

G/C armgic_last_priority

in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn when setting irq type (IST_LEVEL/IST_EDGE)

sc_gic_lines is the total number of valid lines but pic_sources[] is sparse; when initializing mpsafe targets make sure to go all the way to the end (sc_pic.pic_maxsources) instead

branches: 1.12.2;
Only target boot cpu for SPIs atm. Fix a couple of bugs in the now
disabled code.

Sprinkle #include "opt_multiprocessor.h"

branches: 1.10.2;
Implement MI IPI interface with cross-call support.

When dealing with the PMR register, only use non-secure priority values.

Move aprint to print sooner.

branches: 1.7.2;
Various MP changes.

Don't byte swap the data, assume the bus_space will do it.

branches: 1.5.2;
armgic_priority_to_ipl is only used in #if 0'd code, so apply that as
well.

branches: 1.4.2;
Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.
Modify the list of devices to include the offset(s) from PERIPHBASE.

branches: 1.3.2; 1.3.4;
Rename kcpuset_copybits() to kcpuset_export_u32() and thus be more specific
about the interface.

Verify the source isn't a dummy source.

branches: 1.1.2;
Add Cortex-A9 support including the ARM Generic Interrupt Controller
and the A9 Global Timer / Watchdog.

Fix some conditionals to match gicv3 and add some comments to describe
what's going on.

Fixes PR port-evbarm/56420

If an SGI or PPI is established after interrupts are enabled, make sure
we unblock the source on _all_ CPUs and not just the CPU that is
establishing the interrupt.

Make gic_splfuncs optional and disable it by default until it has had
more testing.

Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.

Only target the boot cpu for real with SPI interrupts. I tried to do
this back in 2014, but somehow I missed a spot.

This is a quick-and-dirty fix for the USB stack which expects transfer
completions to be in-order. If interrupts happen across the CPUs then
this isn't guaranteed (yet).

kern/55243 panic at usb_transfer_complete() on raspberry pi 4

branches: 1.46.2;
If we are committing a deferred splhigh() to hardware, no need to continue.

Apply PMR optimizations from gicv3

Avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.

Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.

branches: 1.42.2;
G/C arm/atomic.h

Remove CPU ID test in armgic_match. Perfectly normal to have GIC in
non-Cortex cores.

Avoid undefined behaviour. Detected by KUBSAN.

Fix "left shift of 255 by 24 places cannot be represented in type 'int'"
warning from UBSan.

branches: 1.38.4; 1.38.10;
Use intr_establish_xname

armgic_ipi_send: use GIC interface number, not CPU index, when setting
the target(s) for an IPI.

Update sc_mptargets atomically, as PEs will be started up in parallel w/o locking here

Support pic_set_affinity and pic_get_affinity

branches: 1.34.2;
Cover all pic_maxsources lines for armgic_cpu_init_priorities() and
armgic_cpu_update_priorities().

Previously only the first 32 lines were covered, which is significantly
less than the 1000-some interrupt lines possible.

Only relevant to MULTIPROCESSOR configurations.

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.32.2;
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC

The priority level is changed by writing to GICC_PMR with interrupts
disabled. However, interrupts are enabled/disabled downstream of the GICC
at the CPU. When raising priority level, there is a window between the time
that interrupts are disabled and the GICC_PMR register is written. If an
interrupt occurs at a previously allowed priority before GICC_PMR is
changed, the CPU will receive the signal when interrupts are re-enabled.
At this time, GICC_PMR is now the new priority level, so reads of
GICC_IAR will report a spurious IRQ.

Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
there is at least one pending IRQ.

KNF

ARM Trusted Firmware reserves SGIs 8-15 for secure use. Even without ATF,
U-Boot on some platforms may use SGIs in this range for the PSCI
implementation.

Change ARMGIC_IPI_BASE to 0 from (16 - NIPI) and add a compile-time assert
to ensure that we don't end up with a conflict.

Revert the KERNHIST for now it causes problems

If we see GICC_IAR_IRQ_SSPURIOUS we should also stop looking for irqs

Wrap long line

Print the GICC_IIDR when AB_DEBUG

Add 'armgichist' KERNHIST for (future) debugging.

Don't assume that CPU index = GIC CPU interface number. We can determine
the current CPU interface number by reading from the read-only
GICD_ITARGETSR0 through GICD_ITARGETSR7 registers.

This gets interrupts working on Exynos 5422, where the boot processor has
GIC CPU interface #4.

Clean out some #if 0'ed or //'ed code

Initialise all the SGI/PPI priorities for all CPUs to mask the interrupts

branches: 1.21.2;
Use an FDT-based ARM_INTR_IMPL for Tegra.

Adjust some of IPLs of various IPIs.

Add separate IPI routines for IPI_AST and IPI_KPREEMPT.

Add a pic_cpus to the softc which specifies which cpus the pic can send
IPIs to. For GIC, initialize pic_cpus to kcpuset_running since it can handle
all the cpus.

All SGIs are MPSAFE so establish them as such.

Trailing whitespace

G/C armgic_last_priority

in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn when setting irq type (IST_LEVEL/IST_EDGE)

sc_gic_lines is the total number of valid lines but pic_sources[] is sparse; when initializing mpsafe targets make sure to go all the way to the end (sc_pic.pic_maxsources) instead

branches: 1.12.2;
Only target boot cpu for SPIs atm. Fix a couple of bugs in the now
disabled code.

Sprinkle #include "opt_multiprocessor.h"

branches: 1.10.2;
Implement MI IPI interface with cross-call support.

When dealing with the PMR register, only use non-secure priority values.

Move aprint to print sooner.

branches: 1.7.2;
Various MP changes.

Don't byte swap the data, assume the bus_space will do it.

branches: 1.5.2;
armgic_priority_to_ipl is only used in #if 0'd code, so apply that as
well.

branches: 1.4.2;
Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.
Modify the list of devices to include the offset(s) from PERIPHBASE.

branches: 1.3.2; 1.3.4;
Rename kcpuset_copybits() to kcpuset_export_u32() and thus be more specific
about the interface.

Verify the source isn't a dummy source.

branches: 1.1.2;
Add Cortex-A9 support including the ARM Generic Interrupt Controller
and the A9 Global Timer / Watchdog.

If an SGI or PPI is established after interrupts are enabled, make sure
we unblock the source on _all_ CPUs and not just the CPU that is
establishing the interrupt.

Make gic_splfuncs optional and disable it by default until it has had
more testing.

Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.

Only target the boot cpu for real with SPI interrupts. I tried to do
this back in 2014, but somehow I missed a spot.

This is a quick-and-dirty fix for the USB stack which expects transfer
completions to be in-order. If interrupts happen across the CPUs then
this isn't guaranteed (yet).

kern/55243 panic at usb_transfer_complete() on raspberry pi 4

branches: 1.46.2;
If we are committing a deferred splhigh() to hardware, no need to continue.

Apply PMR optimizations from gicv3

Avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.

Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.

branches: 1.42.2;
G/C arm/atomic.h

Remove CPU ID test in armgic_match. Perfectly normal to have GIC in
non-Cortex cores.

Avoid undefined behaviour. Detected by KUBSAN.

Fix "left shift of 255 by 24 places cannot be represented in type 'int'"
warning from UBSan.

branches: 1.38.4; 1.38.10;
Use intr_establish_xname

armgic_ipi_send: use GIC interface number, not CPU index, when setting
the target(s) for an IPI.

Update sc_mptargets atomically, as PEs will be started up in parallel w/o locking here

Support pic_set_affinity and pic_get_affinity

branches: 1.34.2;
Cover all pic_maxsources lines for armgic_cpu_init_priorities() and
armgic_cpu_update_priorities().

Previously only the first 32 lines were covered, which is significantly
less than the 1000-some interrupt lines possible.

Only relevant to MULTIPROCESSOR configurations.

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.32.2;
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC

The priority level is changed by writing to GICC_PMR with interrupts
disabled. However, interrupts are enabled/disabled downstream of the GICC
at the CPU. When raising priority level, there is a window between the time
that interrupts are disabled and the GICC_PMR register is written. If an
interrupt occurs at a previously allowed priority before GICC_PMR is
changed, the CPU will receive the signal when interrupts are re-enabled.
At this time, GICC_PMR is now the new priority level, so reads of
GICC_IAR will report a spurious IRQ.

Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
there is at least one pending IRQ.

KNF

ARM Trusted Firmware reserves SGIs 8-15 for secure use. Even without ATF,
U-Boot on some platforms may use SGIs in this range for the PSCI
implementation.

Change ARMGIC_IPI_BASE to 0 from (16 - NIPI) and add a compile-time assert
to ensure that we don't end up with a conflict.

Revert the KERNHIST for now it causes problems

If we see GICC_IAR_IRQ_SSPURIOUS we should also stop looking for irqs

Wrap long line

Print the GICC_IIDR when AB_DEBUG

Add 'armgichist' KERNHIST for (future) debugging.

Don't assume that CPU index = GIC CPU interface number. We can determine
the current CPU interface number by reading from the read-only
GICD_ITARGETSR0 through GICD_ITARGETSR7 registers.

This gets interrupts working on Exynos 5422, where the boot processor has
GIC CPU interface #4.

Clean out some #if 0'ed or //'ed code

Initialise all the SGI/PPI priorities for all CPUs to mask the interrupts

branches: 1.21.2;
Use an FDT-based ARM_INTR_IMPL for Tegra.

Adjust some of IPLs of various IPIs.

Add separate IPI routines for IPI_AST and IPI_KPREEMPT.

Add a pic_cpus to the softc which specifies which cpus the pic can send
IPIs to. For GIC, initialize pic_cpus to kcpuset_running since it can handle
all the cpus.

All SGIs are MPSAFE so establish them as such.

Trailing whitespace

G/C armgic_last_priority

in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn when setting irq type (IST_LEVEL/IST_EDGE)

sc_gic_lines is the total number of valid lines but pic_sources[] is sparse; when initializing mpsafe targets make sure to go all the way to the end (sc_pic.pic_maxsources) instead

branches: 1.12.2;
Only target boot cpu for SPIs atm. Fix a couple of bugs in the now
disabled code.

Sprinkle #include "opt_multiprocessor.h"

branches: 1.10.2;
Implement MI IPI interface with cross-call support.

When dealing with the PMR register, only use non-secure priority values.

Move aprint to print sooner.

branches: 1.7.2;
Various MP changes.

Don't byte swap the data, assume the bus_space will do it.

branches: 1.5.2;
armgic_priority_to_ipl is only used in #if 0'd code, so apply that as
well.

branches: 1.4.2;
Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.
Modify the list of devices to include the offset(s) from PERIPHBASE.

branches: 1.3.2; 1.3.4;
Rename kcpuset_copybits() to kcpuset_export_u32() and thus be more specific
about the interface.

Verify the source isn't a dummy source.

branches: 1.1.2;
Add Cortex-A9 support including the ARM Generic Interrupt Controller
and the A9 Global Timer / Watchdog.

Make gic_splfuncs optional and disable it by default until it has had
more testing.

Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.

Only target the boot cpu for real with SPI interrupts. I tried to do
this back in 2014, but somehow I missed a spot.

This is a quick-and-dirty fix for the USB stack which expects transfer
completions to be in-order. If interrupts happen across the CPUs then
this isn't guaranteed (yet).

kern/55243 panic at usb_transfer_complete() on raspberry pi 4

branches: 1.46.2;
If we are committing a deferred splhigh() to hardware, no need to continue.

Apply PMR optimizations from gicv3

Avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.

Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.

branches: 1.42.2;
G/C arm/atomic.h

Remove CPU ID test in armgic_match. Perfectly normal to have GIC in
non-Cortex cores.

Avoid undefined behaviour. Detected by KUBSAN.

Fix "left shift of 255 by 24 places cannot be represented in type 'int'"
warning from UBSan.

branches: 1.38.4; 1.38.10;
Use intr_establish_xname

armgic_ipi_send: use GIC interface number, not CPU index, when setting
the target(s) for an IPI.

Update sc_mptargets atomically, as PEs will be started up in parallel w/o locking here

Support pic_set_affinity and pic_get_affinity

branches: 1.34.2;
Cover all pic_maxsources lines for armgic_cpu_init_priorities() and
armgic_cpu_update_priorities().

Previously only the first 32 lines were covered, which is significantly
less than the 1000-some interrupt lines possible.

Only relevant to MULTIPROCESSOR configurations.

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.32.2;
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC

The priority level is changed by writing to GICC_PMR with interrupts
disabled. However, interrupts are enabled/disabled downstream of the GICC
at the CPU. When raising priority level, there is a window between the time
that interrupts are disabled and the GICC_PMR register is written. If an
interrupt occurs at a previously allowed priority before GICC_PMR is
changed, the CPU will receive the signal when interrupts are re-enabled.
At this time, GICC_PMR is now the new priority level, so reads of
GICC_IAR will report a spurious IRQ.

Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
there is at least one pending IRQ.

KNF

ARM Trusted Firmware reserves SGIs 8-15 for secure use. Even without ATF,
U-Boot on some platforms may use SGIs in this range for the PSCI
implementation.

Change ARMGIC_IPI_BASE to 0 from (16 - NIPI) and add a compile-time assert
to ensure that we don't end up with a conflict.

Revert the KERNHIST for now it causes problems

If we see GICC_IAR_IRQ_SSPURIOUS we should also stop looking for irqs

Wrap long line

Print the GICC_IIDR when AB_DEBUG

Add 'armgichist' KERNHIST for (future) debugging.

Don't assume that CPU index = GIC CPU interface number. We can determine
the current CPU interface number by reading from the read-only
GICD_ITARGETSR0 through GICD_ITARGETSR7 registers.

This gets interrupts working on Exynos 5422, where the boot processor has
GIC CPU interface #4.

Clean out some #if 0'ed or //'ed code

Initialise all the SGI/PPI priorities for all CPUs to mask the interrupts

branches: 1.21.2;
Use an FDT-based ARM_INTR_IMPL for Tegra.

Adjust some of IPLs of various IPIs.

Add separate IPI routines for IPI_AST and IPI_KPREEMPT.

Add a pic_cpus to the softc which specifies which cpus the pic can send
IPIs to. For GIC, initialize pic_cpus to kcpuset_running since it can handle
all the cpus.

All SGIs are MPSAFE so establish them as such.

Trailing whitespace

G/C armgic_last_priority

in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn when setting irq type (IST_LEVEL/IST_EDGE)

sc_gic_lines is the total number of valid lines but pic_sources[] is sparse; when initializing mpsafe targets make sure to go all the way to the end (sc_pic.pic_maxsources) instead

branches: 1.12.2;
Only target boot cpu for SPIs atm. Fix a couple of bugs in the now
disabled code.

Sprinkle #include "opt_multiprocessor.h"

branches: 1.10.2;
Implement MI IPI interface with cross-call support.

When dealing with the PMR register, only use non-secure priority values.

Move aprint to print sooner.

branches: 1.7.2;
Various MP changes.

Don't byte swap the data, assume the bus_space will do it.

branches: 1.5.2;
armgic_priority_to_ipl is only used in #if 0'd code, so apply that as
well.

branches: 1.4.2;
Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.
Modify the list of devices to include the offset(s) from PERIPHBASE.

branches: 1.3.2; 1.3.4;
Rename kcpuset_copybits() to kcpuset_export_u32() and thus be more specific
about the interface.

Verify the source isn't a dummy source.

branches: 1.1.2;
Add Cortex-A9 support including the ARM Generic Interrupt Controller
and the A9 Global Timer / Watchdog.

Only target the boot cpu for real with SPI interrupts. I tried to do
this back in 2014, but somehow I missed a spot.

This is a quick-and-dirty fix for the USB stack which expects transfer
completions to be in-order. If interrupts happen across the CPUs then
this isn't guaranteed (yet).

kern/55243 panic at usb_transfer_complete() on raspberry pi 4

If we are committing a deferred splhigh() to hardware, no need to continue.

Apply PMR optimizations from gicv3

Avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.

Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.

branches: 1.42.2;
G/C arm/atomic.h

Remove CPU ID test in armgic_match. Perfectly normal to have GIC in
non-Cortex cores.

Avoid undefined behaviour. Detected by KUBSAN.

Fix "left shift of 255 by 24 places cannot be represented in type 'int'"
warning from UBSan.

branches: 1.38.10;
Use intr_establish_xname

armgic_ipi_send: use GIC interface number, not CPU index, when setting
the target(s) for an IPI.

Update sc_mptargets atomically, as PEs will be started up in parallel w/o locking here

Support pic_set_affinity and pic_get_affinity

branches: 1.34.2;
Cover all pic_maxsources lines for armgic_cpu_init_priorities() and
armgic_cpu_update_priorities().

Previously only the first 32 lines were covered, which is significantly
less than the 1000-some interrupt lines possible.

Only relevant to MULTIPROCESSOR configurations.

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.32.2;
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC

The priority level is changed by writing to GICC_PMR with interrupts
disabled. However, interrupts are enabled/disabled downstream of the GICC
at the CPU. When raising priority level, there is a window between the time
that interrupts are disabled and the GICC_PMR register is written. If an
interrupt occurs at a previously allowed priority before GICC_PMR is
changed, the CPU will receive the signal when interrupts are re-enabled.
At this time, GICC_PMR is now the new priority level, so reads of
GICC_IAR will report a spurious IRQ.

Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
there is at least one pending IRQ.

KNF

ARM Trusted Firmware reserves SGIs 8-15 for secure use. Even without ATF,
U-Boot on some platforms may use SGIs in this range for the PSCI
implementation.

Change ARMGIC_IPI_BASE to 0 from (16 - NIPI) and add a compile-time assert
to ensure that we don't end up with a conflict.

Revert the KERNHIST for now it causes problems

If we see GICC_IAR_IRQ_SSPURIOUS we should also stop looking for irqs

Wrap long line

Print the GICC_IIDR when AB_DEBUG

Add 'armgichist' KERNHIST for (future) debugging.

Don't assume that CPU index = GIC CPU interface number. We can determine
the current CPU interface number by reading from the read-only
GICD_ITARGETSR0 through GICD_ITARGETSR7 registers.

This gets interrupts working on Exynos 5422, where the boot processor has
GIC CPU interface #4.

Clean out some #if 0'ed or //'ed code

Initialise all the SGI/PPI priorities for all CPUs to mask the interrupts

branches: 1.21.2;
Use an FDT-based ARM_INTR_IMPL for Tegra.

Adjust some of IPLs of various IPIs.

Add separate IPI routines for IPI_AST and IPI_KPREEMPT.

Add a pic_cpus to the softc which specifies which cpus the pic can send
IPIs to. For GIC, initialize pic_cpus to kcpuset_running since it can handle
all the cpus.

All SGIs are MPSAFE so establish them as such.

Trailing whitespace

G/C armgic_last_priority

in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn when setting irq type (IST_LEVEL/IST_EDGE)

sc_gic_lines is the total number of valid lines but pic_sources[] is sparse; when initializing mpsafe targets make sure to go all the way to the end (sc_pic.pic_maxsources) instead

branches: 1.12.2;
Only target boot cpu for SPIs atm. Fix a couple of bugs in the now
disabled code.

Sprinkle #include "opt_multiprocessor.h"

branches: 1.10.2;
Implement MI IPI interface with cross-call support.

When dealing with the PMR register, only use non-secure priority values.

Move aprint to print sooner.

branches: 1.7.2;
Various MP changes.

Don't byte swap the data, assume the bus_space will do it.

branches: 1.5.2;
armgic_priority_to_ipl is only used in #if 0'd code, so apply that as
well.

branches: 1.4.2;
Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.
Modify the list of devices to include the offset(s) from PERIPHBASE.

branches: 1.3.2; 1.3.4;
Rename kcpuset_copybits() to kcpuset_export_u32() and thus be more specific
about the interface.

Verify the source isn't a dummy source.

branches: 1.1.2;
Add Cortex-A9 support including the ARM Generic Interrupt Controller
and the A9 Global Timer / Watchdog.

If we are committing a deferred splhigh() to hardware, no need to continue.

Apply PMR optimizations from gicv3

Avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.

Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.

branches: 1.42.2;
G/C arm/atomic.h

Remove CPU ID test in armgic_match. Perfectly normal to have GIC in
non-Cortex cores.

Avoid undefined behaviour. Detected by KUBSAN.

Fix "left shift of 255 by 24 places cannot be represented in type 'int'"
warning from UBSan.

branches: 1.38.10;
Use intr_establish_xname

armgic_ipi_send: use GIC interface number, not CPU index, when setting
the target(s) for an IPI.

Update sc_mptargets atomically, as PEs will be started up in parallel w/o locking here

Support pic_set_affinity and pic_get_affinity

branches: 1.34.2;
Cover all pic_maxsources lines for armgic_cpu_init_priorities() and
armgic_cpu_update_priorities().

Previously only the first 32 lines were covered, which is significantly
less than the 1000-some interrupt lines possible.

Only relevant to MULTIPROCESSOR configurations.

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.32.2;
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC

The priority level is changed by writing to GICC_PMR with interrupts
disabled. However, interrupts are enabled/disabled downstream of the GICC
at the CPU. When raising priority level, there is a window between the time
that interrupts are disabled and the GICC_PMR register is written. If an
interrupt occurs at a previously allowed priority before GICC_PMR is
changed, the CPU will receive the signal when interrupts are re-enabled.
At this time, GICC_PMR is now the new priority level, so reads of
GICC_IAR will report a spurious IRQ.

Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
there is at least one pending IRQ.

KNF

ARM Trusted Firmware reserves SGIs 8-15 for secure use. Even without ATF,
U-Boot on some platforms may use SGIs in this range for the PSCI
implementation.

Change ARMGIC_IPI_BASE to 0 from (16 - NIPI) and add a compile-time assert
to ensure that we don't end up with a conflict.

Revert the KERNHIST for now it causes problems

If we see GICC_IAR_IRQ_SSPURIOUS we should also stop looking for irqs

Wrap long line

Print the GICC_IIDR when AB_DEBUG

Add 'armgichist' KERNHIST for (future) debugging.

Don't assume that CPU index = GIC CPU interface number. We can determine
the current CPU interface number by reading from the read-only
GICD_ITARGETSR0 through GICD_ITARGETSR7 registers.

This gets interrupts working on Exynos 5422, where the boot processor has
GIC CPU interface #4.

Clean out some #if 0'ed or //'ed code

Initialise all the SGI/PPI priorities for all CPUs to mask the interrupts

branches: 1.21.2;
Use an FDT-based ARM_INTR_IMPL for Tegra.