extent(9) -> vmem(9)

Merge thorpej-cfargs2.

branches: 1.47.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.46.2;
malloc(9) -> kmem(9)

branches: 1.45.2;
Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

branches: 1.42.18;
PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.41.6;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

use sprintf.

branches: 1.39.2;
split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

branches: 1.38.6;
converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.37.2; 1.37.6;
#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

Merge forward from matt-nb5-mips64.
Adapt to new interrupt/spl framework.
Add LP64 support.

branches: 1.33.2; 1.33.4;
Use fixed pci_intr_handle_t per device number regardless of pin and swiz.

Tested the following multifunction card and devices over ppb(4)
on Express5800/230 (JC94):

---
uhci0 at pci0 dev 4 function 0: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci0: interrupting at int C
usb0 at uhci0: USB revision 1.0
uhci1 at pci0 dev 4 function 1: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci1: interrupting at int C
usb1 at uhci1: USB revision 1.0
ehci0 at pci0 dev 4 function 2: VIA Technologies VT8237 EHCI USB Controller (rev. 0x63)
ehci0: interrupting at int C
ehci0: dropped intr workaround enabled
ehci0: EHCI version 1.0
ehci0: companion controllers, 2 ports each: uhci0 uhci1
usb2 at ehci0: USB revision 2.0
fwohci0 at pci0 dev 4 function 3: VIA Technologies VT6306 IEEE 1394 Host Controller (rev. 0x46)
fwohci0: interrupting at int C
fwohci0: OHCI version 1.0 (ROM=1)
fwohci0: No. of Isochronous channels is 4.
fwohci0: EUI64 00:01:08:00:37:02:79:4f
fwohci0: Phy 1394a available S400, 3 ports.
fwohci0: Link S400, max_rec 1024 bytes.
fwohci0: max_rec 1024 -> 2048
ieee1394if0 at fwohci0: IEEE1394 bus
fwip0 at ieee1394if0: IP over IEEE1394
fwohci0: Initiate bus reset
vge0 at pci0 dev 4 function 4: VIA VT612X Gigabit Ethernet (rev. 0x11)
vge0: interrupting at int C
vge0: Ethernet address: 00:01:08:00:b1:71
ciphy0 at vge0 phy 1: Cicada CS8201 10/100/1000TX PHY, rev. 2
ciphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FDX, auto
:
---
ppb0 at pci0 dev 4 function 0: Digital Equipment DC21154 PCI-PCI Bridge (rev. 0x05)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled
ex0 at pci1 dev 4 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex0: interrupting at int C
ex0: MAC address 00:01:03:ce:74:48
bmtphy0 at ex0 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
ex1 at pci1 dev 5 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex1: interrupting at int C
ex1: MAC address 00:01:03:ce:74:49
bmtphy1 at ex1 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
:

branches: 1.32.6; 1.32.14; 1.32.16; 1.32.18;
Split device_t/softc with misc related changes.

branches: 1.31.2; 1.31.4;
Remove clause 3 and 4 from TNF licenses

branches: 1.30.2; 1.30.4;
Fix spl(9) botch in cpu_intr() on arc:
Don't enable unhandled interrupts before all interrupts are processed,
and also change all interrupt handlers to return processed MIPS_INT_MASK
values, rather than masked values of them.

branches: 1.29.20; 1.29.36; 1.29.40;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.28.10;
Misc minor cleanup for arc interrupt handlers:
- always enable options MIPS3_ENABLE_CLOCK_INTR and just clear the compare
register in cpu_intr() to make CLKF_BASE() works
properly
- prepare only possible number of cpu_inttab
- use macro for interrupt priority number passed to arc_set_intr()
to avoid confusion
- merge arc_hardware_intr() into cpu_intr()
- check independent timer interrupt first in cpu_intr()
- tweak MIPS_SR_INT_IE before calling hardclock timer handlers so that
spllowersoftclock(9) will be invoked properly in hardclock(9)
- reenable interrupt for timer in cpu_intr() rather than each timer handlers

okay'ed by soda.

Note the real fix is to make CLKF_BASE() check all independent
interrupt sources including jazz and isa devices.

branches: 1.27.4;
In !defined(PCI_NETBSD_CONFIGURE) case, check PCI_ID_REG and PCI_CLASS_REG
before CSR fixup.

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

Add support for pci_configure_bus(9) (a.k.a. options PCI_NETBSD_CONFIGURE)
so that PCI devices over ppb(4) work properly on PCI based NEC machines.

Tested on my NEC JC94 (Express5800/230) and 3Com 3C982-TXM,
which has a DEC/Intel 21154 PCI-PCI bridge and two 3C920 Ethernet chips.

Ack interrupts only if they are actually handled.

Misc cosmetics.

Include "ioconf.h" rather than declare struct cfdriver foo_cd in each file.

branches: 1.21.4; 1.21.6; 1.21.8; 1.21.10; 1.21.12;
Explicitly enable interrupts before softintr is handled as noted
in the TODO file. At least this fixes "sn0: receive buffers exhausted"
messages on my NEC-JC94.

XXX: does anyone know what "Dont reenable" comment means, which was
XXX: there since initial import of pica (not arc).

branches: 1.20.8; 1.20.14;
Make all intr_mask value types uint32_t rather than int, u_int,
or unsigned etc.

- remove __P()
- use ANSI function decls
- u_intNN_t -> uintNN_t
- some KNF

branches: 1.18.4;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

Count necpb interrupts with evcnt(9).

__KERNEL_RCSID()

branches: 1.15.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use aprint_normal for cfprint routines.

Use CFATTACH_DECL().

Declare all cfattach structures const.

* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.10.2;
Implement pci_decompose_tag().

branches: 1.9.6;
Disable PCI expansion ROM for normal operation.
It fixes memory mapped I/O problems on some devices.
(from port-arc ML)

branches: 1.8.2;
rename statically allocated software context which is needed for
console initialization, from "struct necpb_config necpb_configuration;"
to "struct necpb_context necpb_main_context".
to resolve naming conflicts with "struct XXX_config *XXX_conf;"
which describes platform-dependent configuration variants.

branches: 1.7.2;
Adapt to pci_intr_map change.

Switch pica to jazzio.
Split shared MD portion between algor and jazzio.

branches: 1.5.2;
Fix a printf format.

remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>

remove/move more mach vm header files:

<vm/pglist.h> -> <uvm/uvm_pglist.h>
<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
<vm/vm_object.h> -> nothing
<vm/vm_pager.h> -> into <uvm/uvm_pager.h>

also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.

branches: 1.2.4;
TGA console initialization for NEC RISCstation 2250,
contributed by Shuichiro URATA <ur@a-r.org>

NEC RISCstation 2250 (RD-94) PCI bus support,
contributed by Shuichiro URATA <ur@a-r.org>

Merge thorpej-cfargs2.

branches: 1.47.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.46.2;
malloc(9) -> kmem(9)

branches: 1.45.2;
Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

branches: 1.42.18;
PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.41.6;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

use sprintf.

branches: 1.39.2;
split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

branches: 1.38.6;
converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.37.2; 1.37.6;
#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

Merge forward from matt-nb5-mips64.
Adapt to new interrupt/spl framework.
Add LP64 support.

branches: 1.33.2; 1.33.4;
Use fixed pci_intr_handle_t per device number regardless of pin and swiz.

Tested the following multifunction card and devices over ppb(4)
on Express5800/230 (JC94):

---
uhci0 at pci0 dev 4 function 0: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci0: interrupting at int C
usb0 at uhci0: USB revision 1.0
uhci1 at pci0 dev 4 function 1: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci1: interrupting at int C
usb1 at uhci1: USB revision 1.0
ehci0 at pci0 dev 4 function 2: VIA Technologies VT8237 EHCI USB Controller (rev. 0x63)
ehci0: interrupting at int C
ehci0: dropped intr workaround enabled
ehci0: EHCI version 1.0
ehci0: companion controllers, 2 ports each: uhci0 uhci1
usb2 at ehci0: USB revision 2.0
fwohci0 at pci0 dev 4 function 3: VIA Technologies VT6306 IEEE 1394 Host Controller (rev. 0x46)
fwohci0: interrupting at int C
fwohci0: OHCI version 1.0 (ROM=1)
fwohci0: No. of Isochronous channels is 4.
fwohci0: EUI64 00:01:08:00:37:02:79:4f
fwohci0: Phy 1394a available S400, 3 ports.
fwohci0: Link S400, max_rec 1024 bytes.
fwohci0: max_rec 1024 -> 2048
ieee1394if0 at fwohci0: IEEE1394 bus
fwip0 at ieee1394if0: IP over IEEE1394
fwohci0: Initiate bus reset
vge0 at pci0 dev 4 function 4: VIA VT612X Gigabit Ethernet (rev. 0x11)
vge0: interrupting at int C
vge0: Ethernet address: 00:01:08:00:b1:71
ciphy0 at vge0 phy 1: Cicada CS8201 10/100/1000TX PHY, rev. 2
ciphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FDX, auto
:
---
ppb0 at pci0 dev 4 function 0: Digital Equipment DC21154 PCI-PCI Bridge (rev. 0x05)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled
ex0 at pci1 dev 4 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex0: interrupting at int C
ex0: MAC address 00:01:03:ce:74:48
bmtphy0 at ex0 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
ex1 at pci1 dev 5 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex1: interrupting at int C
ex1: MAC address 00:01:03:ce:74:49
bmtphy1 at ex1 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
:

branches: 1.32.6; 1.32.14; 1.32.16; 1.32.18;
Split device_t/softc with misc related changes.

branches: 1.31.2; 1.31.4;
Remove clause 3 and 4 from TNF licenses

branches: 1.30.2; 1.30.4;
Fix spl(9) botch in cpu_intr() on arc:
Don't enable unhandled interrupts before all interrupts are processed,
and also change all interrupt handlers to return processed MIPS_INT_MASK
values, rather than masked values of them.

branches: 1.29.20; 1.29.36; 1.29.40;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.28.10;
Misc minor cleanup for arc interrupt handlers:
- always enable options MIPS3_ENABLE_CLOCK_INTR and just clear the compare
register in cpu_intr() to make CLKF_BASE() works
properly
- prepare only possible number of cpu_inttab
- use macro for interrupt priority number passed to arc_set_intr()
to avoid confusion
- merge arc_hardware_intr() into cpu_intr()
- check independent timer interrupt first in cpu_intr()
- tweak MIPS_SR_INT_IE before calling hardclock timer handlers so that
spllowersoftclock(9) will be invoked properly in hardclock(9)
- reenable interrupt for timer in cpu_intr() rather than each timer handlers

okay'ed by soda.

Note the real fix is to make CLKF_BASE() check all independent
interrupt sources including jazz and isa devices.

branches: 1.27.4;
In !defined(PCI_NETBSD_CONFIGURE) case, check PCI_ID_REG and PCI_CLASS_REG
before CSR fixup.

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

Add support for pci_configure_bus(9) (a.k.a. options PCI_NETBSD_CONFIGURE)
so that PCI devices over ppb(4) work properly on PCI based NEC machines.

Tested on my NEC JC94 (Express5800/230) and 3Com 3C982-TXM,
which has a DEC/Intel 21154 PCI-PCI bridge and two 3C920 Ethernet chips.

Ack interrupts only if they are actually handled.

Misc cosmetics.

Include "ioconf.h" rather than declare struct cfdriver foo_cd in each file.

branches: 1.21.4; 1.21.6; 1.21.8; 1.21.10; 1.21.12;
Explicitly enable interrupts before softintr is handled as noted
in the TODO file. At least this fixes "sn0: receive buffers exhausted"
messages on my NEC-JC94.

XXX: does anyone know what "Dont reenable" comment means, which was
XXX: there since initial import of pica (not arc).

branches: 1.20.8; 1.20.14;
Make all intr_mask value types uint32_t rather than int, u_int,
or unsigned etc.

- remove __P()
- use ANSI function decls
- u_intNN_t -> uintNN_t
- some KNF

branches: 1.18.4;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

Count necpb interrupts with evcnt(9).

__KERNEL_RCSID()

branches: 1.15.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use aprint_normal for cfprint routines.

Use CFATTACH_DECL().

Declare all cfattach structures const.

* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.10.2;
Implement pci_decompose_tag().

branches: 1.9.6;
Disable PCI expansion ROM for normal operation.
It fixes memory mapped I/O problems on some devices.
(from port-arc ML)

branches: 1.8.2;
rename statically allocated software context which is needed for
console initialization, from "struct necpb_config necpb_configuration;"
to "struct necpb_context necpb_main_context".
to resolve naming conflicts with "struct XXX_config *XXX_conf;"
which describes platform-dependent configuration variants.

branches: 1.7.2;
Adapt to pci_intr_map change.

Switch pica to jazzio.
Split shared MD portion between algor and jazzio.

branches: 1.5.2;
Fix a printf format.

remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>

remove/move more mach vm header files:

<vm/pglist.h> -> <uvm/uvm_pglist.h>
<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
<vm/vm_object.h> -> nothing
<vm/vm_pager.h> -> into <uvm/uvm_pager.h>

also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.

branches: 1.2.4;
TGA console initialization for NEC RISCstation 2250,
contributed by Shuichiro URATA <ur@a-r.org>

NEC RISCstation 2250 (RD-94) PCI bus support,
contributed by Shuichiro URATA <ur@a-r.org>

Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.46.2;
malloc(9) -> kmem(9)

branches: 1.45.2;
Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

branches: 1.42.18;
PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.41.6;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

use sprintf.

branches: 1.39.2;
split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

branches: 1.38.6;
converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.37.2; 1.37.6;
#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

Merge forward from matt-nb5-mips64.
Adapt to new interrupt/spl framework.
Add LP64 support.

branches: 1.33.2; 1.33.4;
Use fixed pci_intr_handle_t per device number regardless of pin and swiz.

Tested the following multifunction card and devices over ppb(4)
on Express5800/230 (JC94):

---
uhci0 at pci0 dev 4 function 0: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci0: interrupting at int C
usb0 at uhci0: USB revision 1.0
uhci1 at pci0 dev 4 function 1: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci1: interrupting at int C
usb1 at uhci1: USB revision 1.0
ehci0 at pci0 dev 4 function 2: VIA Technologies VT8237 EHCI USB Controller (rev. 0x63)
ehci0: interrupting at int C
ehci0: dropped intr workaround enabled
ehci0: EHCI version 1.0
ehci0: companion controllers, 2 ports each: uhci0 uhci1
usb2 at ehci0: USB revision 2.0
fwohci0 at pci0 dev 4 function 3: VIA Technologies VT6306 IEEE 1394 Host Controller (rev. 0x46)
fwohci0: interrupting at int C
fwohci0: OHCI version 1.0 (ROM=1)
fwohci0: No. of Isochronous channels is 4.
fwohci0: EUI64 00:01:08:00:37:02:79:4f
fwohci0: Phy 1394a available S400, 3 ports.
fwohci0: Link S400, max_rec 1024 bytes.
fwohci0: max_rec 1024 -> 2048
ieee1394if0 at fwohci0: IEEE1394 bus
fwip0 at ieee1394if0: IP over IEEE1394
fwohci0: Initiate bus reset
vge0 at pci0 dev 4 function 4: VIA VT612X Gigabit Ethernet (rev. 0x11)
vge0: interrupting at int C
vge0: Ethernet address: 00:01:08:00:b1:71
ciphy0 at vge0 phy 1: Cicada CS8201 10/100/1000TX PHY, rev. 2
ciphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FDX, auto
:
---
ppb0 at pci0 dev 4 function 0: Digital Equipment DC21154 PCI-PCI Bridge (rev. 0x05)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled
ex0 at pci1 dev 4 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex0: interrupting at int C
ex0: MAC address 00:01:03:ce:74:48
bmtphy0 at ex0 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
ex1 at pci1 dev 5 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex1: interrupting at int C
ex1: MAC address 00:01:03:ce:74:49
bmtphy1 at ex1 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
:

branches: 1.32.6; 1.32.14; 1.32.16; 1.32.18;
Split device_t/softc with misc related changes.

branches: 1.31.2; 1.31.4;
Remove clause 3 and 4 from TNF licenses

branches: 1.30.2; 1.30.4;
Fix spl(9) botch in cpu_intr() on arc:
Don't enable unhandled interrupts before all interrupts are processed,
and also change all interrupt handlers to return processed MIPS_INT_MASK
values, rather than masked values of them.

branches: 1.29.20; 1.29.36; 1.29.40;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.28.10;
Misc minor cleanup for arc interrupt handlers:
- always enable options MIPS3_ENABLE_CLOCK_INTR and just clear the compare
register in cpu_intr() to make CLKF_BASE() works
properly
- prepare only possible number of cpu_inttab
- use macro for interrupt priority number passed to arc_set_intr()
to avoid confusion
- merge arc_hardware_intr() into cpu_intr()
- check independent timer interrupt first in cpu_intr()
- tweak MIPS_SR_INT_IE before calling hardclock timer handlers so that
spllowersoftclock(9) will be invoked properly in hardclock(9)
- reenable interrupt for timer in cpu_intr() rather than each timer handlers

okay'ed by soda.

Note the real fix is to make CLKF_BASE() check all independent
interrupt sources including jazz and isa devices.

branches: 1.27.4;
In !defined(PCI_NETBSD_CONFIGURE) case, check PCI_ID_REG and PCI_CLASS_REG
before CSR fixup.

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

Add support for pci_configure_bus(9) (a.k.a. options PCI_NETBSD_CONFIGURE)
so that PCI devices over ppb(4) work properly on PCI based NEC machines.

Tested on my NEC JC94 (Express5800/230) and 3Com 3C982-TXM,
which has a DEC/Intel 21154 PCI-PCI bridge and two 3C920 Ethernet chips.

Ack interrupts only if they are actually handled.

Misc cosmetics.

Include "ioconf.h" rather than declare struct cfdriver foo_cd in each file.

branches: 1.21.4; 1.21.6; 1.21.8; 1.21.10; 1.21.12;
Explicitly enable interrupts before softintr is handled as noted
in the TODO file. At least this fixes "sn0: receive buffers exhausted"
messages on my NEC-JC94.

XXX: does anyone know what "Dont reenable" comment means, which was
XXX: there since initial import of pica (not arc).

branches: 1.20.8; 1.20.14;
Make all intr_mask value types uint32_t rather than int, u_int,
or unsigned etc.

- remove __P()
- use ANSI function decls
- u_intNN_t -> uintNN_t
- some KNF

branches: 1.18.4;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

Count necpb interrupts with evcnt(9).

__KERNEL_RCSID()

branches: 1.15.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use aprint_normal for cfprint routines.

Use CFATTACH_DECL().

Declare all cfattach structures const.

* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.10.2;
Implement pci_decompose_tag().

branches: 1.9.6;
Disable PCI expansion ROM for normal operation.
It fixes memory mapped I/O problems on some devices.
(from port-arc ML)

branches: 1.8.2;
rename statically allocated software context which is needed for
console initialization, from "struct necpb_config necpb_configuration;"
to "struct necpb_context necpb_main_context".
to resolve naming conflicts with "struct XXX_config *XXX_conf;"
which describes platform-dependent configuration variants.

branches: 1.7.2;
Adapt to pci_intr_map change.

Switch pica to jazzio.
Split shared MD portion between algor and jazzio.

branches: 1.5.2;
Fix a printf format.

remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>

remove/move more mach vm header files:

<vm/pglist.h> -> <uvm/uvm_pglist.h>
<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
<vm/vm_object.h> -> nothing
<vm/vm_pager.h> -> into <uvm/uvm_pager.h>

also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.

branches: 1.2.4;
TGA console initialization for NEC RISCstation 2250,
contributed by Shuichiro URATA <ur@a-r.org>

NEC RISCstation 2250 (RD-94) PCI bus support,
contributed by Shuichiro URATA <ur@a-r.org>

malloc(9) -> kmem(9)

Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

branches: 1.42.18;
PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.41.6;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

use sprintf.

branches: 1.39.2;
split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

branches: 1.38.6;
converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.37.2; 1.37.6;
#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

Merge forward from matt-nb5-mips64.
Adapt to new interrupt/spl framework.
Add LP64 support.

branches: 1.33.2; 1.33.4;
Use fixed pci_intr_handle_t per device number regardless of pin and swiz.

Tested the following multifunction card and devices over ppb(4)
on Express5800/230 (JC94):

---
uhci0 at pci0 dev 4 function 0: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci0: interrupting at int C
usb0 at uhci0: USB revision 1.0
uhci1 at pci0 dev 4 function 1: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci1: interrupting at int C
usb1 at uhci1: USB revision 1.0
ehci0 at pci0 dev 4 function 2: VIA Technologies VT8237 EHCI USB Controller (rev. 0x63)
ehci0: interrupting at int C
ehci0: dropped intr workaround enabled
ehci0: EHCI version 1.0
ehci0: companion controllers, 2 ports each: uhci0 uhci1
usb2 at ehci0: USB revision 2.0
fwohci0 at pci0 dev 4 function 3: VIA Technologies VT6306 IEEE 1394 Host Controller (rev. 0x46)
fwohci0: interrupting at int C
fwohci0: OHCI version 1.0 (ROM=1)
fwohci0: No. of Isochronous channels is 4.
fwohci0: EUI64 00:01:08:00:37:02:79:4f
fwohci0: Phy 1394a available S400, 3 ports.
fwohci0: Link S400, max_rec 1024 bytes.
fwohci0: max_rec 1024 -> 2048
ieee1394if0 at fwohci0: IEEE1394 bus
fwip0 at ieee1394if0: IP over IEEE1394
fwohci0: Initiate bus reset
vge0 at pci0 dev 4 function 4: VIA VT612X Gigabit Ethernet (rev. 0x11)
vge0: interrupting at int C
vge0: Ethernet address: 00:01:08:00:b1:71
ciphy0 at vge0 phy 1: Cicada CS8201 10/100/1000TX PHY, rev. 2
ciphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FDX, auto
:
---
ppb0 at pci0 dev 4 function 0: Digital Equipment DC21154 PCI-PCI Bridge (rev. 0x05)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled
ex0 at pci1 dev 4 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex0: interrupting at int C
ex0: MAC address 00:01:03:ce:74:48
bmtphy0 at ex0 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
ex1 at pci1 dev 5 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex1: interrupting at int C
ex1: MAC address 00:01:03:ce:74:49
bmtphy1 at ex1 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
:

branches: 1.32.6; 1.32.14; 1.32.16; 1.32.18;
Split device_t/softc with misc related changes.

branches: 1.31.2; 1.31.4;
Remove clause 3 and 4 from TNF licenses

branches: 1.30.2; 1.30.4;
Fix spl(9) botch in cpu_intr() on arc:
Don't enable unhandled interrupts before all interrupts are processed,
and also change all interrupt handlers to return processed MIPS_INT_MASK
values, rather than masked values of them.

branches: 1.29.20; 1.29.36; 1.29.40;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.28.10;
Misc minor cleanup for arc interrupt handlers:
- always enable options MIPS3_ENABLE_CLOCK_INTR and just clear the compare
register in cpu_intr() to make CLKF_BASE() works
properly
- prepare only possible number of cpu_inttab
- use macro for interrupt priority number passed to arc_set_intr()
to avoid confusion
- merge arc_hardware_intr() into cpu_intr()
- check independent timer interrupt first in cpu_intr()
- tweak MIPS_SR_INT_IE before calling hardclock timer handlers so that
spllowersoftclock(9) will be invoked properly in hardclock(9)
- reenable interrupt for timer in cpu_intr() rather than each timer handlers

okay'ed by soda.

Note the real fix is to make CLKF_BASE() check all independent
interrupt sources including jazz and isa devices.

branches: 1.27.4;
In !defined(PCI_NETBSD_CONFIGURE) case, check PCI_ID_REG and PCI_CLASS_REG
before CSR fixup.

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

Add support for pci_configure_bus(9) (a.k.a. options PCI_NETBSD_CONFIGURE)
so that PCI devices over ppb(4) work properly on PCI based NEC machines.

Tested on my NEC JC94 (Express5800/230) and 3Com 3C982-TXM,
which has a DEC/Intel 21154 PCI-PCI bridge and two 3C920 Ethernet chips.

Ack interrupts only if they are actually handled.

Misc cosmetics.

Include "ioconf.h" rather than declare struct cfdriver foo_cd in each file.

branches: 1.21.4; 1.21.6; 1.21.8; 1.21.10; 1.21.12;
Explicitly enable interrupts before softintr is handled as noted
in the TODO file. At least this fixes "sn0: receive buffers exhausted"
messages on my NEC-JC94.

XXX: does anyone know what "Dont reenable" comment means, which was
XXX: there since initial import of pica (not arc).

branches: 1.20.8; 1.20.14;
Make all intr_mask value types uint32_t rather than int, u_int,
or unsigned etc.

- remove __P()
- use ANSI function decls
- u_intNN_t -> uintNN_t
- some KNF

branches: 1.18.4;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

Count necpb interrupts with evcnt(9).

__KERNEL_RCSID()

branches: 1.15.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use aprint_normal for cfprint routines.

Use CFATTACH_DECL().

Declare all cfattach structures const.

* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.10.2;
Implement pci_decompose_tag().

branches: 1.9.6;
Disable PCI expansion ROM for normal operation.
It fixes memory mapped I/O problems on some devices.
(from port-arc ML)

branches: 1.8.2;
rename statically allocated software context which is needed for
console initialization, from "struct necpb_config necpb_configuration;"
to "struct necpb_context necpb_main_context".
to resolve naming conflicts with "struct XXX_config *XXX_conf;"
which describes platform-dependent configuration variants.

branches: 1.7.2;
Adapt to pci_intr_map change.

Switch pica to jazzio.
Split shared MD portion between algor and jazzio.

branches: 1.5.2;
Fix a printf format.

remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>

remove/move more mach vm header files:

<vm/pglist.h> -> <uvm/uvm_pglist.h>
<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
<vm/vm_object.h> -> nothing
<vm/vm_pager.h> -> into <uvm/uvm_pager.h>

also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.

branches: 1.2.4;
TGA console initialization for NEC RISCstation 2250,
contributed by Shuichiro URATA <ur@a-r.org>

NEC RISCstation 2250 (RD-94) PCI bus support,
contributed by Shuichiro URATA <ur@a-r.org>

Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

branches: 1.42.18;
PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.41.6;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

use sprintf.

branches: 1.39.2;
split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

branches: 1.38.6;
converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.37.2; 1.37.6;
#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

Merge forward from matt-nb5-mips64.
Adapt to new interrupt/spl framework.
Add LP64 support.

branches: 1.33.2; 1.33.4;
Use fixed pci_intr_handle_t per device number regardless of pin and swiz.

Tested the following multifunction card and devices over ppb(4)
on Express5800/230 (JC94):

---
uhci0 at pci0 dev 4 function 0: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci0: interrupting at int C
usb0 at uhci0: USB revision 1.0
uhci1 at pci0 dev 4 function 1: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci1: interrupting at int C
usb1 at uhci1: USB revision 1.0
ehci0 at pci0 dev 4 function 2: VIA Technologies VT8237 EHCI USB Controller (rev. 0x63)
ehci0: interrupting at int C
ehci0: dropped intr workaround enabled
ehci0: EHCI version 1.0
ehci0: companion controllers, 2 ports each: uhci0 uhci1
usb2 at ehci0: USB revision 2.0
fwohci0 at pci0 dev 4 function 3: VIA Technologies VT6306 IEEE 1394 Host Controller (rev. 0x46)
fwohci0: interrupting at int C
fwohci0: OHCI version 1.0 (ROM=1)
fwohci0: No. of Isochronous channels is 4.
fwohci0: EUI64 00:01:08:00:37:02:79:4f
fwohci0: Phy 1394a available S400, 3 ports.
fwohci0: Link S400, max_rec 1024 bytes.
fwohci0: max_rec 1024 -> 2048
ieee1394if0 at fwohci0: IEEE1394 bus
fwip0 at ieee1394if0: IP over IEEE1394
fwohci0: Initiate bus reset
vge0 at pci0 dev 4 function 4: VIA VT612X Gigabit Ethernet (rev. 0x11)
vge0: interrupting at int C
vge0: Ethernet address: 00:01:08:00:b1:71
ciphy0 at vge0 phy 1: Cicada CS8201 10/100/1000TX PHY, rev. 2
ciphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FDX, auto
:
---
ppb0 at pci0 dev 4 function 0: Digital Equipment DC21154 PCI-PCI Bridge (rev. 0x05)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled
ex0 at pci1 dev 4 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex0: interrupting at int C
ex0: MAC address 00:01:03:ce:74:48
bmtphy0 at ex0 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
ex1 at pci1 dev 5 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex1: interrupting at int C
ex1: MAC address 00:01:03:ce:74:49
bmtphy1 at ex1 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
:

branches: 1.32.6; 1.32.14; 1.32.16; 1.32.18;
Split device_t/softc with misc related changes.

branches: 1.31.2; 1.31.4;
Remove clause 3 and 4 from TNF licenses

branches: 1.30.2; 1.30.4;
Fix spl(9) botch in cpu_intr() on arc:
Don't enable unhandled interrupts before all interrupts are processed,
and also change all interrupt handlers to return processed MIPS_INT_MASK
values, rather than masked values of them.

branches: 1.29.20; 1.29.36; 1.29.40;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.28.10;
Misc minor cleanup for arc interrupt handlers:
- always enable options MIPS3_ENABLE_CLOCK_INTR and just clear the compare
register in cpu_intr() to make CLKF_BASE() works
properly
- prepare only possible number of cpu_inttab
- use macro for interrupt priority number passed to arc_set_intr()
to avoid confusion
- merge arc_hardware_intr() into cpu_intr()
- check independent timer interrupt first in cpu_intr()
- tweak MIPS_SR_INT_IE before calling hardclock timer handlers so that
spllowersoftclock(9) will be invoked properly in hardclock(9)
- reenable interrupt for timer in cpu_intr() rather than each timer handlers

okay'ed by soda.

Note the real fix is to make CLKF_BASE() check all independent
interrupt sources including jazz and isa devices.

branches: 1.27.4;
In !defined(PCI_NETBSD_CONFIGURE) case, check PCI_ID_REG and PCI_CLASS_REG
before CSR fixup.

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

Add support for pci_configure_bus(9) (a.k.a. options PCI_NETBSD_CONFIGURE)
so that PCI devices over ppb(4) work properly on PCI based NEC machines.

Tested on my NEC JC94 (Express5800/230) and 3Com 3C982-TXM,
which has a DEC/Intel 21154 PCI-PCI bridge and two 3C920 Ethernet chips.

Ack interrupts only if they are actually handled.

Misc cosmetics.

Include "ioconf.h" rather than declare struct cfdriver foo_cd in each file.

branches: 1.21.4; 1.21.6; 1.21.8; 1.21.10; 1.21.12;
Explicitly enable interrupts before softintr is handled as noted
in the TODO file. At least this fixes "sn0: receive buffers exhausted"
messages on my NEC-JC94.

XXX: does anyone know what "Dont reenable" comment means, which was
XXX: there since initial import of pica (not arc).

branches: 1.20.8; 1.20.14;
Make all intr_mask value types uint32_t rather than int, u_int,
or unsigned etc.

- remove __P()
- use ANSI function decls
- u_intNN_t -> uintNN_t
- some KNF

branches: 1.18.4;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

Count necpb interrupts with evcnt(9).

__KERNEL_RCSID()

branches: 1.15.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use aprint_normal for cfprint routines.

Use CFATTACH_DECL().

Declare all cfattach structures const.

* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.10.2;
Implement pci_decompose_tag().

branches: 1.9.6;
Disable PCI expansion ROM for normal operation.
It fixes memory mapped I/O problems on some devices.
(from port-arc ML)

branches: 1.8.2;
rename statically allocated software context which is needed for
console initialization, from "struct necpb_config necpb_configuration;"
to "struct necpb_context necpb_main_context".
to resolve naming conflicts with "struct XXX_config *XXX_conf;"
which describes platform-dependent configuration variants.

branches: 1.7.2;
Adapt to pci_intr_map change.

Switch pica to jazzio.
Split shared MD portion between algor and jazzio.

branches: 1.5.2;
Fix a printf format.

remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>

remove/move more mach vm header files:

<vm/pglist.h> -> <uvm/uvm_pglist.h>
<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
<vm/vm_object.h> -> nothing
<vm/vm_pager.h> -> into <uvm/uvm_pager.h>

also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.

branches: 1.2.4;
TGA console initialization for NEC RISCstation 2250,
contributed by Shuichiro URATA <ur@a-r.org>

NEC RISCstation 2250 (RD-94) PCI bus support,
contributed by Shuichiro URATA <ur@a-r.org>

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

branches: 1.42.18;
PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.41.6;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

use sprintf.

branches: 1.39.2;
split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

branches: 1.38.6;
converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.37.2; 1.37.6;
#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

Merge forward from matt-nb5-mips64.
Adapt to new interrupt/spl framework.
Add LP64 support.

branches: 1.33.2; 1.33.4;
Use fixed pci_intr_handle_t per device number regardless of pin and swiz.

Tested the following multifunction card and devices over ppb(4)
on Express5800/230 (JC94):

---
uhci0 at pci0 dev 4 function 0: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci0: interrupting at int C
usb0 at uhci0: USB revision 1.0
uhci1 at pci0 dev 4 function 1: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci1: interrupting at int C
usb1 at uhci1: USB revision 1.0
ehci0 at pci0 dev 4 function 2: VIA Technologies VT8237 EHCI USB Controller (rev. 0x63)
ehci0: interrupting at int C
ehci0: dropped intr workaround enabled
ehci0: EHCI version 1.0
ehci0: companion controllers, 2 ports each: uhci0 uhci1
usb2 at ehci0: USB revision 2.0
fwohci0 at pci0 dev 4 function 3: VIA Technologies VT6306 IEEE 1394 Host Controller (rev. 0x46)
fwohci0: interrupting at int C
fwohci0: OHCI version 1.0 (ROM=1)
fwohci0: No. of Isochronous channels is 4.
fwohci0: EUI64 00:01:08:00:37:02:79:4f
fwohci0: Phy 1394a available S400, 3 ports.
fwohci0: Link S400, max_rec 1024 bytes.
fwohci0: max_rec 1024 -> 2048
ieee1394if0 at fwohci0: IEEE1394 bus
fwip0 at ieee1394if0: IP over IEEE1394
fwohci0: Initiate bus reset
vge0 at pci0 dev 4 function 4: VIA VT612X Gigabit Ethernet (rev. 0x11)
vge0: interrupting at int C
vge0: Ethernet address: 00:01:08:00:b1:71
ciphy0 at vge0 phy 1: Cicada CS8201 10/100/1000TX PHY, rev. 2
ciphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FDX, auto
:
---
ppb0 at pci0 dev 4 function 0: Digital Equipment DC21154 PCI-PCI Bridge (rev. 0x05)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled
ex0 at pci1 dev 4 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex0: interrupting at int C
ex0: MAC address 00:01:03:ce:74:48
bmtphy0 at ex0 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
ex1 at pci1 dev 5 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex1: interrupting at int C
ex1: MAC address 00:01:03:ce:74:49
bmtphy1 at ex1 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
:

branches: 1.32.6; 1.32.14; 1.32.16; 1.32.18;
Split device_t/softc with misc related changes.

branches: 1.31.2; 1.31.4;
Remove clause 3 and 4 from TNF licenses

branches: 1.30.2; 1.30.4;
Fix spl(9) botch in cpu_intr() on arc:
Don't enable unhandled interrupts before all interrupts are processed,
and also change all interrupt handlers to return processed MIPS_INT_MASK
values, rather than masked values of them.

branches: 1.29.20; 1.29.36; 1.29.40;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.28.10;
Misc minor cleanup for arc interrupt handlers:
- always enable options MIPS3_ENABLE_CLOCK_INTR and just clear the compare
register in cpu_intr() to make CLKF_BASE() works
properly
- prepare only possible number of cpu_inttab
- use macro for interrupt priority number passed to arc_set_intr()
to avoid confusion
- merge arc_hardware_intr() into cpu_intr()
- check independent timer interrupt first in cpu_intr()
- tweak MIPS_SR_INT_IE before calling hardclock timer handlers so that
spllowersoftclock(9) will be invoked properly in hardclock(9)
- reenable interrupt for timer in cpu_intr() rather than each timer handlers

okay'ed by soda.

Note the real fix is to make CLKF_BASE() check all independent
interrupt sources including jazz and isa devices.

branches: 1.27.4;
In !defined(PCI_NETBSD_CONFIGURE) case, check PCI_ID_REG and PCI_CLASS_REG
before CSR fixup.

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

Add support for pci_configure_bus(9) (a.k.a. options PCI_NETBSD_CONFIGURE)
so that PCI devices over ppb(4) work properly on PCI based NEC machines.

Tested on my NEC JC94 (Express5800/230) and 3Com 3C982-TXM,
which has a DEC/Intel 21154 PCI-PCI bridge and two 3C920 Ethernet chips.

Ack interrupts only if they are actually handled.

Misc cosmetics.

Include "ioconf.h" rather than declare struct cfdriver foo_cd in each file.

branches: 1.21.4; 1.21.6; 1.21.8; 1.21.10; 1.21.12;
Explicitly enable interrupts before softintr is handled as noted
in the TODO file. At least this fixes "sn0: receive buffers exhausted"
messages on my NEC-JC94.

XXX: does anyone know what "Dont reenable" comment means, which was
XXX: there since initial import of pica (not arc).

branches: 1.20.8; 1.20.14;
Make all intr_mask value types uint32_t rather than int, u_int,
or unsigned etc.

- remove __P()
- use ANSI function decls
- u_intNN_t -> uintNN_t
- some KNF

branches: 1.18.4;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

Count necpb interrupts with evcnt(9).

__KERNEL_RCSID()

branches: 1.15.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use aprint_normal for cfprint routines.

Use CFATTACH_DECL().

Declare all cfattach structures const.

* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.10.2;
Implement pci_decompose_tag().

branches: 1.9.6;
Disable PCI expansion ROM for normal operation.
It fixes memory mapped I/O problems on some devices.
(from port-arc ML)

branches: 1.8.2;
rename statically allocated software context which is needed for
console initialization, from "struct necpb_config necpb_configuration;"
to "struct necpb_context necpb_main_context".
to resolve naming conflicts with "struct XXX_config *XXX_conf;"
which describes platform-dependent configuration variants.

branches: 1.7.2;
Adapt to pci_intr_map change.

Switch pica to jazzio.
Split shared MD portion between algor and jazzio.

branches: 1.5.2;
Fix a printf format.

remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>

remove/move more mach vm header files:

<vm/pglist.h> -> <uvm/uvm_pglist.h>
<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
<vm/vm_object.h> -> nothing
<vm/vm_pager.h> -> into <uvm/uvm_pager.h>

also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.

branches: 1.2.4;
TGA console initialization for NEC RISCstation 2250,
contributed by Shuichiro URATA <ur@a-r.org>

NEC RISCstation 2250 (RD-94) PCI bus support,
contributed by Shuichiro URATA <ur@a-r.org>

in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.41.6;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

use sprintf.

branches: 1.39.2;
split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

branches: 1.38.6;
converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.37.2; 1.37.6;
#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

Merge forward from matt-nb5-mips64.
Adapt to new interrupt/spl framework.
Add LP64 support.

branches: 1.33.2; 1.33.4;
Use fixed pci_intr_handle_t per device number regardless of pin and swiz.

Tested the following multifunction card and devices over ppb(4)
on Express5800/230 (JC94):

---
uhci0 at pci0 dev 4 function 0: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci0: interrupting at int C
usb0 at uhci0: USB revision 1.0
uhci1 at pci0 dev 4 function 1: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci1: interrupting at int C
usb1 at uhci1: USB revision 1.0
ehci0 at pci0 dev 4 function 2: VIA Technologies VT8237 EHCI USB Controller (rev. 0x63)
ehci0: interrupting at int C
ehci0: dropped intr workaround enabled
ehci0: EHCI version 1.0
ehci0: companion controllers, 2 ports each: uhci0 uhci1
usb2 at ehci0: USB revision 2.0
fwohci0 at pci0 dev 4 function 3: VIA Technologies VT6306 IEEE 1394 Host Controller (rev. 0x46)
fwohci0: interrupting at int C
fwohci0: OHCI version 1.0 (ROM=1)
fwohci0: No. of Isochronous channels is 4.
fwohci0: EUI64 00:01:08:00:37:02:79:4f
fwohci0: Phy 1394a available S400, 3 ports.
fwohci0: Link S400, max_rec 1024 bytes.
fwohci0: max_rec 1024 -> 2048
ieee1394if0 at fwohci0: IEEE1394 bus
fwip0 at ieee1394if0: IP over IEEE1394
fwohci0: Initiate bus reset
vge0 at pci0 dev 4 function 4: VIA VT612X Gigabit Ethernet (rev. 0x11)
vge0: interrupting at int C
vge0: Ethernet address: 00:01:08:00:b1:71
ciphy0 at vge0 phy 1: Cicada CS8201 10/100/1000TX PHY, rev. 2
ciphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FDX, auto
:
---
ppb0 at pci0 dev 4 function 0: Digital Equipment DC21154 PCI-PCI Bridge (rev. 0x05)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled
ex0 at pci1 dev 4 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex0: interrupting at int C
ex0: MAC address 00:01:03:ce:74:48
bmtphy0 at ex0 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
ex1 at pci1 dev 5 function 0: 3Com 3c980C-TXM 10/100 Ethernet (rev. 0x78)
ex1: interrupting at int C
ex1: MAC address 00:01:03:ce:74:49
bmtphy1 at ex1 phy 24: Broadcom 3c905C internal PHY, rev. 7
bmtphy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
:

branches: 1.32.6; 1.32.14; 1.32.16; 1.32.18;
Split device_t/softc with misc related changes.

branches: 1.31.2; 1.31.4;
Remove clause 3 and 4 from TNF licenses

branches: 1.30.2; 1.30.4;
Fix spl(9) botch in cpu_intr() on arc:
Don't enable unhandled interrupts before all interrupts are processed,
and also change all interrupt handlers to return processed MIPS_INT_MASK
values, rather than masked values of them.

branches: 1.29.20; 1.29.36; 1.29.40;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.28.10;
Misc minor cleanup for arc interrupt handlers:
- always enable options MIPS3_ENABLE_CLOCK_INTR and just clear the compare
register in cpu_intr() to make CLKF_BASE() works
properly
- prepare only possible number of cpu_inttab
- use macro for interrupt priority number passed to arc_set_intr()
to avoid confusion
- merge arc_hardware_intr() into cpu_intr()
- check independent timer interrupt first in cpu_intr()
- tweak MIPS_SR_INT_IE before calling hardclock timer handlers so that
spllowersoftclock(9) will be invoked properly in hardclock(9)
- reenable interrupt for timer in cpu_intr() rather than each timer handlers

okay'ed by soda.

Note the real fix is to make CLKF_BASE() check all independent
interrupt sources including jazz and isa devices.

branches: 1.27.4;
In !defined(PCI_NETBSD_CONFIGURE) case, check PCI_ID_REG and PCI_CLASS_REG
before CSR fixup.

Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.

Add support for pci_configure_bus(9) (a.k.a. options PCI_NETBSD_CONFIGURE)
so that PCI devices over ppb(4) work properly on PCI based NEC machines.

Tested on my NEC JC94 (Express5800/230) and 3Com 3C982-TXM,
which has a DEC/Intel 21154 PCI-PCI bridge and two 3C920 Ethernet chips.

Ack interrupts only if they are actually handled.

Misc cosmetics.

Include "ioconf.h" rather than declare struct cfdriver foo_cd in each file.

branches: 1.21.4; 1.21.6; 1.21.8; 1.21.10; 1.21.12;
Explicitly enable interrupts before softintr is handled as noted
in the TODO file. At least this fixes "sn0: receive buffers exhausted"
messages on my NEC-JC94.

XXX: does anyone know what "Dont reenable" comment means, which was
XXX: there since initial import of pica (not arc).

branches: 1.20.8; 1.20.14;
Make all intr_mask value types uint32_t rather than int, u_int,
or unsigned etc.

- remove __P()
- use ANSI function decls
- u_intNN_t -> uintNN_t
- some KNF

branches: 1.18.4;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

Count necpb interrupts with evcnt(9).

__KERNEL_RCSID()

branches: 1.15.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use aprint_normal for cfprint routines.

Use CFATTACH_DECL().

Declare all cfattach structures const.

* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.10.2;
Implement pci_decompose_tag().

branches: 1.9.6;
Disable PCI expansion ROM for normal operation.
It fixes memory mapped I/O problems on some devices.
(from port-arc ML)