necpb.c revision 1.47
1/* $NetBSD: necpb.c,v 1.47 2021/04/24 23:36:25 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63#include <sys/cdefs.h> 64__KERNEL_RCSID(0, "$NetBSD: necpb.c,v 1.47 2021/04/24 23:36:25 thorpej Exp $"); 65 66#include "opt_pci.h" 67 68#include <sys/types.h> 69#include <sys/param.h> 70#include <sys/time.h> 71#include <sys/systm.h> 72#include <sys/errno.h> 73#include <sys/device.h> 74#include <sys/kmem.h> 75#include <sys/extent.h> 76 77#include <uvm/uvm_extern.h> 78 79#define _ARC_BUS_DMA_PRIVATE 80#include <sys/bus.h> 81 82#include <machine/pio.h> 83 84#include <machine/autoconf.h> 85#include <machine/cpu.h> 86#include <machine/platform.h> 87 88#include <mips/cache.h> 89 90#include <dev/pci/pcivar.h> 91#include <dev/pci/pcireg.h> 92#include <dev/pci/pcidevs.h> 93#ifdef PCI_NETBSD_CONFIGURE 94#include <dev/pci/pciconf.h> 95#endif 96 97#include <arc/jazz/rd94.h> 98#include <arc/pci/necpbvar.h> 99 100#include "ioconf.h" 101 102static int necpbmatch(device_t, cfdata_t, void *); 103static void necpbattach(device_t, device_t, void *); 104 105static void necpb_attach_hook(device_t, device_t, 106 struct pcibus_attach_args *); 107static int necpb_bus_maxdevs(pci_chipset_tag_t, int); 108static pcitag_t necpb_make_tag(pci_chipset_tag_t, int, int, int); 109static void necpb_decompose_tag(pci_chipset_tag_t, pcitag_t, int *, 110 int *, int *); 111static pcireg_t necpb_conf_read(pci_chipset_tag_t, pcitag_t, int); 112static void necpb_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 113static int necpb_intr_map(const struct pci_attach_args *, 114 pci_intr_handle_t *); 115static const char *necpb_intr_string(pci_chipset_tag_t, pci_intr_handle_t, 116 char *, size_t); 117static void *necpb_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 118 int, int (*func)(void *), void *); 119static void necpb_intr_disestablish(pci_chipset_tag_t, void *); 120#ifdef PCI_NETBSD_CONFIGURE 121static void necpb_conf_interrupt(pci_chipset_tag_t, int, int, int, int, 122 int *); 123static int necpb_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t); 124#endif 125 126static uint32_t necpb_intr(uint32_t, struct clockframe *); 127 128 129CFATTACH_DECL_NEW(necpb, sizeof(struct necpb_softc), 130 necpbmatch, necpbattach, NULL, NULL); 131 132static struct necpb_intrhand *necpb_inttbl[4]; 133 134/* There can be only one. */ 135int necpbfound; 136struct necpb_context necpb_main_context; 137static long necpb_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(10) / sizeof(long)]; 138static long necpb_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(10) / sizeof(long)]; 139 140#define PCI_IO_START 0x00100000 141#define PCI_IO_END 0x01ffffff 142#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1) 143 144#define PCI_MEM_START 0x08000000 145#define PCI_MEM_END 0x3fffffff 146#define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1) 147 148static int 149necpbmatch(device_t parent, cfdata_t cf, void *aux) 150{ 151 struct confargs *ca = aux; 152 153 if (strcmp(ca->ca_name, necpb_cd.cd_name) != 0) 154 return 0; 155 156 if (necpbfound) 157 return 0; 158 159 return 1; 160} 161 162/* 163 * Set up the chipset's function pointers. 164 */ 165void 166necpb_init(struct necpb_context *ncp) 167{ 168 pci_chipset_tag_t pc; 169#ifndef PCI_NETBSD_CONFIGURE 170 pcitag_t tag; 171 pcireg_t id, class, csr; 172 u_int dev; 173#endif 174 175 if (ncp->nc_initialized) 176 return; 177 178 arc_large_bus_space_init(&ncp->nc_memt, "necpcimem", 179 RD94_P_PCI_MEM, 0, RD94_S_PCI_MEM); 180 arc_bus_space_init_extent(&ncp->nc_memt, (void *)necpb_mem_ex_storage, 181 sizeof(necpb_mem_ex_storage)); 182 183 arc_bus_space_init(&ncp->nc_iot, "necpciio", 184 RD94_P_PCI_IO, RD94_V_PCI_IO, 0, RD94_S_PCI_IO); 185 arc_bus_space_init_extent(&ncp->nc_iot, (void *)necpb_io_ex_storage, 186 sizeof(necpb_io_ex_storage)); 187 188 jazz_bus_dma_tag_init(&ncp->nc_dmat); 189 190 pc = &ncp->nc_pc; 191 pc->pc_attach_hook = necpb_attach_hook; 192 pc->pc_bus_maxdevs = necpb_bus_maxdevs; 193 pc->pc_make_tag = necpb_make_tag; 194 pc->pc_decompose_tag = necpb_decompose_tag; 195 pc->pc_conf_read = necpb_conf_read; 196 pc->pc_conf_write = necpb_conf_write; 197 pc->pc_intr_map = necpb_intr_map; 198 pc->pc_intr_string = necpb_intr_string; 199 pc->pc_intr_establish = necpb_intr_establish; 200 pc->pc_intr_disestablish = necpb_intr_disestablish; 201#ifdef PCI_NETBSD_CONFIGURE 202 pc->pc_conf_interrupt = necpb_conf_interrupt; 203 pc->pc_conf_hook = necpb_conf_hook; 204#endif 205 206#ifndef PCI_NETBSD_CONFIGURE 207 /* 208 * XXX: 209 * NEC's firmware does not configure PCI devices completely. 210 * We need to disable expansion ROM and enable mem/io/busmaster 211 * bits here. 212 */ 213 for (dev = 3; dev <= 5; dev++) { 214 tag = necpb_make_tag(pc, 0, dev, 0); 215 id = necpb_conf_read(pc, tag, PCI_ID_REG); 216 217 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 218 continue; 219 220 class = necpb_conf_read(pc, tag, PCI_CLASS_REG); 221 csr = necpb_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 222 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 223 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 224 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 225 necpb_conf_write(pc, tag, PCI_MAPREG_ROM, 0); 226 } 227 csr |= PCI_COMMAND_MASTER_ENABLE; 228 necpb_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 229 } 230#endif 231 232 ncp->nc_initialized = 1; 233} 234 235static void 236necpbattach(device_t parent, device_t self, void *aux) 237{ 238 struct necpb_softc *sc = device_private(self); 239 struct pcibus_attach_args pba; 240 pci_chipset_tag_t pc; 241 int i; 242 243 sc->sc_dev = self; 244 245 necpbfound = 1; 246 247 aprint_normal("\n"); 248 249 sc->sc_ncp = &necpb_main_context; 250 necpb_init(sc->sc_ncp); 251 252 pc = &sc->sc_ncp->nc_pc; 253#ifdef PCI_NETBSD_CONFIGURE 254 struct pciconf_resources *pcires = pciconf_resource_init(); 255 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 256 PCI_IO_START, PCI_IO_SIZE); 257 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 258 PCI_MEM_START, PCI_MEM_SIZE); 259 pci_configure_bus(pc, pcires, 0, mips_cache_info.mci_dcache_align); 260 pciconf_resource_fini(pcires); 261#endif 262 263 out32(RD94_SYS_PCI_INTMASK, 0xf); 264 265 for (i = 0; i < 4; i++) 266 necpb_inttbl[i] = NULL; 267 268 (*platform->set_intr)(MIPS_INT_MASK_2, necpb_intr, ARC_INTPRI_PCIISA); 269 270 pba.pba_iot = &sc->sc_ncp->nc_iot; 271 pba.pba_memt = &sc->sc_ncp->nc_memt; 272 pba.pba_dmat = &sc->sc_ncp->nc_dmat; 273 pba.pba_dmat64 = NULL; 274 pba.pba_pc = pc; 275 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 276 pba.pba_bus = 0; 277 pba.pba_bridgetag = NULL; 278 279 config_found(self, &pba, pcibusprint, CFARG_EOL); 280} 281 282static void 283necpb_attach_hook(device_t parent, device_t self, 284 struct pcibus_attach_args *pba) 285{ 286} 287 288static int 289necpb_bus_maxdevs(pci_chipset_tag_t pc, int busno) 290{ 291 292 return 32; 293} 294 295static pcitag_t 296necpb_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 297{ 298 pcitag_t tag; 299 300 if (bus >= 256 || device >= 32 || function >= 8) 301 panic("%s: bad request", __func__); 302 303 tag = 0x80000000 | (bus << 16) | (device << 11) | (function << 8); 304 return tag; 305} 306 307static void 308necpb_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, 309 int *fp) 310{ 311 312 if (bp != NULL) 313 *bp = (tag >> 16) & 0xff; 314 if (dp != NULL) 315 *dp = (tag >> 11) & 0x1f; 316 if (fp != NULL) 317 *fp = (tag >> 8) & 0x07; 318} 319 320static pcireg_t 321necpb_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 322{ 323 pcireg_t data; 324 int s; 325 326 if ((unsigned int)reg >= PCI_CONF_SIZE) 327 return (pcireg_t) -1; 328 329 s = splhigh(); 330 out32(RD94_SYS_PCI_CONFADDR, tag | reg); 331 data = in32(RD94_SYS_PCI_CONFDATA); 332 out32(RD94_SYS_PCI_CONFADDR, 0); 333 splx(s); 334 335 return data; 336} 337 338static void 339necpb_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 340{ 341 int s; 342 343 if ((unsigned int)reg >= PCI_CONF_SIZE) 344 return; 345 346 s = splhigh(); 347 out32(RD94_SYS_PCI_CONFADDR, tag | reg); 348 out32(RD94_SYS_PCI_CONFDATA, data); 349 out32(RD94_SYS_PCI_CONFADDR, 0); 350 splx(s); 351} 352 353static int 354necpb_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 355{ 356 pci_chipset_tag_t pc = pa->pa_pc; 357 pcitag_t intrtag = pa->pa_intrtag; 358 int pin = pa->pa_intrpin; 359 int bus, dev; 360 361 if (pin == 0) { 362 /* No IRQ used. */ 363 *ihp = -1; 364 return 1; 365 } 366 367 if (pin > 4) { 368 printf("necpb_intr_map: bad interrupt pin %d\n", pin); 369 *ihp = -1; 370 return 1; 371 } 372 373 necpb_decompose_tag(pc, intrtag, &bus, &dev, NULL); 374 if (bus != 0) { 375 printf("necpb_intr_map: unknown bus %d\n", bus); 376 *ihp = -1; 377 return 1; 378 } 379 380 switch (dev) { 381 case 3: 382 *ihp = 3; 383 break; 384 case 4: 385 *ihp = 2; 386 break; 387 case 5: 388 *ihp = 1; 389 break; 390 default: 391 *ihp = -1; 392 return 1; 393 } 394 395 return 0; 396} 397 398static const char * 399necpb_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 400 size_t len) 401{ 402 if (ih >= 4) 403 panic("%s: bogus handle %ld", __func__, ih); 404 snprintf(buf, len, "int %c", 'A' + (int)ih); 405 return buf; 406} 407 408static void * 409necpb_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 410 int (*func)(void *), void *arg) 411{ 412 struct necpb_intrhand *n, *p; 413 uint32_t mask; 414 char buf[PCI_INTRSTR_LEN]; 415 416 if (ih >= 4) 417 panic("%s: bogus handle", __func__); 418 419 n = kmem_alloc(sizeof(*n), KM_SLEEP); 420 n->ih_func = func; 421 n->ih_arg = arg; 422 n->ih_next = NULL; 423 n->ih_intn = ih; 424 strlcpy(n->ih_evname, necpb_intr_string(pc, ih, buf, sizeof(buf)), 425 sizeof(n->ih_evname)); 426 evcnt_attach_dynamic(&n->ih_evcnt, EVCNT_TYPE_INTR, NULL, "necpb", 427 n->ih_evname); 428 429 if (necpb_inttbl[ih] == NULL) { 430 necpb_inttbl[ih] = n; 431 mask = in32(RD94_SYS_PCI_INTMASK); 432 mask |= 1 << ih; 433 out32(RD94_SYS_PCI_INTMASK, mask); 434 } else { 435 p = necpb_inttbl[ih]; 436 while (p->ih_next != NULL) 437 p = p->ih_next; 438 p->ih_next = n; 439 } 440 441 return n; 442} 443 444static void 445necpb_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 446{ 447 struct necpb_intrhand *n, *p, *q; 448 uint32_t mask; 449 450 n = cookie; 451 452 q = NULL; 453 p = necpb_inttbl[n->ih_intn]; 454 while (p != n) { 455 if (p == NULL) 456 panic("%s: broken intr table", __func__); 457 q = p; 458 p = p->ih_next; 459 } 460 461 if (q == NULL) { 462 necpb_inttbl[n->ih_intn] = n->ih_next; 463 if (n->ih_next == NULL) { 464 mask = in32(RD94_SYS_PCI_INTMASK); 465 mask &= ~(1 << n->ih_intn); 466 out32(RD94_SYS_PCI_INTMASK, mask); 467 } 468 } else 469 q->ih_next = n->ih_next; 470 471 evcnt_detach(&n->ih_evcnt); 472 473 kmem_free(n, sizeof(*n)); 474} 475 476/* 477 * Handle PCI/EISA interrupt. 478 */ 479static uint32_t 480necpb_intr(uint32_t mask, struct clockframe *cf) 481{ 482 uint32_t vector, stat; 483 struct necpb_intrhand *p; 484 int i, handled; 485 486 handled = 0; 487 vector = in32(RD94_SYS_INTSTAT2) & 0xffff; 488 489 if (vector == 0x4000) { 490 stat = in32(RD94_SYS_PCI_INTSTAT); 491 stat &= in32(RD94_SYS_PCI_INTMASK); 492 for (i = 0; i < 4; i++) { 493 if (stat & (1 << i)) { 494#if 0 495 printf("pint %d\n", i); 496#endif 497 p = necpb_inttbl[i]; 498 while (p != NULL) { 499 if ((*p->ih_func)(p->ih_arg)) { 500 p->ih_evcnt.ev_count++; 501 handled |= 1; 502 } 503 p = p->ih_next; 504 } 505 } 506 } 507 } else if (vector == 0x8000) { 508 printf("eisa_nmi\n"); 509 } else { 510 printf("eint %d\n", vector & 0xff); 511#if 0 512 if (eisa_intr(vector & 0xff)) { 513 handled |= 1; 514 } 515#endif 516 } 517 518 return handled ? MIPS_INT_MASK_2 : 0; 519} 520 521#ifdef PCI_NETBSD_CONFIGURE 522static void 523necpb_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int func, 524 int swiz, int *iline) 525{ 526 527 return; 528} 529 530static int 531necpb_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, 532 pcireg_t id) 533{ 534 535 /* ignore bogus IDs */ 536 if (id == 0) 537 return 0; 538 539 /* don't configure bridges */ 540 if (bus == 0 && (dev == 1 || dev == 2)) 541 return 0; 542 543 return PCI_CONF_DEFAULT; 544} 545#endif 546