| #
267654 |
|
19-Jun-2014 |
gjb |
Copy stable/9 to releng/9.3 as part of the 9.3-RELEASE cycle.
Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation |
| #
250038 |
|
29-Apr-2013 |
hiren |
MFC: r249069
Trailing whitespace cleanup along with 80 column enforcemnt.
MFC: r249428
Cosmetic change: Fix a comment reference for Ivy Bridge *Xeon*
MFC: r249460
Improve/correct a comment. We now support a lot more cpu types.
Approved by: sbruno (mentor)
|
| #
249655 |
|
19-Apr-2013 |
hiren |
MFC: r248842
Update hwpmc to support Haswell class processors.
0x3C: /* Per Intel document 325462-045US 01/2013. */
Add manpage to document all the goodness that is available in this
processor model.
Approved by: sbruno (mentor)
|
| #
237444 |
|
22-Jun-2012 |
gnn |
MFC 230063
Clean up a switch statement for uncore events on Westmere processors.
Submitted by: Davide Italiano
Reviewed by: gnn
|
| #
234046 |
|
08-Apr-2012 |
davide |
MFC: r232366
- Add support for the Intel Sandy Bridge microarchitecture (both core and
uncore counting events)
- New manpages with event lists.
- Add MSRs for the Intel Sandy Bridge microarchitecture
Approved by: gnn (mentor)
|
| #
234041 |
|
08-Apr-2012 |
davide |
MFC: r229469
Add missing MSR programming for some events.
Submitted by: me
Approved by: gnn (mentor)
|
| #
225736 |
|
22-Sep-2011 |
kensmith |
Copy head to stable/9 as part of 9.0-RELEASE release cycle.
Approved by: re (implicit)
|
| #
206089 |
|
02-Apr-2010 |
fabient |
- Support for uncore counting events: one fixed PMC with the uncore
domain clock, 8 programmable PMC.
- Westmere based CPU (Xeon 5600, Corei7 980X) support.
- New man pages with events list for core and uncore.
- Updated Corei7 events with Intel 253669-033US December 2009 doc.
There is some removed events in the documentation, they have been
kept in the code but documented in the man page as obsolete.
- Offcore response events can be setup with rsp token.
Sponsored by: NETASQ
|