1/*- 2 * Copyright (c) 2010 Fabien Thomas 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Intel Uncore PMCs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD$"); 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/pmc.h> 37#include <sys/pmckern.h> 38#include <sys/systm.h> 39 40#include <machine/intr_machdep.h> 41#include <machine/apicvar.h> 42#include <machine/cpu.h> 43#include <machine/cpufunc.h> 44#include <machine/specialreg.h> 45 46#define UCF_PMC_CAPS \ 47 (PMC_CAP_READ | PMC_CAP_WRITE) 48 49#define UCP_PMC_CAPS \ 50 (PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 51 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 52 53#define SELECTSEL(x) \ 54 (((x) == PMC_CPU_INTEL_SANDYBRIDGE || (x) == PMC_CPU_INTEL_HASWELL) ? \ 55 UCP_CB0_EVSEL0 : UCP_EVSEL0) 56 57#define SELECTOFF(x) \ 58 (((x) == PMC_CPU_INTEL_SANDYBRIDGE || (x) == PMC_CPU_INTEL_HASWELL) ? \ 59 UCF_OFFSET_SB : UCF_OFFSET) 60 61static enum pmc_cputype uncore_cputype; 62 63struct uncore_cpu { 64 volatile uint32_t pc_resync; 65 volatile uint32_t pc_ucfctrl; /* Fixed function control. */ 66 volatile uint64_t pc_globalctrl; /* Global control register. */ 67 struct pmc_hw pc_uncorepmcs[]; 68}; 69 70static struct uncore_cpu **uncore_pcpu; 71 72static uint64_t uncore_pmcmask; 73 74static int uncore_ucf_ri; /* relative index of fixed counters */ 75static int uncore_ucf_width; 76static int uncore_ucf_npmc; 77 78static int uncore_ucp_width; 79static int uncore_ucp_npmc; 80 81static int 82uncore_pcpu_noop(struct pmc_mdep *md, int cpu) 83{ 84 (void) md; 85 (void) cpu; 86 return (0); 87} 88 89static int 90uncore_pcpu_init(struct pmc_mdep *md, int cpu) 91{ 92 struct pmc_cpu *pc; 93 struct uncore_cpu *cc; 94 struct pmc_hw *phw; 95 int uncore_ri, n, npmc; 96 97 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 98 ("[ucf,%d] insane cpu number %d", __LINE__, cpu)); 99 100 PMCDBG(MDP,INI,1,"uncore-init cpu=%d", cpu); 101 102 uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri; 103 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num; 104 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num; 105 106 cc = malloc(sizeof(struct uncore_cpu) + npmc * sizeof(struct pmc_hw), 107 M_PMC, M_WAITOK | M_ZERO); 108 109 uncore_pcpu[cpu] = cc; 110 pc = pmc_pcpu[cpu]; 111 112 KASSERT(pc != NULL && cc != NULL, 113 ("[uncore,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 114 115 for (n = 0, phw = cc->pc_uncorepmcs; n < npmc; n++, phw++) { 116 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 117 PMC_PHW_CPU_TO_STATE(cpu) | 118 PMC_PHW_INDEX_TO_STATE(n + uncore_ri); 119 phw->phw_pmc = NULL; 120 pc->pc_hwpmcs[n + uncore_ri] = phw; 121 } 122 123 return (0); 124} 125 126static int 127uncore_pcpu_fini(struct pmc_mdep *md, int cpu) 128{ 129 int uncore_ri, n, npmc; 130 struct pmc_cpu *pc; 131 struct uncore_cpu *cc; 132 133 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 134 ("[uncore,%d] insane cpu number (%d)", __LINE__, cpu)); 135 136 PMCDBG(MDP,INI,1,"uncore-pcpu-fini cpu=%d", cpu); 137 138 if ((cc = uncore_pcpu[cpu]) == NULL) 139 return (0); 140 141 uncore_pcpu[cpu] = NULL; 142 143 pc = pmc_pcpu[cpu]; 144 145 KASSERT(pc != NULL, ("[uncore,%d] NULL per-cpu %d state", __LINE__, 146 cpu)); 147 148 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num; 149 uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri; 150 151 for (n = 0; n < npmc; n++) 152 wrmsr(SELECTSEL(uncore_cputype) + n, 0); 153 154 wrmsr(UCF_CTRL, 0); 155 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num; 156 157 for (n = 0; n < npmc; n++) 158 pc->pc_hwpmcs[n + uncore_ri] = NULL; 159 160 free(cc, M_PMC); 161 162 return (0); 163} 164 165/* 166 * Fixed function counters. 167 */ 168 169static pmc_value_t 170ucf_perfctr_value_to_reload_count(pmc_value_t v) 171{ 172 v &= (1ULL << uncore_ucf_width) - 1; 173 return (1ULL << uncore_ucf_width) - v; 174} 175 176static pmc_value_t 177ucf_reload_count_to_perfctr_value(pmc_value_t rlc) 178{ 179 return (1ULL << uncore_ucf_width) - rlc; 180} 181 182static int 183ucf_allocate_pmc(int cpu, int ri, struct pmc *pm, 184 const struct pmc_op_pmcallocate *a) 185{ 186 enum pmc_event ev; 187 uint32_t caps, flags; 188 189 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 190 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 191 192 PMCDBG(MDP,ALL,1, "ucf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 193 194 if (ri < 0 || ri > uncore_ucf_npmc) 195 return (EINVAL); 196 197 caps = a->pm_caps; 198 199 if (a->pm_class != PMC_CLASS_UCF || 200 (caps & UCF_PMC_CAPS) != caps) 201 return (EINVAL); 202 203 ev = pm->pm_event; 204 if (ev < PMC_EV_UCF_FIRST || ev > PMC_EV_UCF_LAST) 205 return (EINVAL); 206 207 flags = UCF_EN; 208 209 pm->pm_md.pm_ucf.pm_ucf_ctrl = (flags << (ri * 4)); 210 211 PMCDBG(MDP,ALL,2, "ucf-allocate config=0x%jx", 212 (uintmax_t) pm->pm_md.pm_ucf.pm_ucf_ctrl); 213 214 return (0); 215} 216 217static int 218ucf_config_pmc(int cpu, int ri, struct pmc *pm) 219{ 220 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 221 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 222 223 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 224 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 225 226 PMCDBG(MDP,CFG,1, "ucf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 227 228 KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__, 229 cpu)); 230 231 uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc = pm; 232 233 return (0); 234} 235 236static int 237ucf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 238{ 239 int error; 240 struct pmc_hw *phw; 241 char ucf_name[PMC_NAME_MAX]; 242 243 phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri]; 244 245 (void) snprintf(ucf_name, sizeof(ucf_name), "UCF-%d", ri); 246 if ((error = copystr(ucf_name, pi->pm_name, PMC_NAME_MAX, 247 NULL)) != 0) 248 return (error); 249 250 pi->pm_class = PMC_CLASS_UCF; 251 252 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 253 pi->pm_enabled = TRUE; 254 *ppmc = phw->phw_pmc; 255 } else { 256 pi->pm_enabled = FALSE; 257 *ppmc = NULL; 258 } 259 260 return (0); 261} 262 263static int 264ucf_get_config(int cpu, int ri, struct pmc **ppm) 265{ 266 *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 267 268 return (0); 269} 270 271static int 272ucf_read_pmc(int cpu, int ri, pmc_value_t *v) 273{ 274 struct pmc *pm; 275 pmc_value_t tmp; 276 277 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 278 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 279 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 280 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 281 282 pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 283 284 KASSERT(pm, 285 ("[uncore,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 286 ri, ri + uncore_ucf_ri)); 287 288 tmp = rdmsr(UCF_CTR0 + ri); 289 290 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 291 *v = ucf_perfctr_value_to_reload_count(tmp); 292 else 293 *v = tmp; 294 295 PMCDBG(MDP,REA,1, "ucf-read cpu=%d ri=%d -> v=%jx", cpu, ri, *v); 296 297 return (0); 298} 299 300static int 301ucf_release_pmc(int cpu, int ri, struct pmc *pmc) 302{ 303 PMCDBG(MDP,REL,1, "ucf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 304 305 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 306 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 307 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 308 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 309 310 KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc == NULL, 311 ("[uncore,%d] PHW pmc non-NULL", __LINE__)); 312 313 return (0); 314} 315 316static int 317ucf_start_pmc(int cpu, int ri) 318{ 319 struct pmc *pm; 320 struct uncore_cpu *ucfc; 321 322 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 323 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 324 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 325 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 326 327 PMCDBG(MDP,STA,1,"ucf-start cpu=%d ri=%d", cpu, ri); 328 329 ucfc = uncore_pcpu[cpu]; 330 pm = ucfc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 331 332 ucfc->pc_ucfctrl |= pm->pm_md.pm_ucf.pm_ucf_ctrl; 333 334 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl); 335 336 do { 337 ucfc->pc_resync = 0; 338 ucfc->pc_globalctrl |= (1ULL << (ri + SELECTOFF(uncore_cputype))); 339 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl); 340 } while (ucfc->pc_resync != 0); 341 342 PMCDBG(MDP,STA,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)", 343 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL), 344 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL)); 345 346 return (0); 347} 348 349static int 350ucf_stop_pmc(int cpu, int ri) 351{ 352 uint32_t fc; 353 struct uncore_cpu *ucfc; 354 355 PMCDBG(MDP,STO,1,"ucf-stop cpu=%d ri=%d", cpu, ri); 356 357 ucfc = uncore_pcpu[cpu]; 358 359 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 360 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 361 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 362 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 363 364 fc = (UCF_MASK << (ri * 4)); 365 366 ucfc->pc_ucfctrl &= ~fc; 367 368 PMCDBG(MDP,STO,1,"ucf-stop ucfctrl=%x", ucfc->pc_ucfctrl); 369 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl); 370 371 do { 372 ucfc->pc_resync = 0; 373 ucfc->pc_globalctrl &= ~(1ULL << (ri + SELECTOFF(uncore_cputype))); 374 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl); 375 } while (ucfc->pc_resync != 0); 376 377 PMCDBG(MDP,STO,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)", 378 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL), 379 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL)); 380 381 return (0); 382} 383 384static int 385ucf_write_pmc(int cpu, int ri, pmc_value_t v) 386{ 387 struct uncore_cpu *cc; 388 struct pmc *pm; 389 390 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 391 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 392 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 393 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 394 395 cc = uncore_pcpu[cpu]; 396 pm = cc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 397 398 KASSERT(pm, 399 ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 400 401 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 402 v = ucf_reload_count_to_perfctr_value(v); 403 404 wrmsr(UCF_CTRL, 0); /* Turn off fixed counters */ 405 wrmsr(UCF_CTR0 + ri, v); 406 wrmsr(UCF_CTRL, cc->pc_ucfctrl); 407 408 PMCDBG(MDP,WRI,1, "ucf-write cpu=%d ri=%d v=%jx ucfctrl=%jx ", 409 cpu, ri, v, (uintmax_t) rdmsr(UCF_CTRL)); 410 411 return (0); 412} 413 414 415static void 416ucf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 417{ 418 struct pmc_classdep *pcd; 419 420 KASSERT(md != NULL, ("[ucf,%d] md is NULL", __LINE__)); 421 422 PMCDBG(MDP,INI,1, "%s", "ucf-initialize"); 423 424 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF]; 425 426 pcd->pcd_caps = UCF_PMC_CAPS; 427 pcd->pcd_class = PMC_CLASS_UCF; 428 pcd->pcd_num = npmc; 429 pcd->pcd_ri = md->pmd_npmc; 430 pcd->pcd_width = pmcwidth; 431 432 pcd->pcd_allocate_pmc = ucf_allocate_pmc; 433 pcd->pcd_config_pmc = ucf_config_pmc; 434 pcd->pcd_describe = ucf_describe; 435 pcd->pcd_get_config = ucf_get_config; 436 pcd->pcd_get_msr = NULL; 437 pcd->pcd_pcpu_fini = uncore_pcpu_noop; 438 pcd->pcd_pcpu_init = uncore_pcpu_noop; 439 pcd->pcd_read_pmc = ucf_read_pmc; 440 pcd->pcd_release_pmc = ucf_release_pmc; 441 pcd->pcd_start_pmc = ucf_start_pmc; 442 pcd->pcd_stop_pmc = ucf_stop_pmc; 443 pcd->pcd_write_pmc = ucf_write_pmc; 444 445 md->pmd_npmc += npmc; 446} 447 448/* 449 * Intel programmable PMCs. 450 */ 451 452/* 453 * Event descriptor tables. 454 * 455 * For each event id, we track: 456 * 457 * 1. The CPUs that the event is valid for. 458 * 459 * 2. If the event uses a fixed UMASK, the value of the umask field. 460 * If the event doesn't use a fixed UMASK, a mask of legal bits 461 * to check against. 462 */ 463 464struct ucp_event_descr { 465 enum pmc_event ucp_ev; 466 unsigned char ucp_evcode; 467 unsigned char ucp_umask; 468 unsigned char ucp_flags; 469}; 470 471#define UCP_F_I7 (1 << 0) /* CPU: Core i7 */ 472#define UCP_F_WM (1 << 1) /* CPU: Westmere */ 473#define UCP_F_SB (1 << 2) /* CPU: Sandy Bridge */ 474#define UCP_F_HW (1 << 3) /* CPU: Haswell */ 475#define UCP_F_FM (1 << 4) /* Fixed mask */ 476 477#define UCP_F_ALLCPUS \ 478 (UCP_F_I7 | UCP_F_WM) 479 480#define UCP_F_CMASK 0xFF000000 481 482static struct ucp_event_descr ucp_events[] = { 483#undef UCPDESCR 484#define UCPDESCR(N,EV,UM,FLAGS) { \ 485 .ucp_ev = PMC_EV_UCP_EVENT_##N, \ 486 .ucp_evcode = (EV), \ 487 .ucp_umask = (UM), \ 488 .ucp_flags = (FLAGS) \ 489 } 490 491 UCPDESCR(00H_01H, 0x00, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 492 UCPDESCR(00H_02H, 0x00, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 493 UCPDESCR(00H_04H, 0x00, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 494 495 UCPDESCR(01H_01H, 0x01, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 496 UCPDESCR(01H_02H, 0x01, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 497 UCPDESCR(01H_04H, 0x01, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 498 499 UCPDESCR(02H_01H, 0x02, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 500 UCPDESCR(03H_01H, 0x03, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 501 UCPDESCR(03H_02H, 0x03, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 502 UCPDESCR(03H_04H, 0x03, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 503 UCPDESCR(03H_08H, 0x03, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 504 UCPDESCR(03H_10H, 0x03, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 505 UCPDESCR(03H_20H, 0x03, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 506 UCPDESCR(03H_40H, 0x03, 0x40, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 507 508 UCPDESCR(04H_01H, 0x04, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 509 UCPDESCR(04H_02H, 0x04, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 510 UCPDESCR(04H_04H, 0x04, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 511 UCPDESCR(04H_08H, 0x04, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 512 UCPDESCR(04H_10H, 0x04, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 513 514 UCPDESCR(05H_01H, 0x05, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 515 UCPDESCR(05H_02H, 0x05, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 516 UCPDESCR(05H_04H, 0x05, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 517 518 UCPDESCR(06H_01H, 0x06, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 519 UCPDESCR(06H_02H, 0x06, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 520 UCPDESCR(06H_04H, 0x06, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 521 UCPDESCR(06H_08H, 0x06, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 522 UCPDESCR(06H_10H, 0x06, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 523 UCPDESCR(06H_20H, 0x06, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 524 525 UCPDESCR(07H_01H, 0x07, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 526 UCPDESCR(07H_02H, 0x07, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 527 UCPDESCR(07H_04H, 0x07, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 528 UCPDESCR(07H_08H, 0x07, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 529 UCPDESCR(07H_10H, 0x07, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 530 UCPDESCR(07H_20H, 0x07, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 531 UCPDESCR(07H_24H, 0x07, 0x24, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 532 533 UCPDESCR(08H_01H, 0x08, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 534 UCPDESCR(08H_02H, 0x08, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 535 UCPDESCR(08H_04H, 0x08, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 536 UCPDESCR(08H_03H, 0x08, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 537 538 UCPDESCR(09H_01H, 0x09, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 539 UCPDESCR(09H_02H, 0x09, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 540 UCPDESCR(09H_04H, 0x09, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 541 UCPDESCR(09H_03H, 0x09, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 542 543 UCPDESCR(0AH_01H, 0x0A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 544 UCPDESCR(0AH_02H, 0x0A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 545 UCPDESCR(0AH_04H, 0x0A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 546 UCPDESCR(0AH_08H, 0x0A, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 547 UCPDESCR(0AH_0FH, 0x0A, 0x0F, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 548 549 UCPDESCR(0BH_01H, 0x0B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 550 UCPDESCR(0BH_02H, 0x0B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 551 UCPDESCR(0BH_04H, 0x0B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 552 UCPDESCR(0BH_08H, 0x0B, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 553 UCPDESCR(0BH_10H, 0x0B, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 554 UCPDESCR(0BH_1FH, 0x0B, 0x1F, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 555 556 UCPDESCR(0CH_01H, 0x0C, 0x01, UCP_F_FM | UCP_F_WM), 557 UCPDESCR(0CH_02H, 0x0C, 0x02, UCP_F_FM | UCP_F_WM), 558 UCPDESCR(0CH_04H_E, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), 559 UCPDESCR(0CH_04H_F, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), 560 UCPDESCR(0CH_04H_M, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), 561 UCPDESCR(0CH_04H_S, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), 562 UCPDESCR(0CH_08H_E, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), 563 UCPDESCR(0CH_08H_F, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), 564 UCPDESCR(0CH_08H_M, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), 565 UCPDESCR(0CH_08H_S, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), 566 567 UCPDESCR(20H_01H, 0x20, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 568 UCPDESCR(20H_02H, 0x20, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 569 UCPDESCR(20H_04H, 0x20, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 570 UCPDESCR(20H_08H, 0x20, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 571 UCPDESCR(20H_10H, 0x20, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 572 UCPDESCR(20H_20H, 0x20, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 573 574 UCPDESCR(21H_01H, 0x21, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 575 UCPDESCR(21H_02H, 0x21, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 576 UCPDESCR(21H_04H, 0x21, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 577 578 UCPDESCR(22H_01H, 0x22, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM | 579 UCP_F_SB | UCP_F_HW), 580 UCPDESCR(22H_02H, 0x22, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM | 581 UCP_F_SB | UCP_F_HW), 582 UCPDESCR(22H_04H, 0x22, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM | 583 UCP_F_SB | UCP_F_HW), 584 UCPDESCR(22H_08H, 0x22, 0x08, UCP_F_FM | UCP_F_SB | UCP_F_HW), 585 UCPDESCR(22H_10H, 0x22, 0x10, UCP_F_FM | UCP_F_HW), 586 UCPDESCR(22H_20H, 0x22, 0x20, UCP_F_FM | UCP_F_SB | UCP_F_HW), 587 UCPDESCR(22H_40H, 0x22, 0x40, UCP_F_FM | UCP_F_SB | UCP_F_HW), 588 UCPDESCR(22H_80H, 0x22, 0x80, UCP_F_FM | UCP_F_SB | UCP_F_HW), 589 590 UCPDESCR(23H_01H, 0x23, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 591 UCPDESCR(23H_02H, 0x23, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 592 UCPDESCR(23H_04H, 0x23, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 593 594 UCPDESCR(24H_02H, 0x24, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 595 UCPDESCR(24H_04H, 0x24, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 596 597 UCPDESCR(25H_01H, 0x25, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 598 UCPDESCR(25H_02H, 0x25, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 599 UCPDESCR(25H_04H, 0x25, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 600 601 UCPDESCR(26H_01H, 0x26, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 602 603 UCPDESCR(27H_01H, 0x27, 0x01, UCP_F_FM | UCP_F_I7), 604 UCPDESCR(27H_02H, 0x27, 0x02, UCP_F_FM | UCP_F_I7), 605 UCPDESCR(27H_04H, 0x27, 0x04, UCP_F_FM | UCP_F_I7), 606 UCPDESCR(27H_08H, 0x27, 0x08, UCP_F_FM | UCP_F_I7), 607 UCPDESCR(27H_10H, 0x27, 0x10, UCP_F_FM | UCP_F_I7), 608 UCPDESCR(27H_20H, 0x27, 0x20, UCP_F_FM | UCP_F_I7), 609 610 UCPDESCR(28H_01H, 0x28, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 611 UCPDESCR(28H_02H, 0x28, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 612 UCPDESCR(28H_04H, 0x28, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 613 UCPDESCR(28H_08H, 0x28, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 614 UCPDESCR(28H_10H, 0x28, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 615 UCPDESCR(28H_20H, 0x28, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 616 617 UCPDESCR(29H_01H, 0x29, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 618 UCPDESCR(29H_02H, 0x29, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 619 UCPDESCR(29H_04H, 0x29, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 620 UCPDESCR(29H_08H, 0x29, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 621 UCPDESCR(29H_10H, 0x29, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 622 UCPDESCR(29H_20H, 0x29, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 623 624 UCPDESCR(2AH_01H, 0x2A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 625 UCPDESCR(2AH_02H, 0x2A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 626 UCPDESCR(2AH_04H, 0x2A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 627 UCPDESCR(2AH_07H, 0x2A, 0x07, UCP_F_FM | UCP_F_WM), 628 629 UCPDESCR(2BH_01H, 0x2B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 630 UCPDESCR(2BH_02H, 0x2B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 631 UCPDESCR(2BH_04H, 0x2B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 632 UCPDESCR(2BH_07H, 0x2B, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 633 634 UCPDESCR(2CH_01H, 0x2C, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 635 UCPDESCR(2CH_02H, 0x2C, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 636 UCPDESCR(2CH_04H, 0x2C, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 637 UCPDESCR(2CH_07H, 0x2C, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 638 639 UCPDESCR(2DH_01H, 0x2D, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 640 UCPDESCR(2DH_02H, 0x2D, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 641 UCPDESCR(2DH_04H, 0x2D, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 642 UCPDESCR(2DH_07H, 0x2D, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 643 644 UCPDESCR(2EH_01H, 0x2E, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 645 UCPDESCR(2EH_02H, 0x2E, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 646 UCPDESCR(2EH_04H, 0x2E, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 647 UCPDESCR(2EH_07H, 0x2E, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 648 649 UCPDESCR(2FH_01H, 0x2F, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 650 UCPDESCR(2FH_02H, 0x2F, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 651 UCPDESCR(2FH_04H, 0x2F, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 652 UCPDESCR(2FH_07H, 0x2F, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 653 UCPDESCR(2FH_08H, 0x2F, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 654 UCPDESCR(2FH_10H, 0x2F, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 655 UCPDESCR(2FH_20H, 0x2F, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 656 UCPDESCR(2FH_38H, 0x2F, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 657 658 UCPDESCR(30H_01H, 0x30, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 659 UCPDESCR(30H_02H, 0x30, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 660 UCPDESCR(30H_04H, 0x30, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 661 UCPDESCR(30H_07H, 0x30, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 662 663 UCPDESCR(31H_01H, 0x31, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 664 UCPDESCR(31H_02H, 0x31, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 665 UCPDESCR(31H_04H, 0x31, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 666 UCPDESCR(31H_07H, 0x31, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 667 668 UCPDESCR(32H_01H, 0x32, 0x01, UCP_F_FM | UCP_F_WM), 669 UCPDESCR(32H_02H, 0x32, 0x02, UCP_F_FM | UCP_F_WM), 670 UCPDESCR(32H_04H, 0x32, 0x04, UCP_F_FM | UCP_F_WM), 671 UCPDESCR(32H_07H, 0x32, 0x07, UCP_F_FM | UCP_F_WM), 672 673 UCPDESCR(33H_01H, 0x33, 0x01, UCP_F_FM | UCP_F_WM), 674 UCPDESCR(33H_02H, 0x33, 0x02, UCP_F_FM | UCP_F_WM), 675 UCPDESCR(33H_04H, 0x33, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 676 UCPDESCR(33H_07H, 0x33, 0x07, UCP_F_FM | UCP_F_WM), 677 678 UCPDESCR(34H_01H, 0x34, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | 679 UCP_F_HW), 680 UCPDESCR(34H_02H, 0x34, 0x02, UCP_F_FM | UCP_F_WM | UCP_F_SB), 681 UCPDESCR(34H_04H, 0x34, 0x04, UCP_F_FM | UCP_F_WM | UCP_F_SB), 682 UCPDESCR(34H_06H, 0x34, 0x06, UCP_F_FM | UCP_F_HW), 683 UCPDESCR(34H_08H, 0x34, 0x08, UCP_F_FM | UCP_F_WM | UCP_F_SB | 684 UCP_F_HW), 685 UCPDESCR(34H_10H, 0x34, 0x10, UCP_F_FM | UCP_F_WM | UCP_F_SB | 686 UCP_F_HW), 687 UCPDESCR(34H_20H, 0x34, 0x20, UCP_F_FM | UCP_F_WM | UCP_F_SB | 688 UCP_F_HW), 689 UCPDESCR(34H_40H, 0x34, 0x40, UCP_F_FM | UCP_F_SB | UCP_F_HW), 690 UCPDESCR(34H_80H, 0x34, 0x80, UCP_F_FM | UCP_F_SB | UCP_F_HW), 691 692 UCPDESCR(35H_01H, 0x35, 0x01, UCP_F_FM | UCP_F_WM), 693 UCPDESCR(35H_02H, 0x35, 0x02, UCP_F_FM | UCP_F_WM), 694 UCPDESCR(35H_04H, 0x35, 0x04, UCP_F_FM | UCP_F_WM), 695 696 UCPDESCR(40H_01H, 0x40, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 697 UCPDESCR(40H_02H, 0x40, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 698 UCPDESCR(40H_04H, 0x40, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 699 UCPDESCR(40H_08H, 0x40, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 700 UCPDESCR(40H_10H, 0x40, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 701 UCPDESCR(40H_20H, 0x40, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 702 UCPDESCR(40H_07H, 0x40, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 703 UCPDESCR(40H_38H, 0x40, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 704 705 UCPDESCR(41H_01H, 0x41, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 706 UCPDESCR(41H_02H, 0x41, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 707 UCPDESCR(41H_04H, 0x41, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 708 UCPDESCR(41H_08H, 0x41, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 709 UCPDESCR(41H_10H, 0x41, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 710 UCPDESCR(41H_20H, 0x41, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 711 UCPDESCR(41H_07H, 0x41, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 712 UCPDESCR(41H_38H, 0x41, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 713 714 UCPDESCR(42H_01H, 0x42, 0x01, UCP_F_FM | UCP_F_WM), 715 UCPDESCR(42H_02H, 0x42, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 716 UCPDESCR(42H_04H, 0x42, 0x04, UCP_F_FM | UCP_F_WM), 717 UCPDESCR(42H_08H, 0x42, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 718 719 UCPDESCR(43H_01H, 0x43, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 720 UCPDESCR(43H_02H, 0x43, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 721 722 UCPDESCR(60H_01H, 0x60, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 723 UCPDESCR(60H_02H, 0x60, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 724 UCPDESCR(60H_04H, 0x60, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 725 726 UCPDESCR(61H_01H, 0x61, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 727 UCPDESCR(61H_02H, 0x61, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 728 UCPDESCR(61H_04H, 0x61, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 729 730 UCPDESCR(62H_01H, 0x62, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 731 UCPDESCR(62H_02H, 0x62, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 732 UCPDESCR(62H_04H, 0x62, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 733 734 UCPDESCR(63H_01H, 0x63, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 735 UCPDESCR(63H_02H, 0x63, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 736 UCPDESCR(63H_04H, 0x63, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 737 UCPDESCR(63H_08H, 0x63, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 738 UCPDESCR(63H_10H, 0x63, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 739 UCPDESCR(63H_20H, 0x63, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 740 741 UCPDESCR(64H_01H, 0x64, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 742 UCPDESCR(64H_02H, 0x64, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 743 UCPDESCR(64H_04H, 0x64, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 744 UCPDESCR(64H_08H, 0x64, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 745 UCPDESCR(64H_10H, 0x64, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 746 UCPDESCR(64H_20H, 0x64, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 747 748 UCPDESCR(65H_01H, 0x65, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 749 UCPDESCR(65H_02H, 0x65, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 750 UCPDESCR(65H_04H, 0x65, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 751 752 UCPDESCR(66H_01H, 0x66, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 753 UCPDESCR(66H_02H, 0x66, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 754 UCPDESCR(66H_04H, 0x66, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 755 756 UCPDESCR(67H_01H, 0x67, 0x01, UCP_F_FM | UCP_F_WM), 757 758 UCPDESCR(80H_01H, 0x80, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | 759 UCP_F_HW), 760 UCPDESCR(80H_02H, 0x80, 0x02, UCP_F_FM | UCP_F_WM), 761 UCPDESCR(80H_04H, 0x80, 0x04, UCP_F_FM | UCP_F_WM), 762 UCPDESCR(80H_08H, 0x80, 0x08, UCP_F_FM | UCP_F_WM), 763 764 UCPDESCR(81H_01H, 0x81, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | 765 UCP_F_HW), 766 UCPDESCR(81H_02H, 0x81, 0x02, UCP_F_FM | UCP_F_WM), 767 UCPDESCR(81H_04H, 0x81, 0x04, UCP_F_FM | UCP_F_WM), 768 UCPDESCR(81H_08H, 0x81, 0x08, UCP_F_FM | UCP_F_WM), 769 UCPDESCR(81H_20H, 0x81, 0x20, UCP_F_FM | UCP_F_SB | UCP_F_HW), 770 UCPDESCR(81H_80H, 0x81, 0x80, UCP_F_FM | UCP_F_SB | UCP_F_HW), 771 772 UCPDESCR(82H_01H, 0x82, 0x01, UCP_F_FM | UCP_F_WM), 773 774 UCPDESCR(83H_01H, 0x83, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | 775 UCP_F_HW), 776 UCPDESCR(83H_02H, 0x83, 0x02, UCP_F_FM | UCP_F_WM), 777 UCPDESCR(83H_04H, 0x83, 0x04, UCP_F_FM | UCP_F_WM), 778 UCPDESCR(83H_08H, 0x83, 0x08, UCP_F_FM | UCP_F_WM), 779 780 UCPDESCR(84H_01H, 0x84, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | 781 UCP_F_HW), 782 UCPDESCR(84H_02H, 0x84, 0x02, UCP_F_FM | UCP_F_WM), 783 UCPDESCR(84H_04H, 0x84, 0x04, UCP_F_FM | UCP_F_WM), 784 UCPDESCR(84H_08H, 0x84, 0x08, UCP_F_FM | UCP_F_WM), 785 UCPDESCR(85H_02H, 0x85, 0x02, UCP_F_FM | UCP_F_WM), 786 UCPDESCR(86H_01H, 0x86, 0x01, UCP_F_FM | UCP_F_WM) 787}; 788 789static const int nucp_events = sizeof(ucp_events) / sizeof(ucp_events[0]); 790 791static pmc_value_t 792ucp_perfctr_value_to_reload_count(pmc_value_t v) 793{ 794 v &= (1ULL << uncore_ucp_width) - 1; 795 return (1ULL << uncore_ucp_width) - v; 796} 797 798static pmc_value_t 799ucp_reload_count_to_perfctr_value(pmc_value_t rlc) 800{ 801 return (1ULL << uncore_ucp_width) - rlc; 802} 803 804/* 805 * Counter specific event information for Sandybridge and Haswell 806 */ 807static int 808ucp_event_sb_hw_ok_on_counter(enum pmc_event pe, int ri) 809{ 810 uint32_t mask; 811 812 switch (pe) { 813 /* 814 * Events valid only on counter 0. 815 */ 816 case PMC_EV_UCP_EVENT_80H_01H: 817 case PMC_EV_UCP_EVENT_83H_01H: 818 mask = (1 << 0); 819 break; 820 821 default: 822 mask = ~0; /* Any row index is ok. */ 823 } 824 825 return (mask & (1 << ri)); 826} 827 828static int 829ucp_allocate_pmc(int cpu, int ri, struct pmc *pm, 830 const struct pmc_op_pmcallocate *a) 831{ 832 int n; 833 enum pmc_event ev; 834 struct ucp_event_descr *ie; 835 uint32_t caps, config, cpuflag, evsel; 836 837 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 838 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 839 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 840 ("[uncore,%d] illegal row-index value %d", __LINE__, ri)); 841 842 /* check requested capabilities */ 843 caps = a->pm_caps; 844 if ((UCP_PMC_CAPS & caps) != caps) 845 return (EPERM); 846 847 ev = pm->pm_event; 848 849 switch (uncore_cputype) { 850 case PMC_CPU_INTEL_HASWELL: 851 case PMC_CPU_INTEL_SANDYBRIDGE: 852 if (ucp_event_sb_hw_ok_on_counter(ev, ri) == 0) 853 return (EINVAL); 854 break; 855 default: 856 break; 857 } 858 859 860 /* 861 * Look for an event descriptor with matching CPU and event id 862 * fields. 863 */ 864 865 switch (uncore_cputype) { 866 case PMC_CPU_INTEL_COREI7: 867 cpuflag = UCP_F_I7; 868 break; 869 case PMC_CPU_INTEL_HASWELL: 870 cpuflag = UCP_F_HW; 871 break; 872 case PMC_CPU_INTEL_SANDYBRIDGE: 873 cpuflag = UCP_F_SB; 874 break; 875 case PMC_CPU_INTEL_WESTMERE: 876 cpuflag = UCP_F_WM; 877 break; 878 default: 879 return (EINVAL); 880 } 881 882 for (n = 0, ie = ucp_events; n < nucp_events; n++, ie++) 883 if (ie->ucp_ev == ev && ie->ucp_flags & cpuflag) 884 break; 885 886 if (n == nucp_events) 887 return (EINVAL); 888 889 /* 890 * A matching event descriptor has been found, so start 891 * assembling the contents of the event select register. 892 */ 893 evsel = ie->ucp_evcode | UCP_EN; 894 895 config = a->pm_md.pm_ucp.pm_ucp_config & ~UCP_F_CMASK; 896 897 /* 898 * If the event uses a fixed umask value, reject any umask 899 * bits set by the user. 900 */ 901 if (ie->ucp_flags & UCP_F_FM) { 902 903 if (UCP_UMASK(config) != 0) 904 return (EINVAL); 905 906 evsel |= (ie->ucp_umask << 8); 907 908 } else 909 return (EINVAL); 910 911 if (caps & PMC_CAP_THRESHOLD) 912 evsel |= (a->pm_md.pm_ucp.pm_ucp_config & UCP_F_CMASK); 913 if (caps & PMC_CAP_EDGE) 914 evsel |= UCP_EDGE; 915 if (caps & PMC_CAP_INVERT) 916 evsel |= UCP_INV; 917 918 pm->pm_md.pm_ucp.pm_ucp_evsel = evsel; 919 920 return (0); 921} 922 923static int 924ucp_config_pmc(int cpu, int ri, struct pmc *pm) 925{ 926 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 927 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 928 929 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 930 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 931 932 PMCDBG(MDP,CFG,1, "ucp-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 933 934 KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__, 935 cpu)); 936 937 uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc = pm; 938 939 return (0); 940} 941 942static int 943ucp_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 944{ 945 int error; 946 struct pmc_hw *phw; 947 char ucp_name[PMC_NAME_MAX]; 948 949 phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri]; 950 951 (void) snprintf(ucp_name, sizeof(ucp_name), "UCP-%d", ri); 952 if ((error = copystr(ucp_name, pi->pm_name, PMC_NAME_MAX, 953 NULL)) != 0) 954 return (error); 955 956 pi->pm_class = PMC_CLASS_UCP; 957 958 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 959 pi->pm_enabled = TRUE; 960 *ppmc = phw->phw_pmc; 961 } else { 962 pi->pm_enabled = FALSE; 963 *ppmc = NULL; 964 } 965 966 return (0); 967} 968 969static int 970ucp_get_config(int cpu, int ri, struct pmc **ppm) 971{ 972 *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc; 973 974 return (0); 975} 976 977static int 978ucp_read_pmc(int cpu, int ri, pmc_value_t *v) 979{ 980 struct pmc *pm; 981 pmc_value_t tmp; 982 983 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 984 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 985 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 986 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 987 988 pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc; 989 990 KASSERT(pm, 991 ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 992 ri)); 993 994 tmp = rdmsr(UCP_PMC0 + ri); 995 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 996 *v = ucp_perfctr_value_to_reload_count(tmp); 997 else 998 *v = tmp; 999 1000 PMCDBG(MDP,REA,1, "ucp-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 1001 ri, *v); 1002 1003 return (0); 1004} 1005 1006static int 1007ucp_release_pmc(int cpu, int ri, struct pmc *pm) 1008{ 1009 (void) pm; 1010 1011 PMCDBG(MDP,REL,1, "ucp-release cpu=%d ri=%d pm=%p", cpu, ri, 1012 pm); 1013 1014 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1015 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 1016 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 1017 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 1018 1019 KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc 1020 == NULL, ("[uncore,%d] PHW pmc non-NULL", __LINE__)); 1021 1022 return (0); 1023} 1024 1025static int 1026ucp_start_pmc(int cpu, int ri) 1027{ 1028 struct pmc *pm; 1029 uint32_t evsel; 1030 struct uncore_cpu *cc; 1031 1032 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1033 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 1034 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 1035 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 1036 1037 cc = uncore_pcpu[cpu]; 1038 pm = cc->pc_uncorepmcs[ri].phw_pmc; 1039 1040 KASSERT(pm, 1041 ("[uncore,%d] starting cpu%d,ri%d with no pmc configured", 1042 __LINE__, cpu, ri)); 1043 1044 PMCDBG(MDP,STA,1, "ucp-start cpu=%d ri=%d", cpu, ri); 1045 1046 evsel = pm->pm_md.pm_ucp.pm_ucp_evsel; 1047 1048 PMCDBG(MDP,STA,2, 1049 "ucp-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 1050 cpu, ri, SELECTSEL(uncore_cputype) + ri, evsel); 1051 1052 /* Event specific configuration. */ 1053 switch (pm->pm_event) { 1054 case PMC_EV_UCP_EVENT_0CH_04H_E: 1055 case PMC_EV_UCP_EVENT_0CH_08H_E: 1056 wrmsr(MSR_GQ_SNOOP_MESF,0x2); 1057 break; 1058 case PMC_EV_UCP_EVENT_0CH_04H_F: 1059 case PMC_EV_UCP_EVENT_0CH_08H_F: 1060 wrmsr(MSR_GQ_SNOOP_MESF,0x8); 1061 break; 1062 case PMC_EV_UCP_EVENT_0CH_04H_M: 1063 case PMC_EV_UCP_EVENT_0CH_08H_M: 1064 wrmsr(MSR_GQ_SNOOP_MESF,0x1); 1065 break; 1066 case PMC_EV_UCP_EVENT_0CH_04H_S: 1067 case PMC_EV_UCP_EVENT_0CH_08H_S: 1068 wrmsr(MSR_GQ_SNOOP_MESF,0x4); 1069 break; 1070 default: 1071 break; 1072 } 1073 1074 wrmsr(SELECTSEL(uncore_cputype) + ri, evsel); 1075 1076 do { 1077 cc->pc_resync = 0; 1078 cc->pc_globalctrl |= (1ULL << ri); 1079 wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl); 1080 } while (cc->pc_resync != 0); 1081 1082 return (0); 1083} 1084 1085static int 1086ucp_stop_pmc(int cpu, int ri) 1087{ 1088 struct pmc *pm; 1089 struct uncore_cpu *cc; 1090 1091 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1092 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 1093 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 1094 ("[uncore,%d] illegal row index %d", __LINE__, ri)); 1095 1096 cc = uncore_pcpu[cpu]; 1097 pm = cc->pc_uncorepmcs[ri].phw_pmc; 1098 1099 KASSERT(pm, 1100 ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1101 cpu, ri)); 1102 1103 PMCDBG(MDP,STO,1, "ucp-stop cpu=%d ri=%d", cpu, ri); 1104 1105 /* stop hw. */ 1106 wrmsr(SELECTSEL(uncore_cputype) + ri, 0); 1107 1108 do { 1109 cc->pc_resync = 0; 1110 cc->pc_globalctrl &= ~(1ULL << ri); 1111 wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl); 1112 } while (cc->pc_resync != 0); 1113 1114 return (0); 1115} 1116 1117static int 1118ucp_write_pmc(int cpu, int ri, pmc_value_t v) 1119{ 1120 struct pmc *pm; 1121 struct uncore_cpu *cc; 1122 1123 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1124 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 1125 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 1126 ("[uncore,%d] illegal row index %d", __LINE__, ri)); 1127 1128 cc = uncore_pcpu[cpu]; 1129 pm = cc->pc_uncorepmcs[ri].phw_pmc; 1130 1131 KASSERT(pm, 1132 ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1133 cpu, ri)); 1134 1135 PMCDBG(MDP,WRI,1, "ucp-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 1136 UCP_PMC0 + ri, v); 1137 1138 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1139 v = ucp_reload_count_to_perfctr_value(v); 1140 1141 /* 1142 * Write the new value to the counter. The counter will be in 1143 * a stopped state when the pcd_write() entry point is called. 1144 */ 1145 1146 wrmsr(UCP_PMC0 + ri, v); 1147 1148 return (0); 1149} 1150 1151 1152static void 1153ucp_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 1154{ 1155 struct pmc_classdep *pcd; 1156 1157 KASSERT(md != NULL, ("[ucp,%d] md is NULL", __LINE__)); 1158 1159 PMCDBG(MDP,INI,1, "%s", "ucp-initialize"); 1160 1161 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP]; 1162 1163 pcd->pcd_caps = UCP_PMC_CAPS; 1164 pcd->pcd_class = PMC_CLASS_UCP; 1165 pcd->pcd_num = npmc; 1166 pcd->pcd_ri = md->pmd_npmc; 1167 pcd->pcd_width = pmcwidth; 1168 1169 pcd->pcd_allocate_pmc = ucp_allocate_pmc; 1170 pcd->pcd_config_pmc = ucp_config_pmc; 1171 pcd->pcd_describe = ucp_describe; 1172 pcd->pcd_get_config = ucp_get_config; 1173 pcd->pcd_get_msr = NULL; 1174 pcd->pcd_pcpu_fini = uncore_pcpu_fini; 1175 pcd->pcd_pcpu_init = uncore_pcpu_init; 1176 pcd->pcd_read_pmc = ucp_read_pmc; 1177 pcd->pcd_release_pmc = ucp_release_pmc; 1178 pcd->pcd_start_pmc = ucp_start_pmc; 1179 pcd->pcd_stop_pmc = ucp_stop_pmc; 1180 pcd->pcd_write_pmc = ucp_write_pmc; 1181 1182 md->pmd_npmc += npmc; 1183} 1184 1185int 1186pmc_uncore_initialize(struct pmc_mdep *md, int maxcpu) 1187{ 1188 uncore_cputype = md->pmd_cputype; 1189 uncore_pmcmask = 0; 1190 1191 /* 1192 * Initialize programmable counters. 1193 */ 1194 1195 uncore_ucp_npmc = 8; 1196 uncore_ucp_width = 48; 1197 1198 uncore_pmcmask |= ((1ULL << uncore_ucp_npmc) - 1); 1199 1200 ucp_initialize(md, maxcpu, uncore_ucp_npmc, uncore_ucp_width); 1201 1202 /* 1203 * Initialize fixed function counters, if present. 1204 */ 1205 uncore_ucf_ri = uncore_ucp_npmc; 1206 uncore_ucf_npmc = 1; 1207 uncore_ucf_width = 48; 1208 1209 ucf_initialize(md, maxcpu, uncore_ucf_npmc, uncore_ucf_width); 1210 uncore_pmcmask |= ((1ULL << uncore_ucf_npmc) - 1) << SELECTOFF(uncore_cputype); 1211 1212 PMCDBG(MDP,INI,1,"uncore-init pmcmask=0x%jx ucfri=%d", uncore_pmcmask, 1213 uncore_ucf_ri); 1214 1215 uncore_pcpu = malloc(sizeof(struct uncore_cpu **) * maxcpu, M_PMC, 1216 M_ZERO | M_WAITOK); 1217 1218 return (0); 1219} 1220 1221void 1222pmc_uncore_finalize(struct pmc_mdep *md) 1223{ 1224 PMCDBG(MDP,INI,1, "%s", "uncore-finalize"); 1225 1226 free(uncore_pcpu, M_PMC); 1227 uncore_pcpu = NULL; 1228} 1229