hwpmc_uncore.c revision 234041
1/*- 2 * Copyright (c) 2010 Fabien Thomas 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Intel Uncore PMCs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: stable/9/sys/dev/hwpmc/hwpmc_uncore.c 234041 2012-04-08 20:40:26Z davide $"); 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/pmc.h> 37#include <sys/pmckern.h> 38#include <sys/systm.h> 39 40#include <machine/intr_machdep.h> 41#include <machine/apicvar.h> 42#include <machine/cpu.h> 43#include <machine/cpufunc.h> 44#include <machine/specialreg.h> 45 46#define UCF_PMC_CAPS \ 47 (PMC_CAP_READ | PMC_CAP_WRITE) 48 49#define UCP_PMC_CAPS \ 50 (PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 51 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 52 53static enum pmc_cputype uncore_cputype; 54 55struct uncore_cpu { 56 volatile uint32_t pc_resync; 57 volatile uint32_t pc_ucfctrl; /* Fixed function control. */ 58 volatile uint64_t pc_globalctrl; /* Global control register. */ 59 struct pmc_hw pc_uncorepmcs[]; 60}; 61 62static struct uncore_cpu **uncore_pcpu; 63 64static uint64_t uncore_pmcmask; 65 66static int uncore_ucf_ri; /* relative index of fixed counters */ 67static int uncore_ucf_width; 68static int uncore_ucf_npmc; 69 70static int uncore_ucp_width; 71static int uncore_ucp_npmc; 72 73static int 74uncore_pcpu_noop(struct pmc_mdep *md, int cpu) 75{ 76 (void) md; 77 (void) cpu; 78 return (0); 79} 80 81static int 82uncore_pcpu_init(struct pmc_mdep *md, int cpu) 83{ 84 struct pmc_cpu *pc; 85 struct uncore_cpu *cc; 86 struct pmc_hw *phw; 87 int uncore_ri, n, npmc; 88 89 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 90 ("[ucf,%d] insane cpu number %d", __LINE__, cpu)); 91 92 PMCDBG(MDP,INI,1,"uncore-init cpu=%d", cpu); 93 94 uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri; 95 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num; 96 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num; 97 98 cc = malloc(sizeof(struct uncore_cpu) + npmc * sizeof(struct pmc_hw), 99 M_PMC, M_WAITOK | M_ZERO); 100 101 uncore_pcpu[cpu] = cc; 102 pc = pmc_pcpu[cpu]; 103 104 KASSERT(pc != NULL && cc != NULL, 105 ("[uncore,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 106 107 for (n = 0, phw = cc->pc_uncorepmcs; n < npmc; n++, phw++) { 108 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 109 PMC_PHW_CPU_TO_STATE(cpu) | 110 PMC_PHW_INDEX_TO_STATE(n + uncore_ri); 111 phw->phw_pmc = NULL; 112 pc->pc_hwpmcs[n + uncore_ri] = phw; 113 } 114 115 return (0); 116} 117 118static int 119uncore_pcpu_fini(struct pmc_mdep *md, int cpu) 120{ 121 int uncore_ri, n, npmc; 122 struct pmc_cpu *pc; 123 struct uncore_cpu *cc; 124 125 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 126 ("[uncore,%d] insane cpu number (%d)", __LINE__, cpu)); 127 128 PMCDBG(MDP,INI,1,"uncore-pcpu-fini cpu=%d", cpu); 129 130 if ((cc = uncore_pcpu[cpu]) == NULL) 131 return (0); 132 133 uncore_pcpu[cpu] = NULL; 134 135 pc = pmc_pcpu[cpu]; 136 137 KASSERT(pc != NULL, ("[uncore,%d] NULL per-cpu %d state", __LINE__, 138 cpu)); 139 140 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num; 141 uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri; 142 143 for (n = 0; n < npmc; n++) 144 wrmsr(UCP_EVSEL0 + n, 0); 145 146 wrmsr(UCF_CTRL, 0); 147 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num; 148 149 for (n = 0; n < npmc; n++) 150 pc->pc_hwpmcs[n + uncore_ri] = NULL; 151 152 free(cc, M_PMC); 153 154 return (0); 155} 156 157/* 158 * Fixed function counters. 159 */ 160 161static pmc_value_t 162ucf_perfctr_value_to_reload_count(pmc_value_t v) 163{ 164 v &= (1ULL << uncore_ucf_width) - 1; 165 return (1ULL << uncore_ucf_width) - v; 166} 167 168static pmc_value_t 169ucf_reload_count_to_perfctr_value(pmc_value_t rlc) 170{ 171 return (1ULL << uncore_ucf_width) - rlc; 172} 173 174static int 175ucf_allocate_pmc(int cpu, int ri, struct pmc *pm, 176 const struct pmc_op_pmcallocate *a) 177{ 178 enum pmc_event ev; 179 uint32_t caps, flags; 180 181 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 182 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 183 184 PMCDBG(MDP,ALL,1, "ucf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 185 186 if (ri < 0 || ri > uncore_ucf_npmc) 187 return (EINVAL); 188 189 caps = a->pm_caps; 190 191 if (a->pm_class != PMC_CLASS_UCF || 192 (caps & UCF_PMC_CAPS) != caps) 193 return (EINVAL); 194 195 ev = pm->pm_event; 196 if (ev < PMC_EV_UCF_FIRST || ev > PMC_EV_UCF_LAST) 197 return (EINVAL); 198 199 flags = UCF_EN; 200 201 pm->pm_md.pm_ucf.pm_ucf_ctrl = (flags << (ri * 4)); 202 203 PMCDBG(MDP,ALL,2, "ucf-allocate config=0x%jx", 204 (uintmax_t) pm->pm_md.pm_ucf.pm_ucf_ctrl); 205 206 return (0); 207} 208 209static int 210ucf_config_pmc(int cpu, int ri, struct pmc *pm) 211{ 212 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 213 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 214 215 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 216 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 217 218 PMCDBG(MDP,CFG,1, "ucf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 219 220 KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__, 221 cpu)); 222 223 uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc = pm; 224 225 return (0); 226} 227 228static int 229ucf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 230{ 231 int error; 232 struct pmc_hw *phw; 233 char ucf_name[PMC_NAME_MAX]; 234 235 phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri]; 236 237 (void) snprintf(ucf_name, sizeof(ucf_name), "UCF-%d", ri); 238 if ((error = copystr(ucf_name, pi->pm_name, PMC_NAME_MAX, 239 NULL)) != 0) 240 return (error); 241 242 pi->pm_class = PMC_CLASS_UCF; 243 244 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 245 pi->pm_enabled = TRUE; 246 *ppmc = phw->phw_pmc; 247 } else { 248 pi->pm_enabled = FALSE; 249 *ppmc = NULL; 250 } 251 252 return (0); 253} 254 255static int 256ucf_get_config(int cpu, int ri, struct pmc **ppm) 257{ 258 *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 259 260 return (0); 261} 262 263static int 264ucf_read_pmc(int cpu, int ri, pmc_value_t *v) 265{ 266 struct pmc *pm; 267 pmc_value_t tmp; 268 269 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 270 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 271 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 272 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 273 274 pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 275 276 KASSERT(pm, 277 ("[uncore,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 278 ri, ri + uncore_ucf_ri)); 279 280 tmp = rdmsr(UCF_CTR0 + ri); 281 282 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 283 *v = ucf_perfctr_value_to_reload_count(tmp); 284 else 285 *v = tmp; 286 287 PMCDBG(MDP,REA,1, "ucf-read cpu=%d ri=%d -> v=%jx", cpu, ri, *v); 288 289 return (0); 290} 291 292static int 293ucf_release_pmc(int cpu, int ri, struct pmc *pmc) 294{ 295 PMCDBG(MDP,REL,1, "ucf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 296 297 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 298 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 299 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 300 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 301 302 KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc == NULL, 303 ("[uncore,%d] PHW pmc non-NULL", __LINE__)); 304 305 return (0); 306} 307 308static int 309ucf_start_pmc(int cpu, int ri) 310{ 311 struct pmc *pm; 312 struct uncore_cpu *ucfc; 313 314 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 315 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 316 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 317 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 318 319 PMCDBG(MDP,STA,1,"ucf-start cpu=%d ri=%d", cpu, ri); 320 321 ucfc = uncore_pcpu[cpu]; 322 pm = ucfc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 323 324 ucfc->pc_ucfctrl |= pm->pm_md.pm_ucf.pm_ucf_ctrl; 325 326 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl); 327 328 do { 329 ucfc->pc_resync = 0; 330 ucfc->pc_globalctrl |= (1ULL << (ri + UCF_OFFSET)); 331 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl); 332 } while (ucfc->pc_resync != 0); 333 334 PMCDBG(MDP,STA,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)", 335 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL), 336 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL)); 337 338 return (0); 339} 340 341static int 342ucf_stop_pmc(int cpu, int ri) 343{ 344 uint32_t fc; 345 struct uncore_cpu *ucfc; 346 347 PMCDBG(MDP,STO,1,"ucf-stop cpu=%d ri=%d", cpu, ri); 348 349 ucfc = uncore_pcpu[cpu]; 350 351 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 352 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 353 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 354 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 355 356 fc = (UCF_MASK << (ri * 4)); 357 358 ucfc->pc_ucfctrl &= ~fc; 359 360 PMCDBG(MDP,STO,1,"ucf-stop ucfctrl=%x", ucfc->pc_ucfctrl); 361 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl); 362 363 do { 364 ucfc->pc_resync = 0; 365 ucfc->pc_globalctrl &= ~(1ULL << (ri + UCF_OFFSET)); 366 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl); 367 } while (ucfc->pc_resync != 0); 368 369 PMCDBG(MDP,STO,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)", 370 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL), 371 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL)); 372 373 return (0); 374} 375 376static int 377ucf_write_pmc(int cpu, int ri, pmc_value_t v) 378{ 379 struct uncore_cpu *cc; 380 struct pmc *pm; 381 382 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 383 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 384 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 385 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 386 387 cc = uncore_pcpu[cpu]; 388 pm = cc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 389 390 KASSERT(pm, 391 ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 392 393 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 394 v = ucf_reload_count_to_perfctr_value(v); 395 396 wrmsr(UCF_CTRL, 0); /* Turn off fixed counters */ 397 wrmsr(UCF_CTR0 + ri, v); 398 wrmsr(UCF_CTRL, cc->pc_ucfctrl); 399 400 PMCDBG(MDP,WRI,1, "ucf-write cpu=%d ri=%d v=%jx ucfctrl=%jx ", 401 cpu, ri, v, (uintmax_t) rdmsr(UCF_CTRL)); 402 403 return (0); 404} 405 406 407static void 408ucf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 409{ 410 struct pmc_classdep *pcd; 411 412 KASSERT(md != NULL, ("[ucf,%d] md is NULL", __LINE__)); 413 414 PMCDBG(MDP,INI,1, "%s", "ucf-initialize"); 415 416 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF]; 417 418 pcd->pcd_caps = UCF_PMC_CAPS; 419 pcd->pcd_class = PMC_CLASS_UCF; 420 pcd->pcd_num = npmc; 421 pcd->pcd_ri = md->pmd_npmc; 422 pcd->pcd_width = pmcwidth; 423 424 pcd->pcd_allocate_pmc = ucf_allocate_pmc; 425 pcd->pcd_config_pmc = ucf_config_pmc; 426 pcd->pcd_describe = ucf_describe; 427 pcd->pcd_get_config = ucf_get_config; 428 pcd->pcd_get_msr = NULL; 429 pcd->pcd_pcpu_fini = uncore_pcpu_noop; 430 pcd->pcd_pcpu_init = uncore_pcpu_noop; 431 pcd->pcd_read_pmc = ucf_read_pmc; 432 pcd->pcd_release_pmc = ucf_release_pmc; 433 pcd->pcd_start_pmc = ucf_start_pmc; 434 pcd->pcd_stop_pmc = ucf_stop_pmc; 435 pcd->pcd_write_pmc = ucf_write_pmc; 436 437 md->pmd_npmc += npmc; 438} 439 440/* 441 * Intel programmable PMCs. 442 */ 443 444/* 445 * Event descriptor tables. 446 * 447 * For each event id, we track: 448 * 449 * 1. The CPUs that the event is valid for. 450 * 451 * 2. If the event uses a fixed UMASK, the value of the umask field. 452 * If the event doesn't use a fixed UMASK, a mask of legal bits 453 * to check against. 454 */ 455 456struct ucp_event_descr { 457 enum pmc_event ucp_ev; 458 unsigned char ucp_evcode; 459 unsigned char ucp_umask; 460 unsigned char ucp_flags; 461}; 462 463#define UCP_F_I7 (1 << 0) /* CPU: Core i7 */ 464#define UCP_F_WM (1 << 1) /* CPU: Westmere */ 465#define UCP_F_FM (1 << 2) /* Fixed mask */ 466 467#define UCP_F_ALLCPUS \ 468 (UCP_F_I7 | UCP_F_WM) 469 470#define UCP_F_CMASK 0xFF000000 471 472static struct ucp_event_descr ucp_events[] = { 473#undef UCPDESCR 474#define UCPDESCR(N,EV,UM,FLAGS) { \ 475 .ucp_ev = PMC_EV_UCP_EVENT_##N, \ 476 .ucp_evcode = (EV), \ 477 .ucp_umask = (UM), \ 478 .ucp_flags = (FLAGS) \ 479 } 480 481 UCPDESCR(00H_01H, 0x00, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 482 UCPDESCR(00H_02H, 0x00, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 483 UCPDESCR(00H_04H, 0x00, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 484 485 UCPDESCR(01H_01H, 0x01, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 486 UCPDESCR(01H_02H, 0x01, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 487 UCPDESCR(01H_04H, 0x01, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 488 489 UCPDESCR(02H_01H, 0x02, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 490 UCPDESCR(03H_01H, 0x03, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 491 UCPDESCR(03H_02H, 0x03, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 492 UCPDESCR(03H_04H, 0x03, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 493 UCPDESCR(03H_08H, 0x03, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 494 UCPDESCR(03H_10H, 0x03, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 495 UCPDESCR(03H_20H, 0x03, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 496 UCPDESCR(03H_40H, 0x03, 0x40, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 497 498 UCPDESCR(04H_01H, 0x04, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 499 UCPDESCR(04H_02H, 0x04, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 500 UCPDESCR(04H_04H, 0x04, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 501 UCPDESCR(04H_08H, 0x04, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 502 UCPDESCR(04H_10H, 0x04, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 503 504 UCPDESCR(05H_01H, 0x05, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 505 UCPDESCR(05H_02H, 0x05, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 506 UCPDESCR(05H_04H, 0x05, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 507 508 UCPDESCR(06H_01H, 0x06, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 509 UCPDESCR(06H_02H, 0x06, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 510 UCPDESCR(06H_04H, 0x06, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 511 UCPDESCR(06H_08H, 0x06, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 512 UCPDESCR(06H_10H, 0x06, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 513 UCPDESCR(06H_20H, 0x06, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 514 515 UCPDESCR(07H_01H, 0x07, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 516 UCPDESCR(07H_02H, 0x07, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 517 UCPDESCR(07H_04H, 0x07, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 518 UCPDESCR(07H_08H, 0x07, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 519 UCPDESCR(07H_10H, 0x07, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 520 UCPDESCR(07H_20H, 0x07, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 521 UCPDESCR(07H_24H, 0x07, 0x24, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 522 523 UCPDESCR(08H_01H, 0x08, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 524 UCPDESCR(08H_02H, 0x08, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 525 UCPDESCR(08H_04H, 0x08, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 526 UCPDESCR(08H_03H, 0x08, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 527 528 UCPDESCR(09H_01H, 0x09, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 529 UCPDESCR(09H_02H, 0x09, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 530 UCPDESCR(09H_04H, 0x09, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 531 UCPDESCR(09H_03H, 0x09, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 532 533 UCPDESCR(0AH_01H, 0x0A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 534 UCPDESCR(0AH_02H, 0x0A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 535 UCPDESCR(0AH_04H, 0x0A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 536 UCPDESCR(0AH_08H, 0x0A, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 537 UCPDESCR(0AH_0FH, 0x0A, 0x0F, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 538 539 UCPDESCR(0BH_01H, 0x0B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 540 UCPDESCR(0BH_02H, 0x0B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 541 UCPDESCR(0BH_04H, 0x0B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 542 UCPDESCR(0BH_08H, 0x0B, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 543 UCPDESCR(0BH_10H, 0x0B, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 544 UCPDESCR(0BH_1FH, 0x0B, 0x1F, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 545 546 UCPDESCR(0CH_01H, 0x0C, 0x01, UCP_F_FM | UCP_F_WM), 547 UCPDESCR(0CH_02H, 0x0C, 0x02, UCP_F_FM | UCP_F_WM), 548 UCPDESCR(0CH_04H_E, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), 549 UCPDESCR(0CH_04H_F, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), 550 UCPDESCR(0CH_04H_M, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), 551 UCPDESCR(0CH_04H_S, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), 552 UCPDESCR(0CH_08H_E, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), 553 UCPDESCR(0CH_08H_F, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), 554 UCPDESCR(0CH_08H_M, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), 555 UCPDESCR(0CH_08H_S, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), 556 557 UCPDESCR(20H_01H, 0x20, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 558 UCPDESCR(20H_02H, 0x20, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 559 UCPDESCR(20H_04H, 0x20, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 560 UCPDESCR(20H_08H, 0x20, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 561 UCPDESCR(20H_10H, 0x20, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 562 UCPDESCR(20H_20H, 0x20, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 563 564 UCPDESCR(21H_01H, 0x21, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 565 UCPDESCR(21H_02H, 0x21, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 566 UCPDESCR(21H_04H, 0x21, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 567 568 UCPDESCR(22H_01H, 0x22, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 569 UCPDESCR(22H_02H, 0x22, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 570 UCPDESCR(22H_04H, 0x22, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 571 572 UCPDESCR(23H_01H, 0x23, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 573 UCPDESCR(23H_02H, 0x23, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 574 UCPDESCR(23H_04H, 0x23, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 575 576 UCPDESCR(24H_02H, 0x24, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 577 UCPDESCR(24H_04H, 0x24, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 578 579 UCPDESCR(25H_01H, 0x25, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 580 UCPDESCR(25H_02H, 0x25, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 581 UCPDESCR(25H_04H, 0x25, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 582 583 UCPDESCR(26H_01H, 0x26, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 584 585 UCPDESCR(27H_01H, 0x27, 0x01, UCP_F_FM | UCP_F_I7), 586 UCPDESCR(27H_02H, 0x27, 0x02, UCP_F_FM | UCP_F_I7), 587 UCPDESCR(27H_04H, 0x27, 0x04, UCP_F_FM | UCP_F_I7), 588 UCPDESCR(27H_08H, 0x27, 0x08, UCP_F_FM | UCP_F_I7), 589 UCPDESCR(27H_10H, 0x27, 0x10, UCP_F_FM | UCP_F_I7), 590 UCPDESCR(27H_20H, 0x27, 0x20, UCP_F_FM | UCP_F_I7), 591 592 UCPDESCR(28H_01H, 0x28, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 593 UCPDESCR(28H_02H, 0x28, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 594 UCPDESCR(28H_04H, 0x28, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 595 UCPDESCR(28H_08H, 0x28, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 596 UCPDESCR(28H_10H, 0x28, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 597 UCPDESCR(28H_20H, 0x28, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 598 599 UCPDESCR(29H_01H, 0x29, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 600 UCPDESCR(29H_02H, 0x29, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 601 UCPDESCR(29H_04H, 0x29, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 602 UCPDESCR(29H_08H, 0x29, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 603 UCPDESCR(29H_10H, 0x29, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 604 UCPDESCR(29H_20H, 0x29, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 605 606 UCPDESCR(2AH_01H, 0x2A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 607 UCPDESCR(2AH_02H, 0x2A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 608 UCPDESCR(2AH_04H, 0x2A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 609 UCPDESCR(2AH_07H, 0x2A, 0x07, UCP_F_FM | UCP_F_WM), 610 611 UCPDESCR(2BH_01H, 0x2B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 612 UCPDESCR(2BH_02H, 0x2B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 613 UCPDESCR(2BH_04H, 0x2B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 614 UCPDESCR(2BH_07H, 0x2B, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 615 616 UCPDESCR(2CH_01H, 0x2C, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 617 UCPDESCR(2CH_02H, 0x2C, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 618 UCPDESCR(2CH_04H, 0x2C, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 619 UCPDESCR(2CH_07H, 0x2C, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 620 621 UCPDESCR(2DH_01H, 0x2D, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 622 UCPDESCR(2DH_02H, 0x2D, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 623 UCPDESCR(2DH_04H, 0x2D, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 624 UCPDESCR(2DH_07H, 0x2D, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 625 626 UCPDESCR(2EH_01H, 0x2E, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 627 UCPDESCR(2EH_02H, 0x2E, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 628 UCPDESCR(2EH_04H, 0x2E, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 629 UCPDESCR(2EH_07H, 0x2E, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 630 631 UCPDESCR(2FH_01H, 0x2F, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 632 UCPDESCR(2FH_02H, 0x2F, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 633 UCPDESCR(2FH_04H, 0x2F, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 634 UCPDESCR(2FH_07H, 0x2F, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 635 UCPDESCR(2FH_08H, 0x2F, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 636 UCPDESCR(2FH_10H, 0x2F, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 637 UCPDESCR(2FH_20H, 0x2F, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 638 UCPDESCR(2FH_38H, 0x2F, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 639 640 UCPDESCR(30H_01H, 0x30, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 641 UCPDESCR(30H_02H, 0x30, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 642 UCPDESCR(30H_04H, 0x30, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 643 UCPDESCR(30H_07H, 0x30, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 644 645 UCPDESCR(31H_01H, 0x31, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 646 UCPDESCR(31H_02H, 0x31, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 647 UCPDESCR(31H_04H, 0x31, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 648 UCPDESCR(31H_07H, 0x31, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 649 650 UCPDESCR(32H_01H, 0x32, 0x01, UCP_F_FM | UCP_F_WM), 651 UCPDESCR(32H_02H, 0x32, 0x02, UCP_F_FM | UCP_F_WM), 652 UCPDESCR(32H_04H, 0x32, 0x04, UCP_F_FM | UCP_F_WM), 653 UCPDESCR(32H_07H, 0x32, 0x07, UCP_F_FM | UCP_F_WM), 654 655 UCPDESCR(33H_01H, 0x33, 0x01, UCP_F_FM | UCP_F_WM), 656 UCPDESCR(33H_02H, 0x33, 0x02, UCP_F_FM | UCP_F_WM), 657 UCPDESCR(33H_04H, 0x33, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 658 UCPDESCR(33H_07H, 0x33, 0x07, UCP_F_FM | UCP_F_WM), 659 660 UCPDESCR(34H_01H, 0x34, 0x01, UCP_F_FM | UCP_F_WM), 661 UCPDESCR(34H_02H, 0x34, 0x02, UCP_F_FM | UCP_F_WM), 662 UCPDESCR(34H_04H, 0x34, 0x04, UCP_F_FM | UCP_F_WM), 663 UCPDESCR(34H_08H, 0x34, 0x08, UCP_F_FM | UCP_F_WM), 664 UCPDESCR(34H_10H, 0x34, 0x10, UCP_F_FM | UCP_F_WM), 665 UCPDESCR(34H_20H, 0x34, 0x20, UCP_F_FM | UCP_F_WM), 666 667 UCPDESCR(35H_01H, 0x35, 0x01, UCP_F_FM | UCP_F_WM), 668 UCPDESCR(35H_02H, 0x35, 0x02, UCP_F_FM | UCP_F_WM), 669 UCPDESCR(35H_04H, 0x35, 0x04, UCP_F_FM | UCP_F_WM), 670 671 UCPDESCR(40H_01H, 0x40, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 672 UCPDESCR(40H_02H, 0x40, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 673 UCPDESCR(40H_04H, 0x40, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 674 UCPDESCR(40H_08H, 0x40, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 675 UCPDESCR(40H_10H, 0x40, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 676 UCPDESCR(40H_20H, 0x40, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 677 UCPDESCR(40H_07H, 0x40, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 678 UCPDESCR(40H_38H, 0x40, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 679 680 UCPDESCR(41H_01H, 0x41, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 681 UCPDESCR(41H_02H, 0x41, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 682 UCPDESCR(41H_04H, 0x41, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 683 UCPDESCR(41H_08H, 0x41, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 684 UCPDESCR(41H_10H, 0x41, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 685 UCPDESCR(41H_20H, 0x41, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 686 UCPDESCR(41H_07H, 0x41, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 687 UCPDESCR(41H_38H, 0x41, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 688 689 UCPDESCR(42H_01H, 0x42, 0x01, UCP_F_FM | UCP_F_WM), 690 UCPDESCR(42H_02H, 0x42, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 691 UCPDESCR(42H_04H, 0x42, 0x04, UCP_F_FM | UCP_F_WM), 692 UCPDESCR(42H_08H, 0x42, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 693 694 UCPDESCR(43H_01H, 0x43, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 695 UCPDESCR(43H_02H, 0x43, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 696 697 UCPDESCR(60H_01H, 0x60, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 698 UCPDESCR(60H_02H, 0x60, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 699 UCPDESCR(60H_04H, 0x60, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 700 701 UCPDESCR(61H_01H, 0x61, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 702 UCPDESCR(61H_02H, 0x61, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 703 UCPDESCR(61H_04H, 0x61, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 704 705 UCPDESCR(62H_01H, 0x62, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 706 UCPDESCR(62H_02H, 0x62, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 707 UCPDESCR(62H_04H, 0x62, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 708 709 UCPDESCR(63H_01H, 0x63, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 710 UCPDESCR(63H_02H, 0x63, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 711 UCPDESCR(63H_04H, 0x63, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 712 UCPDESCR(63H_08H, 0x63, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 713 UCPDESCR(63H_10H, 0x63, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 714 UCPDESCR(63H_20H, 0x63, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 715 716 UCPDESCR(64H_01H, 0x64, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 717 UCPDESCR(64H_02H, 0x64, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 718 UCPDESCR(64H_04H, 0x64, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 719 UCPDESCR(64H_08H, 0x64, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 720 UCPDESCR(64H_10H, 0x64, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 721 UCPDESCR(64H_20H, 0x64, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 722 723 UCPDESCR(65H_01H, 0x65, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 724 UCPDESCR(65H_02H, 0x65, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 725 UCPDESCR(65H_04H, 0x65, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 726 727 UCPDESCR(66H_01H, 0x66, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 728 UCPDESCR(66H_02H, 0x66, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 729 UCPDESCR(66H_04H, 0x66, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 730 731 UCPDESCR(67H_01H, 0x67, 0x01, UCP_F_FM | UCP_F_WM), 732 UCPDESCR(80H_01H, 0x80, 0x01, UCP_F_FM | UCP_F_WM), 733 UCPDESCR(80H_02H, 0x80, 0x02, UCP_F_FM | UCP_F_WM), 734 UCPDESCR(80H_04H, 0x80, 0x04, UCP_F_FM | UCP_F_WM), 735 UCPDESCR(80H_08H, 0x80, 0x08, UCP_F_FM | UCP_F_WM), 736 UCPDESCR(81H_01H, 0x81, 0x01, UCP_F_FM | UCP_F_WM), 737 UCPDESCR(81H_02H, 0x81, 0x02, UCP_F_FM | UCP_F_WM), 738 UCPDESCR(81H_04H, 0x81, 0x04, UCP_F_FM | UCP_F_WM), 739 UCPDESCR(81H_08H, 0x81, 0x08, UCP_F_FM | UCP_F_WM), 740 UCPDESCR(82H_01H, 0x82, 0x01, UCP_F_FM | UCP_F_WM), 741 UCPDESCR(83H_01H, 0x83, 0x01, UCP_F_FM | UCP_F_WM), 742 UCPDESCR(83H_02H, 0x83, 0x02, UCP_F_FM | UCP_F_WM), 743 UCPDESCR(83H_04H, 0x83, 0x04, UCP_F_FM | UCP_F_WM), 744 UCPDESCR(83H_08H, 0x83, 0x08, UCP_F_FM | UCP_F_WM), 745 UCPDESCR(84H_01H, 0x84, 0x01, UCP_F_FM | UCP_F_WM), 746 UCPDESCR(84H_02H, 0x84, 0x02, UCP_F_FM | UCP_F_WM), 747 UCPDESCR(84H_04H, 0x84, 0x04, UCP_F_FM | UCP_F_WM), 748 UCPDESCR(84H_08H, 0x84, 0x08, UCP_F_FM | UCP_F_WM), 749 UCPDESCR(85H_02H, 0x85, 0x02, UCP_F_FM | UCP_F_WM), 750 UCPDESCR(86H_01H, 0x86, 0x01, UCP_F_FM | UCP_F_WM) 751}; 752 753static const int nucp_events = sizeof(ucp_events) / sizeof(ucp_events[0]); 754 755static pmc_value_t 756ucp_perfctr_value_to_reload_count(pmc_value_t v) 757{ 758 v &= (1ULL << uncore_ucp_width) - 1; 759 return (1ULL << uncore_ucp_width) - v; 760} 761 762static pmc_value_t 763ucp_reload_count_to_perfctr_value(pmc_value_t rlc) 764{ 765 return (1ULL << uncore_ucp_width) - rlc; 766} 767 768static int 769ucp_allocate_pmc(int cpu, int ri, struct pmc *pm, 770 const struct pmc_op_pmcallocate *a) 771{ 772 int n; 773 enum pmc_event ev; 774 struct ucp_event_descr *ie; 775 uint32_t caps, config, cpuflag, evsel; 776 777 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 778 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 779 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 780 ("[uncore,%d] illegal row-index value %d", __LINE__, ri)); 781 782 /* check requested capabilities */ 783 caps = a->pm_caps; 784 if ((UCP_PMC_CAPS & caps) != caps) 785 return (EPERM); 786 787 ev = pm->pm_event; 788 789 /* 790 * Look for an event descriptor with matching CPU and event id 791 * fields. 792 */ 793 794 switch (uncore_cputype) { 795 case PMC_CPU_INTEL_COREI7: 796 cpuflag = UCP_F_I7; 797 break; 798 case PMC_CPU_INTEL_WESTMERE: 799 cpuflag = UCP_F_WM; 800 break; 801 default: 802 return (EINVAL); 803 } 804 805 for (n = 0, ie = ucp_events; n < nucp_events; n++, ie++) 806 if (ie->ucp_ev == ev && ie->ucp_flags & cpuflag) 807 break; 808 809 if (n == nucp_events) 810 return (EINVAL); 811 812 /* 813 * A matching event descriptor has been found, so start 814 * assembling the contents of the event select register. 815 */ 816 evsel = ie->ucp_evcode | UCP_EN; 817 818 config = a->pm_md.pm_ucp.pm_ucp_config & ~UCP_F_CMASK; 819 820 /* 821 * If the event uses a fixed umask value, reject any umask 822 * bits set by the user. 823 */ 824 if (ie->ucp_flags & UCP_F_FM) { 825 826 if (UCP_UMASK(config) != 0) 827 return (EINVAL); 828 829 evsel |= (ie->ucp_umask << 8); 830 831 } else 832 return (EINVAL); 833 834 if (caps & PMC_CAP_THRESHOLD) 835 evsel |= (a->pm_md.pm_ucp.pm_ucp_config & UCP_F_CMASK); 836 if (caps & PMC_CAP_EDGE) 837 evsel |= UCP_EDGE; 838 if (caps & PMC_CAP_INVERT) 839 evsel |= UCP_INV; 840 841 pm->pm_md.pm_ucp.pm_ucp_evsel = evsel; 842 843 return (0); 844} 845 846static int 847ucp_config_pmc(int cpu, int ri, struct pmc *pm) 848{ 849 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 850 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 851 852 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 853 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 854 855 PMCDBG(MDP,CFG,1, "ucp-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 856 857 KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__, 858 cpu)); 859 860 uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc = pm; 861 862 return (0); 863} 864 865static int 866ucp_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 867{ 868 int error; 869 struct pmc_hw *phw; 870 char ucp_name[PMC_NAME_MAX]; 871 872 phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri]; 873 874 (void) snprintf(ucp_name, sizeof(ucp_name), "UCP-%d", ri); 875 if ((error = copystr(ucp_name, pi->pm_name, PMC_NAME_MAX, 876 NULL)) != 0) 877 return (error); 878 879 pi->pm_class = PMC_CLASS_UCP; 880 881 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 882 pi->pm_enabled = TRUE; 883 *ppmc = phw->phw_pmc; 884 } else { 885 pi->pm_enabled = FALSE; 886 *ppmc = NULL; 887 } 888 889 return (0); 890} 891 892static int 893ucp_get_config(int cpu, int ri, struct pmc **ppm) 894{ 895 *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc; 896 897 return (0); 898} 899 900static int 901ucp_read_pmc(int cpu, int ri, pmc_value_t *v) 902{ 903 struct pmc *pm; 904 pmc_value_t tmp; 905 906 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 907 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 908 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 909 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 910 911 pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc; 912 913 KASSERT(pm, 914 ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 915 ri)); 916 917 tmp = rdmsr(UCP_PMC0 + ri); 918 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 919 *v = ucp_perfctr_value_to_reload_count(tmp); 920 else 921 *v = tmp; 922 923 PMCDBG(MDP,REA,1, "ucp-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 924 ri, *v); 925 926 return (0); 927} 928 929static int 930ucp_release_pmc(int cpu, int ri, struct pmc *pm) 931{ 932 (void) pm; 933 934 PMCDBG(MDP,REL,1, "ucp-release cpu=%d ri=%d pm=%p", cpu, ri, 935 pm); 936 937 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 938 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 939 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 940 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 941 942 KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc 943 == NULL, ("[uncore,%d] PHW pmc non-NULL", __LINE__)); 944 945 return (0); 946} 947 948static int 949ucp_start_pmc(int cpu, int ri) 950{ 951 struct pmc *pm; 952 uint32_t evsel; 953 struct uncore_cpu *cc; 954 955 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 956 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 957 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 958 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 959 960 cc = uncore_pcpu[cpu]; 961 pm = cc->pc_uncorepmcs[ri].phw_pmc; 962 963 KASSERT(pm, 964 ("[uncore,%d] starting cpu%d,ri%d with no pmc configured", 965 __LINE__, cpu, ri)); 966 967 PMCDBG(MDP,STA,1, "ucp-start cpu=%d ri=%d", cpu, ri); 968 969 evsel = pm->pm_md.pm_ucp.pm_ucp_evsel; 970 971 PMCDBG(MDP,STA,2, "ucp-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 972 cpu, ri, UCP_EVSEL0 + ri, evsel); 973 974 /* Event specific configuration. */ 975 switch (pm->pm_event) { 976 case PMC_EV_UCP_EVENT_0CH_04H_E: 977 wrmsr(MSR_GQ_SNOOP_MESF,0x2); 978 break; 979 case PMC_EV_UCP_EVENT_0CH_04H_F: 980 wrmsr(MSR_GQ_SNOOP_MESF,0x8); 981 break; 982 case PMC_EV_UCP_EVENT_0CH_04H_M: 983 wrmsr(MSR_GQ_SNOOP_MESF,0x1); 984 break; 985 case PMC_EV_UCP_EVENT_0CH_04H_S: 986 wrmsr(MSR_GQ_SNOOP_MESF,0x4); 987 break; 988 case PMC_EV_UCP_EVENT_0CH_08H_E: 989 wrmsr(MSR_GQ_SNOOP_MESF,0x2); 990 break; 991 case PMC_EV_UCP_EVENT_0CH_08H_F: 992 wrmsr(MSR_GQ_SNOOP_MESF,0x8); 993 break; 994 case PMC_EV_UCP_EVENT_0CH_08H_M: 995 wrmsr(MSR_GQ_SNOOP_MESF,0x1); 996 break; 997 case PMC_EV_UCP_EVENT_0CH_08H_S: 998 wrmsr(MSR_GQ_SNOOP_MESF,0x4); 999 break; 1000 default: 1001 break; 1002 } 1003 1004 wrmsr(UCP_EVSEL0 + ri, evsel); 1005 1006 do { 1007 cc->pc_resync = 0; 1008 cc->pc_globalctrl |= (1ULL << ri); 1009 wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl); 1010 } while (cc->pc_resync != 0); 1011 1012 return (0); 1013} 1014 1015static int 1016ucp_stop_pmc(int cpu, int ri) 1017{ 1018 struct pmc *pm; 1019 struct uncore_cpu *cc; 1020 1021 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1022 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 1023 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 1024 ("[uncore,%d] illegal row index %d", __LINE__, ri)); 1025 1026 cc = uncore_pcpu[cpu]; 1027 pm = cc->pc_uncorepmcs[ri].phw_pmc; 1028 1029 KASSERT(pm, 1030 ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1031 cpu, ri)); 1032 1033 PMCDBG(MDP,STO,1, "ucp-stop cpu=%d ri=%d", cpu, ri); 1034 1035 wrmsr(UCP_EVSEL0 + ri, 0); /* stop hw */ 1036 1037 do { 1038 cc->pc_resync = 0; 1039 cc->pc_globalctrl &= ~(1ULL << ri); 1040 wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl); 1041 } while (cc->pc_resync != 0); 1042 1043 return (0); 1044} 1045 1046static int 1047ucp_write_pmc(int cpu, int ri, pmc_value_t v) 1048{ 1049 struct pmc *pm; 1050 struct uncore_cpu *cc; 1051 1052 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1053 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 1054 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 1055 ("[uncore,%d] illegal row index %d", __LINE__, ri)); 1056 1057 cc = uncore_pcpu[cpu]; 1058 pm = cc->pc_uncorepmcs[ri].phw_pmc; 1059 1060 KASSERT(pm, 1061 ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1062 cpu, ri)); 1063 1064 PMCDBG(MDP,WRI,1, "ucp-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 1065 UCP_PMC0 + ri, v); 1066 1067 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1068 v = ucp_reload_count_to_perfctr_value(v); 1069 1070 /* 1071 * Write the new value to the counter. The counter will be in 1072 * a stopped state when the pcd_write() entry point is called. 1073 */ 1074 1075 wrmsr(UCP_PMC0 + ri, v); 1076 1077 return (0); 1078} 1079 1080 1081static void 1082ucp_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 1083{ 1084 struct pmc_classdep *pcd; 1085 1086 KASSERT(md != NULL, ("[ucp,%d] md is NULL", __LINE__)); 1087 1088 PMCDBG(MDP,INI,1, "%s", "ucp-initialize"); 1089 1090 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP]; 1091 1092 pcd->pcd_caps = UCP_PMC_CAPS; 1093 pcd->pcd_class = PMC_CLASS_UCP; 1094 pcd->pcd_num = npmc; 1095 pcd->pcd_ri = md->pmd_npmc; 1096 pcd->pcd_width = pmcwidth; 1097 1098 pcd->pcd_allocate_pmc = ucp_allocate_pmc; 1099 pcd->pcd_config_pmc = ucp_config_pmc; 1100 pcd->pcd_describe = ucp_describe; 1101 pcd->pcd_get_config = ucp_get_config; 1102 pcd->pcd_get_msr = NULL; 1103 pcd->pcd_pcpu_fini = uncore_pcpu_fini; 1104 pcd->pcd_pcpu_init = uncore_pcpu_init; 1105 pcd->pcd_read_pmc = ucp_read_pmc; 1106 pcd->pcd_release_pmc = ucp_release_pmc; 1107 pcd->pcd_start_pmc = ucp_start_pmc; 1108 pcd->pcd_stop_pmc = ucp_stop_pmc; 1109 pcd->pcd_write_pmc = ucp_write_pmc; 1110 1111 md->pmd_npmc += npmc; 1112} 1113 1114int 1115pmc_uncore_initialize(struct pmc_mdep *md, int maxcpu) 1116{ 1117 uncore_cputype = md->pmd_cputype; 1118 uncore_pmcmask = 0; 1119 1120 /* 1121 * Initialize programmable counters. 1122 */ 1123 1124 uncore_ucp_npmc = 8; 1125 uncore_ucp_width = 48; 1126 1127 uncore_pmcmask |= ((1ULL << uncore_ucp_npmc) - 1); 1128 1129 ucp_initialize(md, maxcpu, uncore_ucp_npmc, uncore_ucp_width); 1130 1131 /* 1132 * Initialize fixed function counters, if present. 1133 */ 1134 uncore_ucf_ri = uncore_ucp_npmc; 1135 uncore_ucf_npmc = 1; 1136 uncore_ucf_width = 48; 1137 1138 ucf_initialize(md, maxcpu, uncore_ucf_npmc, uncore_ucf_width); 1139 uncore_pmcmask |= ((1ULL << uncore_ucf_npmc) - 1) << UCF_OFFSET; 1140 1141 PMCDBG(MDP,INI,1,"uncore-init pmcmask=0x%jx ucfri=%d", uncore_pmcmask, 1142 uncore_ucf_ri); 1143 1144 uncore_pcpu = malloc(sizeof(struct uncore_cpu **) * maxcpu, M_PMC, 1145 M_ZERO | M_WAITOK); 1146 1147 return (0); 1148} 1149 1150void 1151pmc_uncore_finalize(struct pmc_mdep *md) 1152{ 1153 PMCDBG(MDP,INI,1, "%s", "uncore-finalize"); 1154 1155 free(uncore_pcpu, M_PMC); 1156 uncore_pcpu = NULL; 1157} 1158