Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

/* -> /*- for license, minor formatting changes

Add new UltraSPARC-III VIS II instructions.

Fix IF_SEXT(val, 32). The constants need to have type long to
handle size > 16.

Add a support macro to convert the 5-bit packed register field of
a floating point instruction into a 6-bit register number for
double and quad arguments.
Make use of the new INSFPdq_RN macro where apporpriate; this
is required for correctly handling the "high" fp registers
(>= %f32).
Fix a number of bugs related to the handling of the high registers
which were caused by using __fpu_[gs]etreg() where __fpu_[gs]etreg64()
should be used (the former can only access the low, single-precision,
registers).

Submitted by: tmm

Add convenience macros to extract the cc0 and cc1 from format 2 and 3
instructions.

Adapt for used by upcoming fp emulation code.
Comment.

Submitted by: tmm

Add code to emulate unimplemented (non-fp) instructions and to fixup
unaligned accesses, and instr.h, which contrains definitions for the
sparc64 instruction set (partly from NetBSD).
Make use of some definitions from instr.h in db_disasm.c.