instr.h revision 86146
1/* 2 * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu 3 * Copyright (c) 1995 Paul Kranenburg 4 * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by David Miller. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp 33 * 34 * $FreeBSD: head/sys/sparc64/include/instr.h 86146 2001-11-06 20:13:44Z tmm $ 35 */ 36 37#ifndef _MACHINE_INSTR_H_ 38#define _MACHINE_INSTR_H_ 39 40/* 41 * Definitions for all instruction formats 42 */ 43#define IF_OP_SHIFT 30 44#define IF_OP_BITS 2 45#define IF_IMM_SHIFT 0 /* Immediate/Displacement */ 46 47/* 48 * Definitions for format 2 49 */ 50#define IF_F2_RD_SHIFT 25 51#define IF_F2_RD_BITS 5 52#define IF_F2_A_SHIFT 29 53#define IF_F2_A_BITS 1 54#define IF_F2_COND_SHIFT 25 55#define IF_F2_COND_BITS 4 56#define IF_F2_RCOND_SHIFT 25 57#define IF_F2_RCOND_BITS 3 58#define IF_F2_OP2_SHIFT 22 59#define IF_F2_OP2_BITS 3 60#define IF_F2_CC1_SHIFT 21 61#define IF_F2_CC1_BITS 1 62#define IF_F2_CC0_SHIFT 20 63#define IF_F2_CC0_BITS 1 64#define IF_F2_D16HI_SHIFT 20 65#define IF_F2_D16HI_BITS 2 66#define IF_F2_P_SHIFT 19 67#define IF_F2_P_BITS 1 68#define IF_F2_RS1_SHIFT 14 69#define IF_F2_RS1_BITS 5 70 71/* 72 * Definitions for format 3 73 */ 74#define IF_F3_OP3_SHIFT 19 75#define IF_F3_OP3_BITS 6 76#define IF_F3_RD_SHIFT IF_F2_RD_SHIFT 77#define IF_F3_RD_BITS IF_F2_RD_BITS 78#define IF_F3_FCN_SHIFT 25 79#define IF_F3_FCN_BITS 5 80#define IF_F3_CC1_SHIFT 26 81#define IF_F3_CC1_BITS 1 82#define IF_F3_CC0_SHIFT 25 83#define IF_F3_CC0_BITS 1 84#define IF_F3_RS1_SHIFT IF_F2_RS1_SHIFT 85#define IF_F3_RS1_BITS IF_F2_RS1_BITS 86#define IF_F3_I_SHIFT 13 87#define IF_F3_I_BITS 1 88#define IF_F3_X_SHIFT 12 89#define IF_F3_X_BITS 1 90#define IF_F3_RCOND_SHIFT 10 91#define IF_F3_RCOND_BITS 3 92#define IF_F3_IMM_ASI_SHIFT 5 93#define IF_F3_IMM_ASI_BITS 8 94#define IF_F3_OPF_SHIFT 5 95#define IF_F3_OPF_BITS 9 96#define IF_F3_CMASK_SHIFT 4 97#define IF_F3_CMASK_BITS 3 98#define IF_F3_RS2_SHIFT 0 99#define IF_F3_RS2_BITS 5 100#define IF_F3_SHCNT32_SHIFT 0 101#define IF_F3_SHCNT32_BITS 5 102#define IF_F3_SHCNT64_SHIFT 0 103#define IF_F3_SHCNT64_BITS 6 104 105/* 106 * Definitions for format 4 107 */ 108#define IF_F4_OP3_SHIFT IF_F3_OP3_SHIFT 109#define IF_F4_OP3_BITS IF_F3_OP3_BITS 110#define IF_F4_RD_SHIFT IF_F2_RD_SHIFT 111#define IF_F4_RD_BITS IF_F2_RD_BITS 112#define IF_F4_RS1_SHIFT IF_F2_RS1_SHIFT 113#define IF_F4_RS1_BITS IF_F2_RS1_BITS 114#define IF_F4_TCOND_SHIFT IF_F2_COND_SHIFT /* cond for Tcc */ 115#define IF_F4_TCOND_BITS IF_F2_COND_BITS 116#define IF_F4_CC2_SHIFT 18 117#define IF_F4_CC2_BITS 1 118#define IF_F4_COND_SHIFT 14 119#define IF_F4_COND_BITS 4 120#define IF_F4_I_SHIFT IF_F3_I_SHIFT 121#define IF_F4_I_BITS IF_F3_I_BITS 122#define IF_F4_OPF_CC_SHIFT 11 123#define IF_F4_OPF_CC_BITS 3 124#define IF_F4_CC1_SHIFT 12 125#define IF_F4_CC1_BITS 1 126#define IF_F4_CC0_SHIFT 11 127#define IF_F4_CC0_BITS 1 128#define IF_F4_RCOND_SHIFT IF_F3_RCOND_SHIFT 129#define IF_F4_RCOND_BITS IF_F3_RCOND_BITS 130#define IF_F4_OPF_LOW_SHIFT 5 131#define IF_F4_RS2_SHIFT IF_F3_RS2_SHIFT 132#define IF_F4_RS2_BITS IF_F3_RS2_BITS 133#define IF_F4_SW_TRAP_SHIFT 0 134#define IF_F4_SW_TRAP_BITS 7 135 136/* 137 * Macros to decode instructions 138 */ 139/* Extract a field */ 140#define IF_EXTRACT(x, s, w) (((x) >> (s)) & ((1 << (w)) - 1)) 141#define IF_DECODE(x, f) \ 142 IF_EXTRACT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 143 144/* Sign-extend a field of width W */ 145#define IF_SEXT(x, w) \ 146 (((x) & (1 << ((w) - 1))) != 0 ? (-1L - ((x) ^ ((1 << (w)) - 1))) : (x)) 147 148#if 0 149/* 150 * The following C variant is from db_disassemble.c, and surely faster, but it 151 * relies on behaviour that is undefined by the C standard (>> in conjunction 152 * with signed negative arguments). 153 */ 154#define IF_SEXT(v, w) ((((long long)(v)) << (64 - w)) >> (64 - w)) 155/* Assembler version of the above */ 156#define IF_SEXT(v, w) \ 157 { u_long t; ( __asm __volatile("sllx %1, %2, %0; srax %0, %2, %0" : 158 "=r" (t) : "r" (v) : "i" (64 - w)); t)} 159#endif 160 161/* All instruction formats */ 162#define IF_OP(i) IF_DECODE(i, OP) 163 164/* Instruction format 2 */ 165#define IF_F2_RD(i) IF_DECODE((i), F2_RD) 166#define IF_F2_A(i) IF_DECODE((i), F2_A) 167#define IF_F2_COND(i) IF_DECODE((i), F2_COND) 168#define IF_F2_RCOND(i) IF_DECODE((i), F2_RCOND) 169#define IF_F2_OP2(i) IF_DECODE((i), F2_OP2) 170#define IF_F2_CC1(i) IF_DECODE((i), F2_CC1) 171#define IF_F2_CC0(i) IF_DECODE((i), F2_CC0) 172#define IF_F2_D16HI(i) IF_DECODE((i), F2_D16HI) 173#define IF_F2_P(i) IF_DECODE((i), F2_P) 174#define IF_F2_RS1(i) IF_DECODE((i), F2_RS1) 175 176/* Instruction format 3 */ 177#define IF_F3_OP3(i) IF_DECODE((i), F3_OP3) 178#define IF_F3_RD(i) IF_F2_RD((i)) 179#define IF_F3_FCN(i) IF_DECODE((i), F3_FCN) 180#define IF_F3_CC1(i) IF_DECODE((i), F3_CC1) 181#define IF_F3_CC0(i) IF_DECODE((i), F3_CC0) 182#define IF_F3_RS1(i) IF_F2_RS1((i)) 183#define IF_F3_I(i) IF_DECODE((i), F3_I) 184#define IF_F3_X(i) IF_DECODE((i), F3_X) 185#define IF_F3_RCOND(i) IF_DECODE((i), F3_RCOND) 186#define IF_F3_IMM_ASI(i) IF_DECODE((i), F3_IMM_ASI) 187#define IF_F3_OPF(i) IF_DECODE((i), F3_OPF) 188#define IF_F3_CMASK(i) IF_DECODE((i), F3_CMASK) 189#define IF_F3_RS2(i) IF_DECODE((i), F3_RS2) 190#define IF_F3_SHCNT32(i) IF_DECODE((i), F3_SHCNT32) 191#define IF_F3_SHCNT64(i) IF_DECODE((i), F3_SHCNT64) 192 193/* Instruction format 4 */ 194#define IF_F4_OP3(i) IF_F3_OP3((i)) 195#define IF_F4_RD(i) IF_F3_RD((i)) 196#define IF_F4_TCOND(i) IF_DECODE((i), F4_TCOND) 197#define IF_F4_RS1(i) IF_F3_RS1((i)) 198#define IF_F4_CC2(i) IF_DECODE((i), F4_CC2) 199#define IF_F4_COND(i) IF_DECODE((i), F4_COND) 200#define IF_F4_I(i) IF_F3_I((i)) 201#define IF_F4_OPF_CC(i) IF_DECODE((i), F4_OPF_CC) 202#define IF_F4_RCOND(i) IF_F3_RCOND((i)) 203#define IF_F4_OPF_LOW(i, w) IF_EXTRACT((i), IF_F4_OPF_LOW_SHIFT, (w)) 204#define IF_F4_RS2(i) IF_F3_RS2((i)) 205#define IF_F4_SW_TRAP(i) IF_DECODE((i), F4_SW_TRAP) 206 207/* Extract an immediate from an instruction, with an without sign extension */ 208#define IF_IMM(i, w) IF_EXTRACT((i), IF_IMM_SHIFT, (w)) 209#define IF_SIMM(i, w) ({ u_long b = (w), x = IF_IMM((i), b); IF_SEXT((x), b); }) 210 211/* 212 * Macros to encode instructions 213 */ 214#define IF_INSERT(x, s, w) (((x) & ((1 << (w)) - 1)) << (s)) 215#define IF_ENCODE(x, f) \ 216 IF_INSERT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 217 218/* All instruction formats */ 219#define EIF_OP(x) IF_ENCODE((x), OP) 220 221/* Instruction format 2 */ 222#define EIF_F2_RD(x) IF_ENCODE((x), F2_RD) 223#define EIF_F2_A(x) IF_ENCODE((x), F2_A) 224#define EIF_F2_COND(x) IF_ENCODE((x), F2_COND) 225#define EIF_F2_RCOND(x) IF_ENCODE((x), F2_RCOND) 226#define EIF_F2_OP2(x) IF_ENCODE((x), F2_OP2) 227#define EIF_F2_CC1(x) IF_ENCODE((x), F2_CC1) 228#define EIF_F2_CC0(x) IF_ENCODE((x), F2_CC0) 229#define EIF_F2_D16HI(x) IF_ENCODE((x), F2_D16HI) 230#define EIF_F2_P(x) IF_ENCODE((x), F2_P) 231#define EIF_F2_RS1(x) IF_ENCODE((x), F2_RS1) 232 233/* Instruction format 3 */ 234#define EIF_F3_OP3(x) IF_ENCODE((x), F3_OP3) 235#define EIF_F3_RD(x) EIF_F2_RD((x)) 236#define EIF_F3_FCN(x) IF_ENCODE((x), F3_FCN) 237#define EIF_F3_CC1(x) IF_ENCODE((x), F3_CC1) 238#define EIF_F3_CC0(x) IF_ENCODE((x), F3_CC0) 239#define EIF_F3_RS1(x) EIF_F2_RS1((x)) 240#define EIF_F3_I(x) IF_ENCODE((x), F3_I) 241#define EIF_F3_X(x) IF_ENCODE((x), F3_X) 242#define EIF_F3_RCOND(x) IF_ENCODE((x), F3_RCOND) 243#define EIF_F3_IMM_ASI(x) IF_ENCODE((x), F3_IMM_ASI) 244#define EIF_F3_OPF(x) IF_ENCODE((x), F3_OPF) 245#define EIF_F3_CMASK(x) IF_ENCODE((x), F3_CMASK) 246#define EIF_F3_RS2(x) IF_ENCODE((x), F3_RS2) 247#define EIF_F3_SHCNT32(x) IF_ENCODE((x), F3_SHCNT32) 248#define EIF_F3_SHCNT64(x) IF_ENCODE((x), F3_SHCNT64) 249 250/* Instruction format 4 */ 251#define EIF_F4_OP3(x) EIF_F3_OP3((x)) 252#define EIF_F4_RD(x) EIF_F2_RD((x)) 253#define EIF_F4_TCOND(x) IF_ENCODE((x), F4_TCOND) 254#define EIF_F4_RS1(x) EIF_F2_RS1((x)) 255#define EIF_F4_CC2(x) IF_ENCODE((x), F4_CC2) 256#define EIF_F4_COND(x) IF_ENCODE((x), F4_COND) 257#define EIF_F4_I(x) EIF_F3_I((x)) 258#define EIF_F4_OPF_CC(x) IF_ENCODE((x), F4_OPF_CC) 259#define EIF_F4_RCOND(x) EIF_F3_RCOND((x)) 260#define EIF_F4_OPF_LOW(i, w) IF_INSERT((x), IF_F4_OPF_CC_SHIFT, (w)) 261#define EIF_F4_RS2(x) EIF_F3_RS2((x)) 262#define EIF_F4_SW_TRAP(x) IF_ENCODE((x), F4_SW_TRAP) 263 264/* Immediates */ 265#define EIF_IMM(x, w) IF_INSERT((x), IF_IMM_SHIFT, (w)) 266#define EIF_SIMM(x, w) IF_EIMM((x), (w)) 267 268/* 269 * OP field values (specifying the instruction format) 270 */ 271#define IOP_FORM2 0x00 /* Format 2: sethi, branches */ 272#define IOP_CALL 0x01 /* Format 1: call */ 273#define IOP_MISC 0x02 /* Format 3 or 4: arith & misc */ 274#define IOP_LDST 0x03 /* Format 4: loads and stores */ 275 276/* 277 * OP2/OP3 values (specifying the actual instruction) 278 */ 279/* OP2 values for format 2 (OP = 0) */ 280#define INS0_ILLTRAP 0x00 281#define INS0_BPcc 0x01 282#define INS0_Bicc 0x02 283#define INS0_BPr 0x03 284#define INS0_SETHI 0x04 /* with rd = 0 and imm22 = 0, nop */ 285#define INS0_FBPfcc 0x05 286#define INS0_FBfcc 0x06 287/* undefined 0x07 */ 288 289/* OP3 values for Format 3 and 4 (OP = 2) */ 290#define INS2_ADD 0x00 291#define INS2_AND 0x01 292#define INS2_OR 0x02 293#define INS2_XOR 0x03 294#define INS2_SUB 0x04 295#define INS2_ANDN 0x05 296#define INS2_ORN 0x06 297#define INS2_XNOR 0x07 298#define INS2_ADDC 0x08 299#define INS2_MULX 0x09 300#define INS2_UMUL 0x0a 301#define INS2_SMUL 0x0b 302#define INS2_SUBC 0x0c 303#define INS2_UDIVX 0x0d 304#define INS2_UDIV 0x0e 305#define INS2_SDIV 0x0f 306#define INS2_ADDcc 0x10 307#define INS2_ANDcc 0x11 308#define INS2_ORcc 0x12 309#define INS2_XORcc 0x13 310#define INS2_SUBcc 0x14 311#define INS2_ANDNcc 0x15 312#define INS2_ORNcc 0x16 313#define INS2_XNORcc 0x17 314#define INS2_ADDCcc 0x18 315/* undefined 0x19 */ 316#define INS2_UMULcc 0x1a 317#define INS2_SMULcc 0x1b 318#define INS2_SUBCcc 0x1c 319/* undefined 0x1d */ 320#define INS2_UDIVcc 0x1e 321#define INS2_SDIVcc 0x1f 322#define INS2_TADDcc 0x20 323#define INS2_TSUBcc 0x21 324#define INS2_TADDccTV 0x22 325#define INS2_TSUBccTV 0x23 326#define INS2_MULScc 0x24 327#define INS2_SSL 0x25 /* SLLX when IF_X(i) == 1 */ 328#define INS2_SRL 0x26 /* SRLX when IF_X(i) == 1 */ 329#define INS2_SRA 0x27 /* SRAX when IF_X(i) == 1 */ 330#define INS2_RD 0x28 /* and MEMBAR, STBAR */ 331/* undefined 0x29 */ 332#define INS2_RDPR 0x2a 333#define INS2_FLUSHW 0x2b 334#define INS2_MOVcc 0x2c 335#define INS2_SDIVX 0x2d 336#define INS2_POPC 0x2e /* undefined if IF_RS1(i) != 0 */ 337#define INS2_MOVr 0x2f 338#define INS2_WR 0x30 /* and SIR */ 339#define INS2_SV_RSTR 0x31 /* saved, restored */ 340#define INS2_WRPR 0x32 341/* undefined 0x33 */ 342#define INS2_FPop1 0x34 /* further encoded in opf field */ 343#define INS2_FPop2 0x35 /* further encoded in opf field */ 344#define INS2_IMPLDEP1 0x36 345#define INS2_IMPLDEP2 0x37 346#define INS2_JMPL 0x38 347#define INS2_RETURN 0x39 348#define INS2_Tcc 0x3a 349#define INS2_FLUSH 0x3b 350#define INS2_SAVE 0x3c 351#define INS2_RESTORE 0x3d 352#define INS2_DONE_RETR 0x3e /* done, retry */ 353/* undefined 0x3f */ 354 355/* OP3 values for format 3 (OP = 3) */ 356#define INS3_LDUW 0x00 357#define INS3_LDUB 0x01 358#define INS3_LDUH 0x02 359#define INS3_LDD 0x03 360#define INS3_STW 0x04 361#define INS3_STB 0x05 362#define INS3_STH 0x06 363#define INS3_STD 0x07 364#define INS3_LDSW 0x08 365#define INS3_LDSB 0x09 366#define INS3_LDSH 0x0a 367#define INS3_LDX 0x0b 368/* undefined 0x0c */ 369#define INS3_LDSTUB 0x0d 370#define INS3_STX 0x0e 371#define INS3_SWAP 0x0f 372#define INS3_LDUWA 0x10 373#define INS3_LDUBA 0x11 374#define INS3_LDUHA 0x12 375#define INS3_LDDA 0x13 376#define INS3_STWA 0x14 377#define INS3_STBA 0x15 378#define INS3_STHA 0x16 379#define INS3_STDA 0x17 380#define INS3_LDSWA 0x18 381#define INS3_LDSBA 0x19 382#define INS3_LDSHA 0x1a 383#define INS3_LDXA 0x1b 384/* undefined 0x1c */ 385#define INS3_LDSTUBA 0x1d 386#define INS3_STXA 0x1e 387#define INS3_SWAPA 0x1f 388#define INS3_LDF 0x20 389#define INS3_LDFSR 0x21 /* and LDXFSR */ 390#define INS3_LDQF 0x22 391#define INS3_LDDF 0x23 392#define INS3_STF 0x24 393#define INS3_STFSR 0x25 /* and STXFSR */ 394#define INS3_STQF 0x26 395#define INS3_STDF 0x27 396/* undefined 0x28 - 0x2c */ 397#define INS3_PREFETCH 0x2d 398/* undefined 0x2e - 0x2f */ 399#define INS3_LDFA 0x30 400/* undefined 0x31 */ 401#define INS3_LDQFA 0x32 402#define INS3_LDDFA 0x33 403#define INS3_STFA 0x34 404/* undefined 0x35 */ 405#define INS3_STQFA 0x36 406#define INS3_STDFA 0x37 407/* undefined 0x38 - 0x3b */ 408#define INS3_CASA 0x39 409#define INS3_PREFETCHA 0x3a 410#define INS3_CASXA 0x3b 411 412/* 413 * OPF values (floating point instructions, IMPLDEP) 414 */ 415/* FPop1 */ 416#define INSFP1_FMOVs 0x001 417#define INSFP1_FMOVd 0x002 418#define INSFP1_FMOVq 0x003 419#define INSFP1_FNEGs 0x005 420#define INSFP1_FNEGd 0x006 421#define INSFP1_FNEGq 0x007 422#define INSFP1_FABSs 0x009 423#define INSFP1_FABSd 0x00a 424#define INSFP1_FABSq 0x00b 425#define INSFP1_FSQRTs 0x029 426#define INSFP1_FSQRTd 0x02a 427#define INSFP1_FSQRTq 0x02b 428#define INSFP1_FADDs 0x041 429#define INSFP1_FADDd 0x042 430#define INSFP1_FADDq 0x043 431#define INSFP1_FSUBs 0x045 432#define INSFP1_FSUBd 0x046 433#define INSFP1_FSUBq 0x047 434#define INSFP1_FMULs 0x049 435#define INSFP1_FMULd 0x04a 436#define INSFP1_FMULq 0x04b 437#define INSFP1_FDIVs 0x04d 438#define INSFP1_FDIVd 0x04e 439#define INSFP1_FDIVq 0x04f 440#define INSFP1_FsMULd 0x069 441#define INSFP1_FdMULq 0x06e 442#define INSFP1_FsTOx 0x081 443#define INSFP1_FdTOx 0x082 444#define INSFP1_FqTOx 0x083 445#define INSFP1_FxTOs 0x084 446#define INSFP1_FxTOd 0x088 447#define INSFP1_FxTOq 0x08c 448#define INSFP1_FiTOs 0x0c4 449#define INSFP1_FdTOs 0x0c6 450#define INSFP1_FqTOs 0x0c7 451#define INSFP1_FiTOd 0x0c8 452#define INSFP1_FsTOd 0x0c9 453#define INSFP1_FqTOd 0x0cb 454#define INSFP1_FiTOq 0x0cc 455#define INSFP1_FsTOq 0x0cd 456#define INSFP1_FdTOq 0x0ce 457 458/* FPop2 */ 459#define INSFP2_FMOV_CCMUL 0x40 460/* use the IFCC_* constants for cc */ 461#define INSFP2_FMOV_CC(i, cc) (i + (cc) * INSFP2_FMOV_CCMUL) 462#define INSFP2_FMOVs(cc) INSFP2_FMOV_CC(0x01, (cc)) 463#define INSFP2_FMOVd(cc) INSFP2_FMOV_CC(0x02, (cc)) 464#define INSFP2_FMOVq(cc) INSFP2_FMOV_CC(0x03, (cc)) 465 466/* use the IRCOND_* constants for rc */ 467#define INSFP2_FMOV_RCMUL 0x20 468#define INSFP2_FMOV_RC(i, rc) (i + (rc) * INSFP2_FMOV_RCMUL) 469#define INSFP2_FMOVRsZ(rc) INSFP2_FMOV_RC(0x05, (rc)) 470#define INSFP2_FMOVRdZ(rc) INSFP2_FMOV_RC(0x06, (rc)) 471#define INSFP2_FMOVRqZ(rc) INSFP2_FMOV_RC(0x07, (rc)) 472#define INSFP2_FCMPs 0x051 473#define INSFP2_FCMPd 0x052 474#define INSFP2_FCMPq 0x053 475#define INSFP2_FCMPEs 0x055 476#define INSFP2_FCMPEd 0x056 477#define INSFP2_FCMPEq 0x057 478 479/* IMPLDEP1 for Sun UltraSparc */ 480#define IIDP1_EDGE8 0x00 481#define IIDP1_EDGE8L 0x02 482#define IIDP1_EDGE16 0x04 483#define IIDP1_EDGE16L 0x06 484#define IIDP1_EDGE32 0x08 485#define IIDP1_EDGE32L 0x0a 486#define IIDP1_ARRAY8 0x10 487#define IIDP1_ARRAY16 0x12 488#define IIDP1_ARRAY32 0x14 489#define IIDP1_ALIGNADDRESS 0x18 490#define IIDP1_ALIGNADDRESS_L 0x1a 491#define IIDP1_FCMPLE16 0x20 492#define IIDP1_FCMPNE16 0x22 493#define IIDP1_FCMPLE32 0x24 494#define IIDP1_FCMPNE32 0x26 495#define IIDP1_FCMPGT16 0x28 496#define IIDP1_FCMPEQ16 0x2a 497#define IIDP1_FCMPGT32 0x2c 498#define IIDP1_FCMPEQ32 0x2e 499#define IIDP1_FMUL8x16 0x31 500#define IIDP1_FMUL8x16AU 0x33 501#define IIDP1_FMUL8X16AL 0x35 502#define IIDP1_FMUL8SUx16 0x36 503#define IIDP1_FMUL8ULx16 0x37 504#define IIDP1_FMULD8SUx16 0x38 505#define IIDP1_FMULD8ULx16 0x39 506#define IIDP1_FPACK32 0x3a 507#define IIDP1_FPACK16 0x3b 508#define IIDP1_FPACKFIX 0x3d 509#define IIDP1_PDIST 0x3e 510#define IIDP1_FALIGNDATA 0x48 511#define IIDP1_FPMERGE 0x4b 512#define IIDP1_FEXPAND 0x4d 513#define IIDP1_FPADD16 0x50 514#define IIDP1_FPADD16S 0x51 515#define IIDP1_FPADD32 0x52 516#define IIDP1_FPADD32S 0x53 517#define IIDP1_SUB16 0x54 518#define IIDP1_SUB16S 0x55 519#define IIDP1_SUB32 0x56 520#define IIDP1_SUB32S 0x57 521#define IIDP1_FZERO 0x60 522#define IIDP1_FZEROS 0x61 523#define IIDP1_FNOR 0x62 524#define IIDP1_FNORS 0x63 525#define IIDP1_FANDNOT2 0x64 526#define IIDP1_FANDNOT2S 0x65 527#define IIDP1_NOT2 0x66 528#define IIDP1_NOT2S 0x67 529#define IIDP1_FANDNOT1 0x68 530#define IIDP1_FANDNOT1S 0x69 531#define IIDP1_FNOT1 0x6a 532#define IIDP1_FNOT1S 0x6b 533#define IIDP1_FXOR 0x6c 534#define IIDP1_FXORS 0x6d 535#define IIDP1_FNAND 0x6e 536#define IIDP1_FNANDS 0x6f 537#define IIDP1_FAND 0x70 538#define IIDP1_FANDS 0x71 539#define IIDP1_FXNOR 0x72 540#define IIDP1_FXNORS 0x73 541#define IIDP1_FSRC1 0x74 542#define IIDP1_FSRC1S 0x75 543#define IIDP1_FORNOT2 0x76 544#define IIDP1_FORNOT2S 0x77 545#define IIDP1_FSRC2 0x78 546#define IIDP1_FSRC2S 0x79 547#define IIDP1_FORNOT1 0x7a 548#define IIDP1_FORNOT1S 0x7b 549#define IIDP1_FOR 0x7c 550#define IIDP1_FORS 0x7d 551#define IIDP1_FONE 0x7e 552#define IIDP1_FONES 0x7f 553#define IIDP1_SHUTDOWN 0x80 554 555/* 556 * Instruction modifiers 557 */ 558/* cond values for integer ccr's */ 559#define IICOND_N 0x00 560#define IICOND_E 0x01 561#define IICOND_LE 0x02 562#define IICOND_L 0x03 563#define IICOND_LEU 0x04 564#define IICOND_CS 0x05 565#define IICOND_NEG 0x06 566#define IICOND_VS 0x07 567#define IICOND_A 0x08 568#define IICOND_NE 0x09 569#define IICOND_G 0x0a 570#define IICOND_GE 0x0b 571#define IICOND_GU 0x0c 572#define IICOND_CC 0x0d 573#define IICOND_POS 0x0e 574#define IICOND_VC 0x0f 575 576/* cond values for fp ccr's */ 577#define IFCOND_N 0x00 578#define IFCOND_NE 0x01 579#define IFCOND_LG 0x02 580#define IFCOND_UL 0x03 581#define IFCOND_L 0x04 582#define IFCOND_UG 0x05 583#define IFCOND_G 0x06 584#define IFCOND_U 0x07 585#define IFCOND_A 0x08 586#define IFCOND_E 0x09 587#define IFCOND_UE 0x0a 588#define IFCOND_GE 0x0b 589#define IFCOND_UGE 0x0c 590#define IFCOND_LE 0x0d 591#define IFCOND_ULE 0x0e 592#define IFCOND_O 0x0f 593 594/* rcond values for BPr, MOVr, FMOVr */ 595#define IRCOND_RZ 0x01 596#define IRCOND_LEZ 0x02 597#define IRCOND_LZ 0x03 598#define IRCOND_NZ 0x05 599#define IRCOND_GZ 0x06 600#define IRCOND_GEZ 0x07 601 602/* cc values for MOVcc and FMOVcc */ 603#define IFCC_ICC 0x04 604#define IFCC_XCC 0x06 605/* if true, the lower 2 bits are the fcc number */ 606#define IFCC_FCC(c) (((c) & 4) == 0) 607 608/* cc values for BPc and Tcc */ 609#define IBCC_ICC 0x00 610#define IBCC_XCC 0x02 611 612/* 613 * Integer registers 614 */ 615#define IREG_G0 0x00 616#define IREG_O0 0x08 617#define IREG_L0 0x10 618#define IREQ_I0 0x18 619 620#endif /* !_MACHINE_INSTR_H_ */ 621