instr.h revision 88663
11590Srgrimes/* 21590Srgrimes * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu 31590Srgrimes * Copyright (c) 1995 Paul Kranenburg 41590Srgrimes * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org> 51590Srgrimes * All rights reserved. 61590Srgrimes * 71590Srgrimes * Redistribution and use in source and binary forms, with or without 81590Srgrimes * modification, are permitted provided that the following conditions 91590Srgrimes * are met: 101590Srgrimes * 1. Redistributions of source code must retain the above copyright 111590Srgrimes * notice, this list of conditions and the following disclaimer. 121590Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 131590Srgrimes * notice, this list of conditions and the following disclaimer in the 141590Srgrimes * documentation and/or other materials provided with the distribution. 151590Srgrimes * 3. All advertising materials mentioning features or use of this software 161590Srgrimes * must display the following acknowledgement: 171590Srgrimes * This product includes software developed by David Miller. 181590Srgrimes * 4. The name of the author may not be used to endorse or promote products 191590Srgrimes * derived from this software without specific prior written permission 201590Srgrimes * 211590Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 221590Srgrimes * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 231590Srgrimes * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 241590Srgrimes * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 251590Srgrimes * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 261590Srgrimes * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 271590Srgrimes * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 281590Srgrimes * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 291590Srgrimes * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 301590Srgrimes * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 311590Srgrimes * 321590Srgrimes * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp 331590Srgrimes * 341590Srgrimes * $FreeBSD: head/sys/sparc64/include/instr.h 88663 2001-12-29 08:55:56Z jake $ 3527315Scharnier */ 361590Srgrimes 3727315Scharnier#ifndef _MACHINE_INSTR_H_ 3827315Scharnier#define _MACHINE_INSTR_H_ 3930921Sache 401590Srgrimes/* 411590Srgrimes * Definitions for all instruction formats 421590Srgrimes */ 431590Srgrimes#define IF_OP_SHIFT 30 4427315Scharnier#define IF_OP_BITS 2 451590Srgrimes#define IF_IMM_SHIFT 0 /* Immediate/Displacement */ 461590Srgrimes 471590Srgrimes/* 481590Srgrimes * Definitions for format 2 491590Srgrimes */ 501590Srgrimes#define IF_F2_RD_SHIFT 25 511590Srgrimes#define IF_F2_RD_BITS 5 521590Srgrimes#define IF_F2_A_SHIFT 29 531590Srgrimes#define IF_F2_A_BITS 1 541590Srgrimes#define IF_F2_COND_SHIFT 25 551590Srgrimes#define IF_F2_COND_BITS 4 561590Srgrimes#define IF_F2_RCOND_SHIFT 25 571590Srgrimes#define IF_F2_RCOND_BITS 3 5830921Sache#define IF_F2_OP2_SHIFT 22 591590Srgrimes#define IF_F2_OP2_BITS 3 601590Srgrimes#define IF_F2_CC1_SHIFT 21 611590Srgrimes#define IF_F2_CC1_BITS 1 621590Srgrimes#define IF_F2_CC0_SHIFT 20 631590Srgrimes#define IF_F2_CC0_BITS 1 6427315Scharnier#define IF_F2_D16HI_SHIFT 20 651590Srgrimes#define IF_F2_D16HI_BITS 2 661590Srgrimes#define IF_F2_P_SHIFT 19 6727315Scharnier#define IF_F2_P_BITS 1 681590Srgrimes#define IF_F2_RS1_SHIFT 14 691590Srgrimes#define IF_F2_RS1_BITS 5 701590Srgrimes 711590Srgrimes/* 721590Srgrimes * Definitions for format 3 731590Srgrimes */ 741590Srgrimes#define IF_F3_OP3_SHIFT 19 751590Srgrimes#define IF_F3_OP3_BITS 6 761590Srgrimes#define IF_F3_RD_SHIFT IF_F2_RD_SHIFT 771590Srgrimes#define IF_F3_RD_BITS IF_F2_RD_BITS 781590Srgrimes#define IF_F3_FCN_SHIFT 25 791590Srgrimes#define IF_F3_FCN_BITS 5 801590Srgrimes#define IF_F3_CC1_SHIFT 26 811590Srgrimes#define IF_F3_CC1_BITS 1 821590Srgrimes#define IF_F3_CC0_SHIFT 25 831590Srgrimes#define IF_F3_CC0_BITS 1 8430921Sache#define IF_F3_RS1_SHIFT IF_F2_RS1_SHIFT 851590Srgrimes#define IF_F3_RS1_BITS IF_F2_RS1_BITS 861590Srgrimes#define IF_F3_I_SHIFT 13 871590Srgrimes#define IF_F3_I_BITS 1 881590Srgrimes#define IF_F3_X_SHIFT 12 891590Srgrimes#define IF_F3_X_BITS 1 901590Srgrimes#define IF_F3_RCOND_SHIFT 10 911590Srgrimes#define IF_F3_RCOND_BITS 3 921590Srgrimes#define IF_F3_IMM_ASI_SHIFT 5 931590Srgrimes#define IF_F3_IMM_ASI_BITS 8 941590Srgrimes#define IF_F3_OPF_SHIFT 5 951590Srgrimes#define IF_F3_OPF_BITS 9 961590Srgrimes#define IF_F3_CMASK_SHIFT 4 971590Srgrimes#define IF_F3_CMASK_BITS 3 981590Srgrimes#define IF_F3_RS2_SHIFT 0 991590Srgrimes#define IF_F3_RS2_BITS 5 1001590Srgrimes#define IF_F3_SHCNT32_SHIFT 0 1011590Srgrimes#define IF_F3_SHCNT32_BITS 5 1021590Srgrimes#define IF_F3_SHCNT64_SHIFT 0 1031590Srgrimes#define IF_F3_SHCNT64_BITS 6 1041590Srgrimes 1051590Srgrimes/* 1061590Srgrimes * Definitions for format 4 1071590Srgrimes */ 1081590Srgrimes#define IF_F4_OP3_SHIFT IF_F3_OP3_SHIFT 1091590Srgrimes#define IF_F4_OP3_BITS IF_F3_OP3_BITS 1101590Srgrimes#define IF_F4_RD_SHIFT IF_F2_RD_SHIFT 1111590Srgrimes#define IF_F4_RD_BITS IF_F2_RD_BITS 1121590Srgrimes#define IF_F4_RS1_SHIFT IF_F2_RS1_SHIFT 1131590Srgrimes#define IF_F4_RS1_BITS IF_F2_RS1_BITS 1141590Srgrimes#define IF_F4_TCOND_SHIFT IF_F2_COND_SHIFT /* cond for Tcc */ 1151590Srgrimes#define IF_F4_TCOND_BITS IF_F2_COND_BITS 1161590Srgrimes#define IF_F4_CC2_SHIFT 18 1171590Srgrimes#define IF_F4_CC2_BITS 1 1181590Srgrimes#define IF_F4_COND_SHIFT 14 1191590Srgrimes#define IF_F4_COND_BITS 4 1201590Srgrimes#define IF_F4_I_SHIFT IF_F3_I_SHIFT 1211590Srgrimes#define IF_F4_I_BITS IF_F3_I_BITS 1221590Srgrimes#define IF_F4_OPF_CC_SHIFT 11 1231590Srgrimes#define IF_F4_OPF_CC_BITS 3 1241590Srgrimes#define IF_F4_CC1_SHIFT 12 1251590Srgrimes#define IF_F4_CC1_BITS 1 1261590Srgrimes#define IF_F4_CC0_SHIFT 11 1271590Srgrimes#define IF_F4_CC0_BITS 1 1281590Srgrimes#define IF_F4_RCOND_SHIFT IF_F3_RCOND_SHIFT 1291590Srgrimes#define IF_F4_RCOND_BITS IF_F3_RCOND_BITS 1301590Srgrimes#define IF_F4_OPF_LOW_SHIFT 5 1311590Srgrimes#define IF_F4_RS2_SHIFT IF_F3_RS2_SHIFT 1321590Srgrimes#define IF_F4_RS2_BITS IF_F3_RS2_BITS 1331590Srgrimes#define IF_F4_SW_TRAP_SHIFT 0 1341590Srgrimes#define IF_F4_SW_TRAP_BITS 7 1351590Srgrimes 1361590Srgrimes/* 1371590Srgrimes * Macros to decode instructions 1381590Srgrimes */ 1391590Srgrimes/* Extract a field */ 1401590Srgrimes#define IF_MASK(s, w) (((1 << (w)) - 1) << (s)) 1411590Srgrimes#define IF_EXTRACT(x, s, w) (((x) & IF_MASK((s), (w))) >> (s)) 1421590Srgrimes#define IF_DECODE(x, f) \ 1431590Srgrimes IF_EXTRACT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 1441590Srgrimes 1451590Srgrimes/* Sign-extend a field of width W */ 1461590Srgrimes#define IF_SEXT(x, w) \ 1471590Srgrimes (((x) & (1 << ((w) - 1))) != 0 ? (-1L - ((x) ^ ((1 << (w)) - 1))) : (x)) 1481590Srgrimes 1491590Srgrimes#if 0 1501590Srgrimes/* 1511590Srgrimes * The following C variant is from db_disassemble.c, and surely faster, but it 1521590Srgrimes * relies on behaviour that is undefined by the C standard (>> in conjunction 1531590Srgrimes * with signed negative arguments). 1541590Srgrimes */ 1551590Srgrimes#define IF_SEXT(v, w) ((((long long)(v)) << (64 - w)) >> (64 - w)) 1561590Srgrimes/* Assembler version of the above */ 1571590Srgrimes#define IF_SEXT(v, w) \ 1581590Srgrimes { u_long t; ( __asm __volatile("sllx %1, %2, %0; srax %0, %2, %0" : 1591590Srgrimes "=r" (t) : "r" (v) : "i" (64 - w)); t)} 16030921Sache#endif 1611590Srgrimes 1621590Srgrimes/* All instruction formats */ 1631590Srgrimes#define IF_OP(i) IF_DECODE(i, OP) 1641590Srgrimes 1651590Srgrimes/* Instruction format 2 */ 1661590Srgrimes#define IF_F2_RD(i) IF_DECODE((i), F2_RD) 1671590Srgrimes#define IF_F2_A(i) IF_DECODE((i), F2_A) 1681590Srgrimes#define IF_F2_COND(i) IF_DECODE((i), F2_COND) 1691590Srgrimes#define IF_F2_RCOND(i) IF_DECODE((i), F2_RCOND) 1701590Srgrimes#define IF_F2_OP2(i) IF_DECODE((i), F2_OP2) 1711590Srgrimes#define IF_F2_CC1(i) IF_DECODE((i), F2_CC1) 1721590Srgrimes#define IF_F2_CC0(i) IF_DECODE((i), F2_CC0) 1731590Srgrimes#define IF_F2_D16HI(i) IF_DECODE((i), F2_D16HI) 1741590Srgrimes#define IF_F2_P(i) IF_DECODE((i), F2_P) 1751590Srgrimes#define IF_F2_RS1(i) IF_DECODE((i), F2_RS1) 1761590Srgrimes 1771590Srgrimes/* Instruction format 3 */ 1781590Srgrimes#define IF_F3_OP3(i) IF_DECODE((i), F3_OP3) 1791590Srgrimes#define IF_F3_RD(i) IF_F2_RD((i)) 1801590Srgrimes#define IF_F3_FCN(i) IF_DECODE((i), F3_FCN) 1811590Srgrimes#define IF_F3_CC1(i) IF_DECODE((i), F3_CC1) 1821590Srgrimes#define IF_F3_CC0(i) IF_DECODE((i), F3_CC0) 1831590Srgrimes#define IF_F3_RS1(i) IF_F2_RS1((i)) 1841590Srgrimes#define IF_F3_I(i) IF_DECODE((i), F3_I) 1851590Srgrimes#define IF_F3_X(i) IF_DECODE((i), F3_X) 1861590Srgrimes#define IF_F3_RCOND(i) IF_DECODE((i), F3_RCOND) 1871590Srgrimes#define IF_F3_IMM_ASI(i) IF_DECODE((i), F3_IMM_ASI) 1881590Srgrimes#define IF_F3_OPF(i) IF_DECODE((i), F3_OPF) 1891590Srgrimes#define IF_F3_CMASK(i) IF_DECODE((i), F3_CMASK) 1901590Srgrimes#define IF_F3_RS2(i) IF_DECODE((i), F3_RS2) 1911590Srgrimes#define IF_F3_SHCNT32(i) IF_DECODE((i), F3_SHCNT32) 1921590Srgrimes#define IF_F3_SHCNT64(i) IF_DECODE((i), F3_SHCNT64) 1931590Srgrimes 1941590Srgrimes/* Instruction format 4 */ 1951590Srgrimes#define IF_F4_OP3(i) IF_F3_OP3((i)) 1961590Srgrimes#define IF_F4_RD(i) IF_F3_RD((i)) 1971590Srgrimes#define IF_F4_TCOND(i) IF_DECODE((i), F4_TCOND) 1981590Srgrimes#define IF_F4_RS1(i) IF_F3_RS1((i)) 1991590Srgrimes#define IF_F4_CC2(i) IF_DECODE((i), F4_CC2) 2001590Srgrimes#define IF_F4_COND(i) IF_DECODE((i), F4_COND) 2011590Srgrimes#define IF_F4_I(i) IF_F3_I((i)) 2021590Srgrimes#define IF_F4_OPF_CC(i) IF_DECODE((i), F4_OPF_CC) 2031590Srgrimes#define IF_F4_RCOND(i) IF_F3_RCOND((i)) 2041590Srgrimes#define IF_F4_OPF_LOW(i, w) IF_EXTRACT((i), IF_F4_OPF_LOW_SHIFT, (w)) 2051590Srgrimes#define IF_F4_RS2(i) IF_F3_RS2((i)) 2061590Srgrimes#define IF_F4_SW_TRAP(i) IF_DECODE((i), F4_SW_TRAP) 2071590Srgrimes 2081590Srgrimes/* Extract an immediate from an instruction, with an without sign extension */ 2091590Srgrimes#define IF_IMM(i, w) IF_EXTRACT((i), IF_IMM_SHIFT, (w)) 2101590Srgrimes#define IF_SIMM(i, w) ({ u_long b = (w), x = IF_IMM((i), b); IF_SEXT((x), b); }) 2111590Srgrimes 2121590Srgrimes/* 2131590Srgrimes * Macros to encode instructions 2141590Srgrimes */ 21530921Sache#define IF_INSERT(x, s, w) (((x) & ((1 << (w)) - 1)) << (s)) 21630921Sache#define IF_ENCODE(x, f) \ 2171590Srgrimes IF_INSERT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 2181590Srgrimes 2191590Srgrimes/* All instruction formats */ 2201590Srgrimes#define EIF_OP(x) IF_ENCODE((x), OP) 2211590Srgrimes 2221590Srgrimes/* Instruction format 2 */ 2231590Srgrimes#define EIF_F2_RD(x) IF_ENCODE((x), F2_RD) 2241590Srgrimes#define EIF_F2_A(x) IF_ENCODE((x), F2_A) 2251590Srgrimes#define EIF_F2_COND(x) IF_ENCODE((x), F2_COND) 2261590Srgrimes#define EIF_F2_RCOND(x) IF_ENCODE((x), F2_RCOND) 2271590Srgrimes#define EIF_F2_OP2(x) IF_ENCODE((x), F2_OP2) 2281590Srgrimes#define EIF_F2_CC1(x) IF_ENCODE((x), F2_CC1) 2291590Srgrimes#define EIF_F2_CC0(x) IF_ENCODE((x), F2_CC0) 2301590Srgrimes#define EIF_F2_D16HI(x) IF_ENCODE((x), F2_D16HI) 2311590Srgrimes#define EIF_F2_P(x) IF_ENCODE((x), F2_P) 2321590Srgrimes#define EIF_F2_RS1(x) IF_ENCODE((x), F2_RS1) 2331590Srgrimes 2341590Srgrimes/* Instruction format 3 */ 2351590Srgrimes#define EIF_F3_OP3(x) IF_ENCODE((x), F3_OP3) 2361590Srgrimes#define EIF_F3_RD(x) EIF_F2_RD((x)) 2371590Srgrimes#define EIF_F3_FCN(x) IF_ENCODE((x), F3_FCN) 2381590Srgrimes#define EIF_F3_CC1(x) IF_ENCODE((x), F3_CC1) 2391590Srgrimes#define EIF_F3_CC0(x) IF_ENCODE((x), F3_CC0) 2401590Srgrimes#define EIF_F3_RS1(x) EIF_F2_RS1((x)) 2411590Srgrimes#define EIF_F3_I(x) IF_ENCODE((x), F3_I) 2421590Srgrimes#define EIF_F3_X(x) IF_ENCODE((x), F3_X) 2431590Srgrimes#define EIF_F3_RCOND(x) IF_ENCODE((x), F3_RCOND) 2441590Srgrimes#define EIF_F3_IMM_ASI(x) IF_ENCODE((x), F3_IMM_ASI) 2451590Srgrimes#define EIF_F3_OPF(x) IF_ENCODE((x), F3_OPF) 2461590Srgrimes#define EIF_F3_CMASK(x) IF_ENCODE((x), F3_CMASK) 2471590Srgrimes#define EIF_F3_RS2(x) IF_ENCODE((x), F3_RS2) 2481590Srgrimes#define EIF_F3_SHCNT32(x) IF_ENCODE((x), F3_SHCNT32) 2491590Srgrimes#define EIF_F3_SHCNT64(x) IF_ENCODE((x), F3_SHCNT64) 2501590Srgrimes 2511590Srgrimes/* Instruction format 4 */ 2521590Srgrimes#define EIF_F4_OP3(x) EIF_F3_OP3((x)) 2531590Srgrimes#define EIF_F4_RD(x) EIF_F2_RD((x)) 2541590Srgrimes#define EIF_F4_TCOND(x) IF_ENCODE((x), F4_TCOND) 2551590Srgrimes#define EIF_F4_RS1(x) EIF_F2_RS1((x)) 2561590Srgrimes#define EIF_F4_CC2(x) IF_ENCODE((x), F4_CC2) 2571590Srgrimes#define EIF_F4_COND(x) IF_ENCODE((x), F4_COND) 2581590Srgrimes#define EIF_F4_I(x) EIF_F3_I((x)) 2591590Srgrimes#define EIF_F4_OPF_CC(x) IF_ENCODE((x), F4_OPF_CC) 2601590Srgrimes#define EIF_F4_RCOND(x) EIF_F3_RCOND((x)) 2611590Srgrimes#define EIF_F4_OPF_LOW(i, w) IF_INSERT((x), IF_F4_OPF_CC_SHIFT, (w)) 2621590Srgrimes#define EIF_F4_RS2(x) EIF_F3_RS2((x)) 2631590Srgrimes#define EIF_F4_SW_TRAP(x) IF_ENCODE((x), F4_SW_TRAP) 2641590Srgrimes 2651590Srgrimes/* Immediates */ 2661590Srgrimes#define EIF_IMM(x, w) IF_INSERT((x), IF_IMM_SHIFT, (w)) 2671590Srgrimes#define EIF_SIMM(x, w) IF_EIMM((x), (w)) 2681590Srgrimes 2691590Srgrimes/* 2701590Srgrimes * OP field values (specifying the instruction format) 2711590Srgrimes */ 2721590Srgrimes#define IOP_FORM2 0x00 /* Format 2: sethi, branches */ 2731590Srgrimes#define IOP_CALL 0x01 /* Format 1: call */ 2741590Srgrimes#define IOP_MISC 0x02 /* Format 3 or 4: arith & misc */ 2751590Srgrimes#define IOP_LDST 0x03 /* Format 4: loads and stores */ 2761590Srgrimes 2771590Srgrimes/* 2781590Srgrimes * OP2/OP3 values (specifying the actual instruction) 2791590Srgrimes */ 2801590Srgrimes/* OP2 values for format 2 (OP = 0) */ 2811590Srgrimes#define INS0_ILLTRAP 0x00 2821590Srgrimes#define INS0_BPcc 0x01 2831590Srgrimes#define INS0_Bicc 0x02 2841590Srgrimes#define INS0_BPr 0x03 2851590Srgrimes#define INS0_SETHI 0x04 /* with rd = 0 and imm22 = 0, nop */ 2861590Srgrimes#define INS0_FBPfcc 0x05 2871590Srgrimes#define INS0_FBfcc 0x06 2881590Srgrimes/* undefined 0x07 */ 2891590Srgrimes 2901590Srgrimes/* OP3 values for Format 3 and 4 (OP = 2) */ 2911590Srgrimes#define INS2_ADD 0x00 2921590Srgrimes#define INS2_AND 0x01 2931590Srgrimes#define INS2_OR 0x02 2941590Srgrimes#define INS2_XOR 0x03 2951590Srgrimes#define INS2_SUB 0x04 2961590Srgrimes#define INS2_ANDN 0x05 2971590Srgrimes#define INS2_ORN 0x06 2981590Srgrimes#define INS2_XNOR 0x07 2991590Srgrimes#define INS2_ADDC 0x08 3001590Srgrimes#define INS2_MULX 0x09 3011590Srgrimes#define INS2_UMUL 0x0a 3021590Srgrimes#define INS2_SMUL 0x0b 3031590Srgrimes#define INS2_SUBC 0x0c 3041590Srgrimes#define INS2_UDIVX 0x0d 3051590Srgrimes#define INS2_UDIV 0x0e 3061590Srgrimes#define INS2_SDIV 0x0f 3071590Srgrimes#define INS2_ADDcc 0x10 3081590Srgrimes#define INS2_ANDcc 0x11 3091590Srgrimes#define INS2_ORcc 0x12 3101590Srgrimes#define INS2_XORcc 0x13 3111590Srgrimes#define INS2_SUBcc 0x14 3121590Srgrimes#define INS2_ANDNcc 0x15 3131590Srgrimes#define INS2_ORNcc 0x16 3141590Srgrimes#define INS2_XNORcc 0x17 3151590Srgrimes#define INS2_ADDCcc 0x18 3161590Srgrimes/* undefined 0x19 */ 3171590Srgrimes#define INS2_UMULcc 0x1a 3181590Srgrimes#define INS2_SMULcc 0x1b 3191590Srgrimes#define INS2_SUBCcc 0x1c 3201590Srgrimes/* undefined 0x1d */ 3211590Srgrimes#define INS2_UDIVcc 0x1e 3221590Srgrimes#define INS2_SDIVcc 0x1f 3231590Srgrimes#define INS2_TADDcc 0x20 3241590Srgrimes#define INS2_TSUBcc 0x21 3251590Srgrimes#define INS2_TADDccTV 0x22 3261590Srgrimes#define INS2_TSUBccTV 0x23 3271590Srgrimes#define INS2_MULScc 0x24 3281590Srgrimes#define INS2_SSL 0x25 /* SLLX when IF_X(i) == 1 */ 3291590Srgrimes#define INS2_SRL 0x26 /* SRLX when IF_X(i) == 1 */ 3301590Srgrimes#define INS2_SRA 0x27 /* SRAX when IF_X(i) == 1 */ 3311590Srgrimes#define INS2_RD 0x28 /* and MEMBAR, STBAR */ 3321590Srgrimes/* undefined 0x29 */ 3331590Srgrimes#define INS2_RDPR 0x2a 3341590Srgrimes#define INS2_FLUSHW 0x2b 3351590Srgrimes#define INS2_MOVcc 0x2c 3361590Srgrimes#define INS2_SDIVX 0x2d 3371590Srgrimes#define INS2_POPC 0x2e /* undefined if IF_RS1(i) != 0 */ 3381590Srgrimes#define INS2_MOVr 0x2f 3391590Srgrimes#define INS2_WR 0x30 /* and SIR */ 3401590Srgrimes#define INS2_SV_RSTR 0x31 /* saved, restored */ 3411590Srgrimes#define INS2_WRPR 0x32 3421590Srgrimes/* undefined 0x33 */ 3431590Srgrimes#define INS2_FPop1 0x34 /* further encoded in opf field */ 3441590Srgrimes#define INS2_FPop2 0x35 /* further encoded in opf field */ 3451590Srgrimes#define INS2_IMPLDEP1 0x36 3461590Srgrimes#define INS2_IMPLDEP2 0x37 3471590Srgrimes#define INS2_JMPL 0x38 3481590Srgrimes#define INS2_RETURN 0x39 3491590Srgrimes#define INS2_Tcc 0x3a 3501590Srgrimes#define INS2_FLUSH 0x3b 3511590Srgrimes#define INS2_SAVE 0x3c 3521590Srgrimes#define INS2_RESTORE 0x3d 3531590Srgrimes#define INS2_DONE_RETR 0x3e /* done, retry */ 3541590Srgrimes/* undefined 0x3f */ 3551590Srgrimes 3561590Srgrimes/* OP3 values for format 3 (OP = 3) */ 3571590Srgrimes#define INS3_LDUW 0x00 3581590Srgrimes#define INS3_LDUB 0x01 3591590Srgrimes#define INS3_LDUH 0x02 3601590Srgrimes#define INS3_LDD 0x03 3611590Srgrimes#define INS3_STW 0x04 3621590Srgrimes#define INS3_STB 0x05 3631590Srgrimes#define INS3_STH 0x06 3641590Srgrimes#define INS3_STD 0x07 3651590Srgrimes#define INS3_LDSW 0x08 3661590Srgrimes#define INS3_LDSB 0x09 3671590Srgrimes#define INS3_LDSH 0x0a 3681590Srgrimes#define INS3_LDX 0x0b 3691590Srgrimes/* undefined 0x0c */ 3701590Srgrimes#define INS3_LDSTUB 0x0d 3711590Srgrimes#define INS3_STX 0x0e 3721590Srgrimes#define INS3_SWAP 0x0f 3731590Srgrimes#define INS3_LDUWA 0x10 3741590Srgrimes#define INS3_LDUBA 0x11 3751590Srgrimes#define INS3_LDUHA 0x12 3761590Srgrimes#define INS3_LDDA 0x13 3771590Srgrimes#define INS3_STWA 0x14 3781590Srgrimes#define INS3_STBA 0x15 3791590Srgrimes#define INS3_STHA 0x16 3801590Srgrimes#define INS3_STDA 0x17 3811590Srgrimes#define INS3_LDSWA 0x18 3821590Srgrimes#define INS3_LDSBA 0x19 3831590Srgrimes#define INS3_LDSHA 0x1a 3841590Srgrimes#define INS3_LDXA 0x1b 3851590Srgrimes/* undefined 0x1c */ 3861590Srgrimes#define INS3_LDSTUBA 0x1d 3871590Srgrimes#define INS3_STXA 0x1e 3881590Srgrimes#define INS3_SWAPA 0x1f 3891590Srgrimes#define INS3_LDF 0x20 3901590Srgrimes#define INS3_LDFSR 0x21 /* and LDXFSR */ 3911590Srgrimes#define INS3_LDQF 0x22 3921590Srgrimes#define INS3_LDDF 0x23 3931590Srgrimes#define INS3_STF 0x24 3941590Srgrimes#define INS3_STFSR 0x25 /* and STXFSR */ 3951590Srgrimes#define INS3_STQF 0x26 3961590Srgrimes#define INS3_STDF 0x27 39727315Scharnier/* undefined 0x28 - 0x2c */ 3981590Srgrimes#define INS3_PREFETCH 0x2d 3991590Srgrimes/* undefined 0x2e - 0x2f */ 4001590Srgrimes#define INS3_LDFA 0x30 4011590Srgrimes/* undefined 0x31 */ 4021590Srgrimes#define INS3_LDQFA 0x32 4031590Srgrimes#define INS3_LDDFA 0x33 4041590Srgrimes#define INS3_STFA 0x34 4051590Srgrimes/* undefined 0x35 */ 4061590Srgrimes#define INS3_STQFA 0x36 4071590Srgrimes#define INS3_STDFA 0x37 4081590Srgrimes/* undefined 0x38 - 0x3b */ 4091590Srgrimes#define INS3_CASA 0x39 4101590Srgrimes#define INS3_PREFETCHA 0x3a 4111590Srgrimes#define INS3_CASXA 0x3b 4121590Srgrimes 4131590Srgrimes/* 4141590Srgrimes * OPF values (floating point instructions, IMPLDEP) 4151590Srgrimes */ 4161590Srgrimes/* 4171590Srgrimes * These values are or'ed to the FPop values to get the instructions. 4181590Srgrimes * They describe the operand type(s). 4191590Srgrimes */ 4201590Srgrimes#define INSFP_i 0x000 /* 32-bit int */ 4211590Srgrimes#define INSFP_s 0x001 /* 32-bit single */ 4221590Srgrimes#define INSFP_d 0x002 /* 64-bit double */ 4231590Srgrimes#define INSFP_q 0x003 /* 128-bit quad */ 4241590Srgrimes/* FPop1. The comments give the types for which this instruction is defined. */ 4251590Srgrimes#define INSFP1_FMOV 0x000 /* s, d, q */ 4261590Srgrimes#define INSFP1_FNEG 0x004 /* s, d, q */ 4271590Srgrimes#define INSFP1_FABS 0x008 /* s, d, q */ 4281590Srgrimes#define INSFP1_FSQRT 0x028 /* s, d, q */ 4291590Srgrimes#define INSFP1_FADD 0x040 /* s, d, q */ 4301590Srgrimes#define INSFP1_FSUB 0x044 /* s, d, q */ 4311590Srgrimes#define INSFP1_FMUL 0x048 /* s, d, q */ 4321590Srgrimes#define INSFP1_FDIV 0x04c /* s, d, q */ 4331590Srgrimes#define INSFP1_FsMULd 0x068 /* s */ 4341590Srgrimes#define INSFP1_FdMULq 0x06c /* d */ 4351590Srgrimes#define INSFP1_FTOx 0x080 /* s, d, q */ 4361590Srgrimes#define INSFP1_FxTOs 0x084 /* special: i only */ 4371590Srgrimes#define INSFP1_FxTOd 0x088 /* special: i only */ 4381590Srgrimes#define INSFP1_FxTOq 0x08c /* special: i only */ 4391590Srgrimes#define INSFP1_FTOs 0x0c4 /* i, d, q */ 4401590Srgrimes#define INSFP1_FTOd 0x0c8 /* i, s, q */ 4411590Srgrimes#define INSFP1_FTOq 0x0cc /* i, s, d */ 4421590Srgrimes#define INSFP1_FTOi 0x0d0 /* i, s, d */ 4431590Srgrimes 4441590Srgrimes/* FPop2 */ 4451590Srgrimes#define INSFP2_FMOV_CCMUL 0x40 4461590Srgrimes#define INSFP2_FMOV_CCOFFS 0x00 4471590Srgrimes/* Use the IFCC_* constants for cc. Operand types: s, d, q */ 4481590Srgrimes#define INSFP2_FMOV_CC(cc) ((cc) * INSFP2_FMOV_CCMUL + INSFP2_FMOV_CCOFFS) 4491590Srgrimes#define INSFP2_FMOV_RCMUL 0x20 4501590Srgrimes#define INSFP2_FMOV_RCOFFS 0x04 4511590Srgrimes/* Use the IRCOND_* constants for rc. Operand types: s, d, q */ 4521590Srgrimes#define INSFP2_FMOV_RC(rc) ((rc) * INSFP2_FMOV_RCMUL + INSFP2_FMOV_RCOFFS) 4531590Srgrimes#define INSFP2_FCMP 0x050 /* s, d, q */ 4541590Srgrimes#define INSFP2_FCMPE 0x054 /* s, d, q */ 4551590Srgrimes 4561590Srgrimes/* IMPLDEP1 for Sun UltraSparc */ 4571590Srgrimes#define IIDP1_EDGE8 0x00 4581590Srgrimes#define IIDP1_EDGE8L 0x02 4591590Srgrimes#define IIDP1_EDGE16 0x04 4601590Srgrimes#define IIDP1_EDGE16L 0x06 4611590Srgrimes#define IIDP1_EDGE32 0x08 4621590Srgrimes#define IIDP1_EDGE32L 0x0a 4631590Srgrimes#define IIDP1_ARRAY8 0x10 4641590Srgrimes#define IIDP1_ARRAY16 0x12 4651590Srgrimes#define IIDP1_ARRAY32 0x14 4661590Srgrimes#define IIDP1_ALIGNADDRESS 0x18 4671590Srgrimes#define IIDP1_ALIGNADDRESS_L 0x1a 4681590Srgrimes#define IIDP1_FCMPLE16 0x20 4691590Srgrimes#define IIDP1_FCMPNE16 0x22 4701590Srgrimes#define IIDP1_FCMPLE32 0x24 4711590Srgrimes#define IIDP1_FCMPNE32 0x26 4721590Srgrimes#define IIDP1_FCMPGT16 0x28 4731590Srgrimes#define IIDP1_FCMPEQ16 0x2a 4741590Srgrimes#define IIDP1_FCMPGT32 0x2c 4751590Srgrimes#define IIDP1_FCMPEQ32 0x2e 4761590Srgrimes#define IIDP1_FMUL8x16 0x31 4771590Srgrimes#define IIDP1_FMUL8x16AU 0x33 4781590Srgrimes#define IIDP1_FMUL8X16AL 0x35 4791590Srgrimes#define IIDP1_FMUL8SUx16 0x36 4801590Srgrimes#define IIDP1_FMUL8ULx16 0x37 4811590Srgrimes#define IIDP1_FMULD8SUx16 0x38 4821590Srgrimes#define IIDP1_FMULD8ULx16 0x39 4831590Srgrimes#define IIDP1_FPACK32 0x3a 4841590Srgrimes#define IIDP1_FPACK16 0x3b 4851590Srgrimes#define IIDP1_FPACKFIX 0x3d 4861590Srgrimes#define IIDP1_PDIST 0x3e 4871590Srgrimes#define IIDP1_FALIGNDATA 0x48 4881590Srgrimes#define IIDP1_FPMERGE 0x4b 48927315Scharnier#define IIDP1_FEXPAND 0x4d 4901590Srgrimes#define IIDP1_FPADD16 0x50 4911590Srgrimes#define IIDP1_FPADD16S 0x51 4921590Srgrimes#define IIDP1_FPADD32 0x52 4931590Srgrimes#define IIDP1_FPADD32S 0x53 4941590Srgrimes#define IIDP1_SUB16 0x54 49527315Scharnier#define IIDP1_SUB16S 0x55 4961590Srgrimes#define IIDP1_SUB32 0x56 4971590Srgrimes#define IIDP1_SUB32S 0x57 4981590Srgrimes#define IIDP1_FZERO 0x60 4991590Srgrimes#define IIDP1_FZEROS 0x61 5001590Srgrimes#define IIDP1_FNOR 0x62 5011590Srgrimes#define IIDP1_FNORS 0x63 50227315Scharnier#define IIDP1_FANDNOT2 0x64 5031590Srgrimes#define IIDP1_FANDNOT2S 0x65 5041590Srgrimes#define IIDP1_NOT2 0x66 5051590Srgrimes#define IIDP1_NOT2S 0x67 5061590Srgrimes#define IIDP1_FANDNOT1 0x68 5071590Srgrimes#define IIDP1_FANDNOT1S 0x69 5081590Srgrimes#define IIDP1_FNOT1 0x6a 50927315Scharnier#define IIDP1_FNOT1S 0x6b 5101590Srgrimes#define IIDP1_FXOR 0x6c 511#define IIDP1_FXORS 0x6d 512#define IIDP1_FNAND 0x6e 513#define IIDP1_FNANDS 0x6f 514#define IIDP1_FAND 0x70 515#define IIDP1_FANDS 0x71 516#define IIDP1_FXNOR 0x72 517#define IIDP1_FXNORS 0x73 518#define IIDP1_FSRC1 0x74 519#define IIDP1_FSRC1S 0x75 520#define IIDP1_FORNOT2 0x76 521#define IIDP1_FORNOT2S 0x77 522#define IIDP1_FSRC2 0x78 523#define IIDP1_FSRC2S 0x79 524#define IIDP1_FORNOT1 0x7a 525#define IIDP1_FORNOT1S 0x7b 526#define IIDP1_FOR 0x7c 527#define IIDP1_FORS 0x7d 528#define IIDP1_FONE 0x7e 529#define IIDP1_FONES 0x7f 530#define IIDP1_SHUTDOWN 0x80 531 532/* 533 * Instruction modifiers 534 */ 535/* cond values for integer ccr's */ 536#define IICOND_N 0x00 537#define IICOND_E 0x01 538#define IICOND_LE 0x02 539#define IICOND_L 0x03 540#define IICOND_LEU 0x04 541#define IICOND_CS 0x05 542#define IICOND_NEG 0x06 543#define IICOND_VS 0x07 544#define IICOND_A 0x08 545#define IICOND_NE 0x09 546#define IICOND_G 0x0a 547#define IICOND_GE 0x0b 548#define IICOND_GU 0x0c 549#define IICOND_CC 0x0d 550#define IICOND_POS 0x0e 551#define IICOND_VC 0x0f 552 553/* cond values for fp ccr's */ 554#define IFCOND_N 0x00 555#define IFCOND_NE 0x01 556#define IFCOND_LG 0x02 557#define IFCOND_UL 0x03 558#define IFCOND_L 0x04 559#define IFCOND_UG 0x05 560#define IFCOND_G 0x06 561#define IFCOND_U 0x07 562#define IFCOND_A 0x08 563#define IFCOND_E 0x09 564#define IFCOND_UE 0x0a 565#define IFCOND_GE 0x0b 566#define IFCOND_UGE 0x0c 567#define IFCOND_LE 0x0d 568#define IFCOND_ULE 0x0e 569#define IFCOND_O 0x0f 570 571/* rcond values for BPr, MOVr, FMOVr */ 572#define IRCOND_Z 0x01 573#define IRCOND_LEZ 0x02 574#define IRCOND_LZ 0x03 575#define IRCOND_NZ 0x05 576#define IRCOND_GZ 0x06 577#define IRCOND_GEZ 0x07 578 579/* cc values for MOVcc and FMOVcc */ 580#define IFCC_ICC 0x04 581#define IFCC_XCC 0x06 582/* if true, the lower 2 bits are the fcc number */ 583#define IFCC_FCC(c) ((c) & 3) 584#define IFCC_GET_FCC(c) ((c) & 3) 585#define IFCC_ISFCC(c) (((c) & 4) == 0) 586 587/* cc values for BPc and Tcc */ 588#define IBCC_ICC 0x00 589#define IBCC_XCC 0x02 590 591/* 592 * Integer registers 593 */ 594#define IREG_G0 0x00 595#define IREG_O0 0x08 596#define IREG_L0 0x10 597#define IREQ_I0 0x18 598 599#endif /* !_MACHINE_INSTR_H_ */ 600