#
331722 |
|
29-Mar-2018 |
eadler |
Revert r330897:
This was intended to be a non-functional change. It wasn't. The commit message was thus wrong. In addition it broke arm, and merged crypto related code.
Revert with prejudice.
This revert skips files touched in r316370 since that commit was since MFCed. This revert also skips files that require $FreeBSD$ property changes.
Thank you to those who helped me get out of this mess including but not limited to gonzo, kevans, rgrimes.
Requested by: gjb (re)
|
#
330897 |
|
14-Mar-2018 |
eadler |
Partial merge of the SPDX changes
These changes are incomplete but are making it difficult to determine what other changes can/should be merged.
No objections from: pfg
|
#
302408 |
|
07-Jul-2016 |
gjb |
Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle. Prune svn:mergeinfo from the new branch, as nothing has been merged here.
Additional commits post-branch will follow.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
#
260162 |
|
01-Jan-2014 |
emaste |
Remove TNF license clauses 3 and 4, matching upstream
Approved by raj@ (Semihalf has a copyright statement in the license block as well).
|
#
257178 |
|
26-Oct-2013 |
nwhitehorn |
Interrelated improvements to early boot mappings: - Remove explicit requirement that the SOC registers be found except as an optimization (although the MPC85XX LAW drivers still require they be found externally, which should change). - Remove magic CCSRBAR_VA value. - Allow bus_machdep.c's early-boot code to handle non 1:1 mappings and systems not in real-mode or global 1:1 maps in early boot. - Allow pmap_mapdev() on Book-E to reissue previous addresses if the area is already mapped. Additionally have it check all mappings, not just the CCSR area.
This allows the console on e500 systems to actually work on systems where the boot loader was not kind enough to set up a 1:1 mapping before starting the kernel.
|
#
234579 |
|
22-Apr-2012 |
nwhitehorn |
Replace eieio; sync for creating bus-space memory barriers with sync. sync performs a strict superset of the functions of eieio, so using both is redundant. While here, expand bus barriers to all bus_space operations, since many drivers do not correctly use bus_space_barrier().
In principle, we can also replace sync just with eieio, for a significant performance increase, but it remains to be seen whether any poorly-written drivers currently depend on the side effects of sync to properly function.
MFC after: 1 week
|
#
226410 |
|
15-Oct-2011 |
nwhitehorn |
Enforce a memory barrier in stream operations, as is done on other bus_space calls. This makes ath(4) work correctly on PowerPC.
Submitted by: adrian Tested by: andreast MFC after: 3 days
|
#
213307 |
|
30-Sep-2010 |
nwhitehorn |
Add support for memory attributes (pmap_mapdev_attr() and friends) on PowerPC/AIM. This is currently stubbed out on Book-E, since I have no idea how to implement it there.
|
#
209849 |
|
09-Jul-2010 |
nwhitehorn |
MFppc64:
Check if devices are direct-mapped individually instead of just checking the value of hw_direct_map.
|
#
193578 |
|
06-Jun-2009 |
raj |
Provide 64-bit big endian bus space operations for PowerPC. They are required for the upcoming sec(4) driver.
Submitted by: Piotr Ziecik Obtained from: Semihalf
|
#
191447 |
|
24-Apr-2009 |
marcel |
Reimplement bs_be_rs_{1|2|4} and bs_le_rs_{1|2|4} by not calling the inline functions in <machine/pio.h> and do not add synchronization. Implement bs_gen_barrier() as eieio and sync.
|
#
190681 |
|
03-Apr-2009 |
nwhitehorn |
Add support for 64-bit PowerPC CPUs operating in the 64-bit bridge mode provided, for example, on the PowerPC 970 (G5), as well as on related CPUs like the POWER3 and POWER4.
This also adds support for various built-in hardware found on Apple G5 hardware (e.g. the IBM CPC925 northbridge).
Reviewed by: grehan
|
#
174782 |
|
19-Dec-2007 |
marcel |
Redefine bus_space_tag_t on PowerPC from a 32-bit integral to a pointer to struct bus_space. The structure contains function pointers that do the actual bus space access.
The reason for this change is that previously all bus space accesses were little endian (i.e. had an explicit byte-swap for multi-byte accesses), because all busses on Macs are little endian. The upcoming support for Book E, and in particular the E500 core, requires support for big-endian busses because all embedded peripherals are in the native byte-order.
With this change, there's no distinction between I/O port space and memory mapped I/O. PowerPC doesn't have I/O port space. Busses assign tags based on the byte-order only. For that purpose, two global structures exist (bs_be_tag and bs_le_tag), of which the address can be taken to get a valid tag.
Obtained from: Juniper, Semihalf
|