cpufunc.h revision 295200
1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD: head/sys/arm/include/cpufunc.h 295200 2016-02-03 09:15:44Z mmel $ 42 */ 43 44#ifndef _MACHINE_CPUFUNC_H_ 45#define _MACHINE_CPUFUNC_H_ 46 47#ifdef _KERNEL 48 49#include <sys/types.h> 50#include <machine/armreg.h> 51#include <machine/cpuconf.h> 52 53static __inline void 54breakpoint(void) 55{ 56 __asm(".word 0xe7ffffff"); 57} 58 59struct cpu_functions { 60 61 /* CPU functions */ 62 63 void (*cf_cpwait) (void); 64 65 /* MMU functions */ 66 67 u_int (*cf_control) (u_int bic, u_int eor); 68 void (*cf_setttb) (u_int ttb); 69 70 /* TLB functions */ 71 72 void (*cf_tlb_flushID) (void); 73 void (*cf_tlb_flushID_SE) (u_int va); 74 void (*cf_tlb_flushD) (void); 75 void (*cf_tlb_flushD_SE) (u_int va); 76 77 /* 78 * Cache operations: 79 * 80 * We define the following primitives: 81 * 82 * icache_sync_all Synchronize I-cache 83 * icache_sync_range Synchronize I-cache range 84 * 85 * dcache_wbinv_all Write-back and Invalidate D-cache 86 * dcache_wbinv_range Write-back and Invalidate D-cache range 87 * dcache_inv_range Invalidate D-cache range 88 * dcache_wb_range Write-back D-cache range 89 * 90 * idcache_wbinv_all Write-back and Invalidate D-cache, 91 * Invalidate I-cache 92 * idcache_wbinv_range Write-back and Invalidate D-cache, 93 * Invalidate I-cache range 94 * 95 * Note that the ARM term for "write-back" is "clean". We use 96 * the term "write-back" since it's a more common way to describe 97 * the operation. 98 * 99 * There are some rules that must be followed: 100 * 101 * ID-cache Invalidate All: 102 * Unlike other functions, this one must never write back. 103 * It is used to intialize the MMU when it is in an unknown 104 * state (such as when it may have lines tagged as valid 105 * that belong to a previous set of mappings). 106 * 107 * I-cache Synch (all or range): 108 * The goal is to synchronize the instruction stream, 109 * so you may beed to write-back dirty D-cache blocks 110 * first. If a range is requested, and you can't 111 * synchronize just a range, you have to hit the whole 112 * thing. 113 * 114 * D-cache Write-Back and Invalidate range: 115 * If you can't WB-Inv a range, you must WB-Inv the 116 * entire D-cache. 117 * 118 * D-cache Invalidate: 119 * If you can't Inv the D-cache, you must Write-Back 120 * and Invalidate. Code that uses this operation 121 * MUST NOT assume that the D-cache will not be written 122 * back to memory. 123 * 124 * D-cache Write-Back: 125 * If you can't Write-back without doing an Inv, 126 * that's fine. Then treat this as a WB-Inv. 127 * Skipping the invalidate is merely an optimization. 128 * 129 * All operations: 130 * Valid virtual addresses must be passed to each 131 * cache operation. 132 */ 133 void (*cf_icache_sync_all) (void); 134 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 135 136 void (*cf_dcache_wbinv_all) (void); 137 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 138 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 139 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 140 141 void (*cf_idcache_inv_all) (void); 142 void (*cf_idcache_wbinv_all) (void); 143 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 144 void (*cf_l2cache_wbinv_all) (void); 145 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 146 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 147 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 148 void (*cf_l2cache_drain_writebuf) (void); 149 150 /* Other functions */ 151 152 void (*cf_drain_writebuf) (void); 153 154 void (*cf_sleep) (int mode); 155 156 /* Soft functions */ 157 158 void (*cf_context_switch) (void); 159 160 void (*cf_setup) (void); 161}; 162 163extern struct cpu_functions cpufuncs; 164extern u_int cputype; 165 166#define cpu_cpwait() cpufuncs.cf_cpwait() 167 168#define cpu_control(c, e) cpufuncs.cf_control(c, e) 169#define cpu_setttb(t) cpufuncs.cf_setttb(t) 170 171#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 172#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 173#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 174#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 175 176#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 177#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 178 179#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 180#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 181#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 182#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 183 184#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 185#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 186#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 187#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 188#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 189#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 190#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 191#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() 192 193#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 194#define cpu_sleep(m) cpufuncs.cf_sleep(m) 195 196#define cpu_setup() cpufuncs.cf_setup() 197 198int set_cpufuncs (void); 199#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 200#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 201 202void cpufunc_nullop (void); 203u_int cpu_ident (void); 204u_int cpufunc_control (u_int clear, u_int bic); 205void cpu_domains (u_int domains); 206u_int cpu_faultstatus (void); 207u_int cpu_faultaddress (void); 208u_int cpu_pfr (int); 209 210#if defined(CPU_FA526) 211void fa526_setup (void); 212void fa526_setttb (u_int ttb); 213void fa526_context_switch (void); 214void fa526_cpu_sleep (int); 215void fa526_tlb_flushID_SE (u_int); 216 217void fa526_icache_sync_all (void); 218void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 219void fa526_dcache_wbinv_all (void); 220void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 221void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 222void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 223void fa526_idcache_wbinv_all(void); 224void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 225#endif 226 227 228#if defined(CPU_ARM9) || defined(CPU_ARM9E) 229void arm9_setttb (u_int); 230void arm9_tlb_flushID_SE (u_int va); 231void arm9_context_switch (void); 232#endif 233 234#if defined(CPU_ARM9) 235void arm9_icache_sync_all (void); 236void arm9_icache_sync_range (vm_offset_t, vm_size_t); 237 238void arm9_dcache_wbinv_all (void); 239void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 240void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 241void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 242 243void arm9_idcache_wbinv_all (void); 244void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 245 246void arm9_setup (void); 247 248extern unsigned arm9_dcache_sets_max; 249extern unsigned arm9_dcache_sets_inc; 250extern unsigned arm9_dcache_index_max; 251extern unsigned arm9_dcache_index_inc; 252#endif 253 254#if defined(CPU_ARM9E) 255void arm10_setup (void); 256 257u_int sheeva_control_ext (u_int, u_int); 258void sheeva_cpu_sleep (int); 259void sheeva_setttb (u_int); 260void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 261void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 262void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 263void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 264 265void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 266void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 267void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 268void sheeva_l2cache_wbinv_all (void); 269#endif 270 271#if defined(CPU_MV_PJ4B) 272void armv6_idcache_wbinv_all (void); 273#endif 274#if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) 275void armv7_setttb (u_int); 276void armv7_tlb_flushID (void); 277void armv7_tlb_flushID_SE (u_int); 278void armv7_icache_sync_all (void); 279void armv7_icache_sync_range (vm_offset_t, vm_size_t); 280void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); 281void armv7_idcache_inv_all (void); 282void armv7_dcache_wbinv_all (void); 283void armv7_idcache_wbinv_all (void); 284void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 285void armv7_dcache_inv_range (vm_offset_t, vm_size_t); 286void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 287void armv7_cpu_sleep (int); 288void armv7_setup (void); 289void armv7_context_switch (void); 290void armv7_drain_writebuf (void); 291void armv7_sev (void); 292u_int armv7_auxctrl (u_int, u_int); 293 294void armadaxp_idcache_wbinv_all (void); 295 296void cortexa_setup (void); 297#endif 298#if defined(CPU_MV_PJ4B) 299void pj4b_config (void); 300void pj4bv7_setup (void); 301#endif 302 303#if defined(CPU_ARM1176) 304void arm11_tlb_flushID (void); 305void arm11_tlb_flushID_SE (u_int); 306void arm11_tlb_flushD (void); 307void arm11_tlb_flushD_SE (u_int va); 308 309void arm11_context_switch (void); 310 311void arm11_drain_writebuf (void); 312 313void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 314void armv6_dcache_inv_range (vm_offset_t, vm_size_t); 315void armv6_dcache_wb_range (vm_offset_t, vm_size_t); 316 317void armv6_idcache_inv_all (void); 318 319void arm11x6_setttb (u_int); 320void arm11x6_idcache_wbinv_all (void); 321void arm11x6_dcache_wbinv_all (void); 322void arm11x6_icache_sync_all (void); 323void arm11x6_icache_sync_range (vm_offset_t, vm_size_t); 324void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t); 325void arm11x6_setup (void); 326void arm11x6_sleep (int); /* no ref. for errata */ 327#endif 328 329#if defined(CPU_ARM9E) 330void armv5_ec_setttb(u_int); 331 332void armv5_ec_icache_sync_all(void); 333void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 334 335void armv5_ec_dcache_wbinv_all(void); 336void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 337void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 338void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 339 340void armv5_ec_idcache_wbinv_all(void); 341void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 342#endif 343 344#if defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 345 defined(CPU_FA526) || \ 346 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 347 defined(CPU_XSCALE_81342) 348 349void armv4_tlb_flushID (void); 350void armv4_tlb_flushD (void); 351void armv4_tlb_flushD_SE (u_int va); 352 353void armv4_drain_writebuf (void); 354void armv4_idcache_inv_all (void); 355#endif 356 357#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 358 defined(CPU_XSCALE_81342) 359void xscale_cpwait (void); 360 361void xscale_cpu_sleep (int mode); 362 363u_int xscale_control (u_int clear, u_int bic); 364 365void xscale_setttb (u_int ttb); 366 367void xscale_tlb_flushID_SE (u_int va); 368 369void xscale_cache_flushID (void); 370void xscale_cache_flushI (void); 371void xscale_cache_flushD (void); 372void xscale_cache_flushD_SE (u_int entry); 373 374void xscale_cache_cleanID (void); 375void xscale_cache_cleanD (void); 376void xscale_cache_cleanD_E (u_int entry); 377 378void xscale_cache_clean_minidata (void); 379 380void xscale_cache_purgeID (void); 381void xscale_cache_purgeID_E (u_int entry); 382void xscale_cache_purgeD (void); 383void xscale_cache_purgeD_E (u_int entry); 384 385void xscale_cache_syncI (void); 386void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 387void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 388void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 389void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 390void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 391void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 392 393void xscale_context_switch (void); 394 395void xscale_setup (void); 396#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 397 398#ifdef CPU_XSCALE_81342 399 400void xscalec3_l2cache_purge (void); 401void xscalec3_cache_purgeID (void); 402void xscalec3_cache_purgeD (void); 403void xscalec3_cache_cleanID (void); 404void xscalec3_cache_cleanD (void); 405void xscalec3_cache_syncI (void); 406 407void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 408void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 409void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 410void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 411void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 412 413void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 414void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 415void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 416 417 418void xscalec3_setttb (u_int ttb); 419void xscalec3_context_switch (void); 420 421#endif /* CPU_XSCALE_81342 */ 422 423#define setttb cpu_setttb 424#define drain_writebuf cpu_drain_writebuf 425 426/* 427 * Macros for manipulating CPU interrupts 428 */ 429#if __ARM_ARCH < 6 430#define __ARM_INTR_BITS (PSR_I | PSR_F) 431#else 432#define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) 433#endif 434 435static __inline uint32_t 436__set_cpsr(uint32_t bic, uint32_t eor) 437{ 438 uint32_t tmp, ret; 439 440 __asm __volatile( 441 "mrs %0, cpsr\n" /* Get the CPSR */ 442 "bic %1, %0, %2\n" /* Clear bits */ 443 "eor %1, %1, %3\n" /* XOR bits */ 444 "msr cpsr_xc, %1\n" /* Set the CPSR */ 445 : "=&r" (ret), "=&r" (tmp) 446 : "r" (bic), "r" (eor) : "memory"); 447 448 return ret; 449} 450 451static __inline uint32_t 452disable_interrupts(uint32_t mask) 453{ 454 455 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); 456} 457 458static __inline uint32_t 459enable_interrupts(uint32_t mask) 460{ 461 462 return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); 463} 464 465static __inline uint32_t 466restore_interrupts(uint32_t old_cpsr) 467{ 468 469 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); 470} 471 472static __inline register_t 473intr_disable(void) 474{ 475 476 return (disable_interrupts(PSR_I | PSR_F)); 477} 478 479static __inline void 480intr_restore(register_t s) 481{ 482 483 restore_interrupts(s); 484} 485#undef __ARM_INTR_BITS 486 487/* 488 * Functions to manipulate cpu r13 489 * (in arm/arm32/setstack.S) 490 */ 491 492void set_stackptr (u_int mode, u_int address); 493u_int get_stackptr (u_int mode); 494 495/* 496 * Miscellany 497 */ 498 499int get_pc_str_offset (void); 500 501/* 502 * CPU functions from locore.S 503 */ 504 505void cpu_reset (void) __attribute__((__noreturn__)); 506 507/* 508 * Cache info variables. 509 */ 510 511/* PRIMARY CACHE VARIABLES */ 512extern int arm_picache_size; 513extern int arm_picache_line_size; 514extern int arm_picache_ways; 515 516extern int arm_pdcache_size; /* and unified */ 517extern int arm_pdcache_line_size; 518extern int arm_pdcache_ways; 519 520extern int arm_pcache_type; 521extern int arm_pcache_unified; 522 523extern int arm_dcache_align; 524extern int arm_dcache_align_mask; 525 526extern u_int arm_cache_level; 527extern u_int arm_cache_loc; 528extern u_int arm_cache_type[14]; 529 530#endif /* _KERNEL */ 531#endif /* _MACHINE_CPUFUNC_H_ */ 532 533/* End of cpufunc.h */ 534