#
296373 |
|
04-Mar-2016 |
marius |
- Copy stable/10@296371 to releng/10.3 in preparation for 10.3-RC1 builds. - Update newvers.sh to reflect RC1. - Update __FreeBSD_version to reflect 10.3. - Update default pkg(8) configuration to use the quarterly branch.
Approved by: re (implicit) |
#
295789 |
|
19-Feb-2016 |
sephe |
MFC [Hyper-V]: r293719-r293722, r293869-r293871, r293873-r293875, r293877
r293719 hyperv/hn: Implement LRO r293720 hyperv/hn: Implement SIOC[SG]IFMEDIA support r293721 hyperv/hn: Avoid mbuf cluster allocation, if the packet is small. r293722 hyperv/hn: Removed unused netvsc_init() r293869 hyperv/hn: Unbreak LINT-NOIP r293870 hyperv: use x86 generic code to do the hypervisor detection r293871 hyperv: remove unused vmbus definitions r293873 hyperv: implement an event timer r293874 hyperv: add interrupt counters r293875 hyperv: set receive buffer size according to NVSP protocol version r293877 Unbreak `make depend` with sys/modules/hyperv/vmbus after r293870
Approved by: re (glebius), adrian (mentor) Sponsored by: Microsoft OSTC
|
#
293195 |
|
05-Jan-2016 |
kib |
MFC r292890: Add standard extended feature bit 6 from the Intel SDM rev. 57.
|
#
291378 |
|
27-Nov-2015 |
kib |
MFC r291266: Correct the number of DTLB entries reported for the CPUID Leaf 2 descriptor 0x6c.
|
#
290187 |
|
30-Oct-2015 |
kib |
MFC r289823: Decode new values for CPUID leaf 2 cache and TLB descriptors, from the Intel SDM revision 56.
|
#
287462 |
|
04-Sep-2015 |
sbruno |
MFC r276834
Update Features2 to display SDBG capability of processor. This is showing up on Haswell-class CPUs
From the Intel SDM, "Table 3-20. Feature Information Returned in the ECX Register"
11 | SDBG | A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug.
Submitted by: jiashiun@gmail.com
|
#
286852 |
|
17-Aug-2015 |
kib |
MFC r286228: Clear the IA32_MISC_ENABLE MSR bit on APs.
|
#
284338 |
|
13-Jun-2015 |
kib |
MFC r284104: Updates from SDM rev. 55.
|
#
278522 |
|
10-Feb-2015 |
jhb |
MFC 273800: Rework virtual machine hypervisor detection. - Move the existing code to x86/x86/identcpu.c since it is x86-specific. - If the CPUID2_HV flag is set, assume a hypervisor is present and query the 0x40000000 leaf to determine the hypervisor vendor ID. Export the vendor ID and the highest supported hypervisor CPUID leaf via hv_vendor[] and hv_high variables, respectively. The hv_vendor[] array is also exported via the hw.hv_vendor sysctl. - Merge the VMWare detection code from tsc.c into the new probe in identcpu.c. Add a VM_GUEST_VMWARE to identify vmware and use that in the TSC code to identify VMWare.
|
#
277374 |
|
19-Jan-2015 |
kib |
MFC r277047: For x86, read MAXPHYADDR into variable cpu_maxphyaddr.
|
#
276482 |
|
31-Dec-2014 |
neel |
MFC r273748
Output a summary of optional SVM features in dmesg similar to CPU features. If bootverbose is enabled, a detailed list is provided; otherwise, a single-line summary is displayed.
Requested by: jhb
|
#
276132 |
|
23-Dec-2014 |
kib |
MFC r271197: Add more bits for the XSAVE features from CPUID 0xd, sub-function 1 %eax report. Print the XSAVE features 0xd/1 in the boot banner.
|
#
276076 |
|
22-Dec-2014 |
jhb |
MFC 271405,271408,271409,272658: MFamd64: Use initializecpu() to set various model-specific registers on AP startup and AP resume (it was already used for BSP startup and BSP resume).
|
#
276070 |
|
22-Dec-2014 |
jhb |
MFC 260557,271076,271077,271082,271083,271098: - Remove spaces from boot messages when we print the CPU ID/Family/Stepping - Move prototypes for various functions into out of C files and into <machine/md_var.h>. - Reduce diffs between i386 and amd64 initcpu.c and identcpu.c files. - Move blacklists of broken TSCs out of the printcpuinfo() function and into the TSC probe routine. - Merge the amd64 and i386 identcpu.c into a single x86 implementation.
|
#
271098 |
|
04-Sep-2014 |
jhb |
Merge the amd64 and i386 identcpu.c into a single x86 implementation. This brings the structured extended features mask and VT-x reporting to i386 and Intel cache and TLB info (under bootverbose) to amd64.
|
#
271077 |
|
04-Sep-2014 |
jhb |
Remove trailing whitespace.
|
#
271076 |
|
04-Sep-2014 |
jhb |
- Move prototypes for various functions into out of C files and into <machine/md_var.h>. - Move some CPU-related variables out of i386/i386/identcpu.c to initcpu.c to match amd64. - Move the declaration of has_f00f_hack out of identcpu.c to machdep.c. - Remove a misleading comment from i386/i386/initcpu.c (locore zeros the BSS before it calls identify_cpu()) and remove explicit zero assignments to reduce the diff with amd64.
|
#
269281 |
|
30-Jul-2014 |
jhb |
- Output a summary of optional VT-x features in dmesg similar to CPU features. If bootverbose is enabled, a detailed list is provided; otherwise, a single-line summary is displayed. - Add read-only sysctls for optional VT-x capabilities used by bhyve under a new hw.vmm.vmx.cap node. Move a few exiting sysctls that indicate the presence of optional capabilities under this node.
CR: https://phabric.freebsd.org/D498 Reviewed by: grehan, neel MFC after: 1 week
|
#
266263 |
|
16-May-2014 |
jhb |
Add definitions for more structured extended features as well as XSAVE Extended Features for AVX512 and MPX (Memory Protection Extensions).
Obtained from: Intel's Instruction Set Extensions Programming Reference (March 2014)
|
#
260557 |
|
11-Jan-2014 |
gavin |
Remove spaces from boot messages when we print the CPU ID/Family/Stepping to match the rest of the CPU identification lines, and once again fit into 80 columns in the usual case.
|
#
257856 |
|
08-Nov-2013 |
kib |
Add bits for the AMD features from CPUID function 0x80000001 ECX, described in the rev. 3.0 of the Kabini BKDG, document 48751.pdf.
Partially based on the patch submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com> Sponsored by: The FreeBSD Foundation MFC after: 1 week
|
#
253747 |
|
28-Jul-2013 |
avg |
x86: detect mwait capabilities and extensions, when present
Reviewed by: kib (earlier amd64-only version) MFC after: 2 weeks
|
#
250495 |
|
11-May-2013 |
rpaulo |
Fix several standard extended feature bits.
Submitted by: Oliver Pinter <oliver.pntr at gmail.com>
|
#
249601 |
|
18-Apr-2013 |
rpaulo |
Print RDSEED, ADX, and SMAP.
Pointed out by: kib
|
#
249577 |
|
17-Apr-2013 |
rpaulo |
Print more bits from the standard extended features CPUID which will be available in the Haswell architecture (c.f. Intel Document #319433-012A).
|
#
242828 |
|
09-Nov-2012 |
kib |
Do not try to enable new features in the %cr4 if running under hypervisor. Apparently, hypervisors failed to filter out 'Standard Extended Features' report from CPUID, but deliver #gp when corresponding bit in %cr4 is toggled.
This shall be reconsidered later, after hypervisors correct the bug.
Reported and tested by: joel Reviewed by: avg MFC after: 2 weeks
|
#
242432 |
|
01-Nov-2012 |
kib |
Provide the reading and display of the Standard Extended Features, introduced with the IvyBridge CPUs. Provide the definitions for new bits in CR3 and CR4 registers.
Tested by: avg, Michael Moll <kvedulv@kvedulv.de> MFC after: 2 weeks
|
#
240773 |
|
21-Sep-2012 |
dim |
After r205013, amd64 and i386 CPU family and model IDs were printed out in hexadecimal, but without any 0x prefix, which can be very misleading.
MFC after: 3 days
|
#
234059 |
|
09-Apr-2012 |
jhb |
Recognize the RDRAND instruction feature.
Submitted by: Michael Fuckner michael fuckner net MFC after: 3 days
|
#
222043 |
|
17-May-2011 |
jkim |
Update CPUID bits to reflect AMD Bulldozer and Intel Sandy Bridge features. Note AMD dropped SSE5 extensions in order to avoid ISA overlap with Intel AVX instructions. The SSE5 bit was recycled as XOP extended instruction bit, CVT16 was deprecated in favor of F16C (half-precision float conversion instructions for AVX), and the remaining FMA4 (4-operand FMA instructions) gained a separate CPUID bit. Replace non-existent references with today's CPUID specifications.
|
#
221188 |
|
28-Apr-2011 |
jkim |
Define "Hypervisor Present" bit. This bit is used by several hypervisors to identify CPUs running under emulation. Currently QEMU-KVM, Xen-HVM, VMware, and MS Hyper-V are known to set this bit.
MFC after: 3 days
|
#
220579 |
|
12-Apr-2011 |
jkim |
Probe capability to find effective frequency. When the TSC is P-state invariant, APERF/MPERF ratio can be used to find effective frequency.
|
#
220018 |
|
26-Mar-2011 |
jkim |
Improve CPU identifications of various IDT/Centaur/VIA, Rise and Transmeta CPUs. These CPUs need explicit MSR configuration to expose ceratin CPU capabilities (e.g., CMPXCHG8B) to work around compatibility issues with ancient software. Unfortunately, Rise mP6 does not set the CX8 bit in CPUID and there is no MSR to expose the feature although all mP6 processors are capable of CMPXCHG8B according to datasheets I found from the Net. Clean up and simplify VIA PadLock detection while I am in the neighborhood.
|
#
219461 |
|
10-Mar-2011 |
jkim |
Deprecate rarely used tsc_is_broken. Instead, we zero out tsc_freq because it is almost always used with tsc_freq any way.
|
#
216276 |
|
07-Dec-2010 |
jkim |
Remove stale comments about P-state invariant TSC and fix style(9) nits.
|
#
216275 |
|
07-Dec-2010 |
jkim |
Do not register a event handler for CPU freqency changes when it is found P-state invariant. This is continuation of r216274.
|
#
216272 |
|
07-Dec-2010 |
jkim |
Probe P-state invariant TSC from rightful place.
|
#
213452 |
|
05-Oct-2010 |
kib |
Display PCID capability of CPU and add CPUID define for it.
MFC after: 1 week
|
#
210369 |
|
22-Jul-2010 |
kib |
When compat32 binary asks for the value of hw.machine_arch, report the name of 32bit sibling architecture instead of the host one. Do the same for hw.machine on amd64.
Add a safety belt debug.adaptive_machine_arch sysctl, to turn the substitution off.
Reviewed by: jhb, nwhitehorn MFC after: 2 weeks
|
#
207676 |
|
05-May-2010 |
kib |
Add definitions for Intel AESNI CPUID bits and print the capabilities on boot.
Hardware provided by: Sentex Communications MFC after: 1 week
|
#
205013 |
|
11-Mar-2010 |
jhb |
Print out the family and model from the cpu_id. This is especially useful given the advent of the extended family and extended model fields. The values are printed in hex to match their common usage in documentation.
Submitted by: Alexander Best MFC after: 1 week
|
#
204309 |
|
25-Feb-2010 |
attilio |
Introduce the new kernel sub-tree x86 which should contain all the code shared and generalized between our current amd64, i386 and pc98.
This is just an initial step that should lead to a more complete effort. For the moment, a very simple porting of cpufreq modules, BIOS calls and the whole MD specific ISA bus part is added to the sub-tree but ideally a lot of code might be added and more shared support should grow.
Sponsored by: Sandvine Incorporated Reviewed by: emaste, kib, jhb, imp Discussed on: arch MFC: 3 weeks
|
#
199968 |
|
30-Nov-2009 |
avg |
x86 cpu features: add MOVBE reporting and flag
The check is glimpsed from Linux and OpenSolaris. MOVBE instruction is found in Intel Atom processors.
|
#
198950 |
|
05-Nov-2009 |
attilio |
Strip from messages for users external URLs the project cannot directly control.
Requested by: kib, rwatson
|
#
198868 |
|
04-Nov-2009 |
attilio |
Opteron rev E family of processor expose a bug where, in very rare ocassions, memory barriers semantic is not honoured by the hardware itself. As a result, some random breakage can happen in uninvestigable ways (for further explanation see at the content of the commit itself).
As long as just a specific familly is bugged of an entire architecture is broken, a complete fix-up is impratical without harming to some extents the other correct cases. Considering that (and considering the frequency of the bug exposure) just print out a warning message if the affected machine is identified.
Pointed out by: Samy Al Bahra <sbahra at repnop dot org> Help on wordings by: jeff MFC: 3 days
|
#
197070 |
|
10-Sep-2009 |
jkim |
Consolidate CPUID to CPU family/model macros for amd64 and i386 to reduce unnecessary #ifdef's for shared code between them.
|
#
195188 |
|
30-Jun-2009 |
avg |
remove unused/unneeded extern declarations
This should result in no changes to compiled code.
Reviewed by: alc Approved by: re (kib) MFC after: 1 day
|
#
191788 |
|
04-May-2009 |
jkim |
Unlock the largest standard CPUID on Intel CPUs for both amd64 and i386 and fix SMP topology detection. On i386, we extend it to cover Core, Core 2, and Core i7 processors, not just Pentium 4 family, and move it to better place. On amd64, all supported Intel CPUs should have this MSR.
|
#
191648 |
|
29-Apr-2009 |
jeff |
- Add support for cpuid leaf 0xb. This allows us to determine the topology of nehalem/corei7 based systems. - Remove the cpu_cores/cpu_logical detection from identcpu. - Describe the layout of the system in cpu_mp_announce().
Sponsored by: Nokia
|
#
187598 |
|
22-Jan-2009 |
jkim |
VIA Nano processor has a special MSR (CENT_HARDWARECTRL3) bit 32 to determine whether TSC is P-state invariant or not. In fact, this MSR is writable but we just leave it at the BIOS default for now.
|
#
187109 |
|
12-Jan-2009 |
jkim |
Add basic amd64 support for VIA Nano processors.
|
#
186797 |
|
05-Jan-2009 |
jkim |
Add Centaur/IDT/VIA vendor ID for Nano family, which has long mode support.
|
#
186009 |
|
12-Dec-2008 |
jkim |
Add more CPUID bits from AMD CPUID Specification Rev. 2.28.
|
#
185460 |
|
30-Nov-2008 |
mav |
According to "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2", CPUs with family 0x6 and model above or 0xE and CPUs with family 0xF and model above or 0x3 have invariant TSC.
|
#
185343 |
|
26-Nov-2008 |
jkim |
Use newly introduced cpu_vendor_id to make invariant TSC detection more clearer and merge r185295 to amd64.
|
#
185341 |
|
26-Nov-2008 |
jkim |
Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").
Reviewed by: jhb, peter (early amd64 version)
|
#
184169 |
|
22-Oct-2008 |
jkim |
Add AMD Family 0Fh, Model 6Bh, Stepping 2 to the list of invariant TSCs and fix i386 test.
|
#
184146 |
|
22-Oct-2008 |
jkim |
Set kern.timecounter.invariant_tsc to 1 for AMD CPU family 10h and higher even if BIOS does not advertise it.
|
#
184102 |
|
21-Oct-2008 |
jkim |
Turn off CPU frequency change notifiers when the TSC is P-state invariant or it is forced by setting 'kern.timecounter.invariant_tsc' tunable to non-zero.
|
#
184101 |
|
21-Oct-2008 |
jkim |
Detect Advanced Power Management Information for AMD CPUs.
|
#
183151 |
|
18-Sep-2008 |
stas |
- Recognize SAVE and OSXSAVE extended processor features.
Approved by: kib (mentor) MFC after: 1 month
|
#
179229 |
|
23-May-2008 |
alc |
The VM system no longer uses setPQL2(). Remove it and its helpers.
|
#
176734 |
|
02-Mar-2008 |
jeff |
- Remove the old smp cpu topology specification with a new, more flexible tree structure that encodes the level of cache sharing and other properties. - Provide several convenience functions for creating one and two level cpu trees as well as a default flat topology. The system now always has some topology. - On i386 and amd64 create a seperate level in the hierarchy for HTT and multi-core cpus. This will allow the scheduler to intelligently load balance non-uniform cores. Presently we don't detect what level of the cache hierarchy is shared at each level in the topology. - Add a mechanism for testing common topologies that have more information than the MD code is able to provide via the kern.smp.topology tunable. This should be considered a debugging tool only and not a stable api.
Sponsored by: Nokia
|
#
175905 |
|
02-Feb-2008 |
das |
Add a few more CPUID feature bits while here. We don't support these features yet.
|
#
175904 |
|
02-Feb-2008 |
das |
SSE4 CPUID bits
|
#
174452 |
|
08-Dec-2007 |
alc |
Recognize architectural support for 1GB virtual pages.
MFC after: 6 weeks
|
#
170135 |
|
30-May-2007 |
des |
MFi386: PDCM, remove pointless message
MFC after: 3 days
|
#
167905 |
|
26-Mar-2007 |
njl |
Add an interface for drivers to be notified of changes to CPU frequency. cpufreq_pre_change is called before the change, giving each driver a chance to revoke the change. cpufreq_post_change provides the results of the change (success or failure). cpufreq_levels_changed gives the unit number of the cpufreq device whose number of available levels has changed. Hook in all the drivers I could find that needed it.
* TSC: update TSC frequency value. When the available levels change, take the highest possible level and notify the timecounter set_cputicker() of that freq. This gets rid of the "calcru: runtime went backwards" messages. * identcpu: updates the sysctl hw.clockrate value * Profiling: if profiling is active when the clock changes, let the user know the results may be inaccurate.
Reviewed by: bde, phk MFC after: 1 month
|
#
167744 |
|
20-Mar-2007 |
jkim |
- Add macros for newly added CPUID bits in the corresponding header files. - Use correct capticalization in xTPR as Intel uses in their documents. - Use proper description instead of vendor code name in comment.
|
#
167741 |
|
20-Mar-2007 |
jhb |
MFi386 1.173: Display two new Intel feature bits.
|
#
167493 |
|
12-Mar-2007 |
jkim |
Add another CPUID for AMD CPUs and fix style(9) while I am here.
|
#
165918 |
|
09-Jan-2007 |
jkim |
Add SSSE3 extensions and correct CNXT-ID spelling for Intel processors.
|
#
160869 |
|
01-Aug-2006 |
obrien |
Correct spelling of 3DNow!.
|
#
160286 |
|
12-Jul-2006 |
jkim |
Add two new CPUID bits for AMD CPUs, i. e., SVM and extended APIC register.
|
#
158004 |
|
24-Apr-2006 |
jkim |
Add another Intel CPU feature flag, xTPR (Send Task Priority Messages).
|
#
158003 |
|
24-Apr-2006 |
jkim |
Check if deterministic cache parameters leaf is valid before use.
|
#
155720 |
|
15-Feb-2006 |
dwmalone |
It seems bit 5 of cpu_feature2 is the VMX (Virtual Machine Extensions) bit. While I'm here, delete a comment that was cut and past from the cpu_features code that doesn't belong here.
|
#
153947 |
|
01-Jan-2006 |
netchild |
Unbreak kernel build.
A happy new year to all.
Submitted by: Goran Gajic <ggajic@afrodita.rcub.bg.ac.yu>, bz Pointy hat to: netchild Appologies to: all
|
#
153940 |
|
31-Dec-2005 |
netchild |
MI changes: - provide an interface (macros) to the page coloring part of the VM system, this allows to try different coloring algorithms without the need to touch every file [1] - make the page queue tuning values readable: sysctl vm.stats.pagequeue - autotuning of the page coloring values based upon the cache size instead of options in the kernel config (disabling of the page coloring as a kernel option is still possible)
MD changes: - detection of the cache size: only IA32 and AMD64 (untested) contains cache size detection code, every other arch just comes with a dummy function (this results in the use of default values like it was the case without the autotuning of the page coloring) - print some more info on Intel CPU's (like we do on AMD and Transmeta CPU's)
Note to AMD owners (IA32 and AMD64): please run "sysctl vm.stats.pagequeue" and report if the cache* values are zero (= bug in the cache detection code) or not.
Based upon work by: Chad David <davidc@acns.ab.ca> [1] Reviewed by: alc, arch (in 2004) Discussed with: alc, Chad David, arch (in 2004)
|
#
152537 |
|
17-Nov-2005 |
obrien |
Fix spelling mistake.
Submitted by: kris
|
#
151431 |
|
17-Oct-2005 |
jkim |
Redo physical/logical CPU count.
Suggested by: jhb
|
#
151418 |
|
17-Oct-2005 |
jkim |
Split displaying number of physical and logical cores.
|
#
151375 |
|
16-Oct-2005 |
obrien |
For AMD processors, nullify CPUID.HTT. FreeBSD has no need for the information it conveys, and it is only confusing people. This fixes incorrect output in the previous commit.
|
#
151348 |
|
14-Oct-2005 |
jkim |
- Print number of physical/logical cores and more CPUID info. - Add newer CPUID definitions for future use.
Many thanks to Mike Tancsa <mike at sentex dot net> for providing test cases for Intel Pentium D and AMD Athlon 64 X2.
Approved by: anholt (mentor)
|
#
146767 |
|
29-May-2005 |
schweikh |
Chop a '>' in a feature name (RSVD2>) that snuck in; this now balances the <> flags displayed at boot, e.g. without this Features2=0x41d<SSE3,RSVD2>,MON,DS_CPL,CNTX-ID>
MFC after: 1 week
|
#
140553 |
|
21-Jan-2005 |
peter |
MFi386: whitespace, copyright header, etc updates
|
#
130227 |
|
08-Jun-2004 |
peter |
Argh. Remove stray number that slipped into the previous commit.
|
#
130224 |
|
08-Jun-2004 |
peter |
Initial PG_NX support (no-execute page bit) - export the rest of the cpu features (and amd's features). - turn on EFER_NXE, depending on the NX amd feature bit - reorg the identcpu stuff a bit in order to stop treating the amd features as second class features (since it is now a primary feature bit set) and make it easier to export.
|
#
130032 |
|
03-Jun-2004 |
peter |
MFi386: move cpu_nameclass struct next to its only consumer
|
#
127974 |
|
07-Apr-2004 |
peter |
Update to include both the L1 and L2 TLB stats, as well as the seperate 2M/4M page TLB vs 4K page TLB stats. This also applies to the i386 platform, as does the cpu features fixes.
|
#
127391 |
|
25-Mar-2004 |
peter |
Run print_AMD_features() for both AuthenticAMD and GenuineIntel cpus. Report the %ecx bits in cpuid function 1. This is a hack. When reporting AMD Features, only mask off the common bits. Otherwise the SEP bit masks off SYSCALL etc in the report.
|
#
126677 |
|
06-Mar-2004 |
peter |
When faced with a "GenuineIntel", we know what they call it now. Replace snide comment with a different one.
|
#
122940 |
|
21-Nov-2003 |
peter |
Cosmetic and/or trivial sync up with i386.
Approved by: re (rwatson)
|
#
122849 |
|
17-Nov-2003 |
peter |
Initial landing of SMP support for FreeBSD/amd64.
- This is heavily derived from John Baldwin's apic/pci cleanup on i386. - I have completely rewritten or drastically cleaned up some other parts. (in particular, bootstrap) - This is still a WIP. It seems that there are some highly bogus bioses on nVidia nForce3-150 boards. I can't stress how broken these boards are. I have a workaround in mind, but right now the Asus SK8N is broken. The Gigabyte K8NPro (nVidia based) is also mind-numbingly hosed. - Most of my testing has been with SCHED_ULE. SCHED_4BSD works. - the apic and acpi components are 'standard'. - If you have an nVidia nForce3-150 board, you are stuck with 'device atpic' in addition, because they somehow managed to forget to connect the 8254 timer to the apic, even though its in the same silicon! ARGH! This directly violates the ACPI spec.
|
#
118031 |
|
25-Jul-2003 |
obrien |
Use __FBSDID().
Brought to you by: a boring talk at Ottawa Linux Symposium
|
#
115358 |
|
27-May-2003 |
peter |
Update AMD Features vector to include NX (page table entry no-execute bit) and LM (long mode) etc.
|
#
114923 |
|
11-May-2003 |
peter |
Call it an AMD64 Processor, not a Hammer. Also, it seems that the cpuid model numbers are wider than I first thought.
Approved by: re (blanket amd64/*)
|
#
114349 |
|
01-May-2003 |
peter |
Commit MD parts of a loosely functional AMD64 port. This is based on a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to attempt to get a stable base to start from. There is a lot missing still. Worth noting: - The kernel runs at 1GB in order to cheat with the pmap code. pmap uses a variation of the PAE code in order to avoid having to worry about 4 levels of page tables yet. - It boots in 64 bit "long mode" with a tiny trampoline embedded in the i386 loader. This simplifies locore.s greatly. - There are still quite a few fragments of i386-specific code that have not been translated yet, and some that I cheated and wrote dumb C versions of (bcopy etc). - It has both int 0x80 for syscalls (but using registers for argument passing, as is native on the amd64 ABI), and the 'syscall' instruction for syscalls. int 0x80 preserves all registers, 'syscall' does not. - I have tried to minimize looking at the NetBSD code, except in a couple of places (eg: to find which register they use to replace the trashed %rcx register in the syscall instruction). As a result, there is not a lot of similarity. I did look at NetBSD a few times while debugging to get some ideas about what I might have done wrong in my first attempt.
|
#
114291 |
|
30-Apr-2003 |
markm |
Warns fixing. Protect against inappropriate linting, and mark GCC-specific assemble code as such (in #ifdefs). Fix an easy static variable warning while I'm here.
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#
113321 |
|
10-Apr-2003 |
wes |
Add a sysctl that records and reports the CPU clock rate calculated at boot. Funny how often this trivial piece of information crops up in embedded boxen.
Sponsored by: St. Bernard Software
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#
113090 |
|
04-Apr-2003 |
des |
Define ovbcopy() as a macro which expands to the equivalent bcopy() call, to take care of the KAME IPv6 code which needs ovbcopy() because NetBSD's bcopy() doesn't handle overlap like ours.
Remove all implementations of ovbcopy().
Previously, bzero was a function pointer on i386, to save a jmp to bzero_vector. Get rid of this microoptimization as it only confuses things, adds machine-dependent code to an MD header, and doesn't really save all that much.
This commit does not add my pagezero() / pagecopy() code.
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#
112367 |
|
18-Mar-2003 |
phk |
Including <sys/stdint.h> is (almost?) universally only to be able to use %j in printfs, so put a newsted include in <sys/systm.h> where the printf prototype lives and save everybody else the trouble.
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#
111638 |
|
27-Feb-2003 |
jhb |
Expand some #ifdef's to fix I386_CPU compile.
Reported by: Andy Farkas <andyf@speednet.com.au>
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#
110039 |
|
29-Jan-2003 |
phk |
Make tsc_freq a 64bit quantity.
Inspired by: http://www.theinquirer.net/?article=7481
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#
109696 |
|
22-Jan-2003 |
jhb |
Rename cpuid_cpuinfo to cpu_procinfo. bde requested that I rename this variable to something in the cpu_* namespace since that's what all the other cpuid variables were named and cpu_procinfo is what I came up with.
Requested by: bde
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#
109027 |
|
09-Jan-2003 |
jhb |
Remove earlysetcpuclass() as it has been OBE.
Suggested by: bde
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#
109026 |
|
09-Jan-2003 |
jhb |
Rework part of the previous processor name changes so that we read cpu_exthigh and cpu_brand in printcpuinfo() instead of in identify_cpu(). We also only do it for known-good values of cpu_vendor which is a bit more conservative.
Reviewed by: bde (mostly)
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#
108961 |
|
08-Jan-2003 |
jhb |
Consistently use spaces in between arguments to strcmp(). Whitespace only.
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#
108948 |
|
08-Jan-2003 |
jhb |
- Use cpu_exthigh instead of executing cpuid again to retrieve it for the print_AMD_foo() functions. - Add a brand name table for the brand index provided on Intel CPU's in %ebx after cpuid 1. - For Intel CPUs, if we don't get a processor name from the extended cpuid then use the brand index in cpuid_cpuinfo to pick a name from the brand table and copy that name into cpu_brand. - Replace the duplicated code to use the extended cpuid to replace cpu_model with the processor name in the AMD and Transmeta sections of printcpuinfo() with generic code that replaces cpu_model with cpu_brand if cpu_brand is not an empty string. We also trim leading spaces from cpu_brand prior to doing this since at least some processor names (notably those of Intel CPUs) have leading spaces in the name. - Give print_AMD_features() its own private regs[] array since printcpuinfo() doesn't use the one it has anymore.
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#
108946 |
|
08-Jan-2003 |
jhb |
Bah, get the test for more than one logical CPU right so we don't bogusly claim a CPU has HT support when it lists 0 or 1 logical CPU's per physical processor.
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#
108913 |
|
08-Jan-2003 |
jhb |
If the boot processor supports hyperthreading and contains more than one logical CPU, display the number of logical CPUs per physical processor underneath the list of CPU features.
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#
108608 |
|
03-Jan-2003 |
jhb |
Document bit 31 of the cpuid features word as PBE (Pending Break Enable).
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#
102934 |
|
04-Sep-2002 |
phk |
Change the support for AMDs ElanSC520 CPU from being a device driver to be options CPU_ELAN (NB: Soekris.com users!)
It is cleaner this way. We still recognize the cpu on the host-pci bridge.
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#
101879 |
|
14-Aug-2002 |
jmallett |
Document why the has_f00f_bug variable is initialised rather than placed into the BSS (so that it can be binary-patched).
Inspired by: bde
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#
101054 |
|
31-Jul-2002 |
phk |
The Elan SC520 MMCR is actually 16bit wide, so u_char is inconvenient.
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#
100321 |
|
18-Jul-2002 |
phk |
Add initialization code for the AMD Elan sc520 which maps the MMCR into KVM and sets the i8254 frequency to the correct value.
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#
95579 |
|
27-Apr-2002 |
alc |
For what it's worth, fix the compilation of an I386_CPU-only kernel now that certain warnings are fatal.
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#
91640 |
|
04-Mar-2002 |
iwasaki |
Add generalized power profile code. This makes other power-management system (APM for now) to be able to generate power profile change events (ie. AC-line status changes), and other kernel components, not only the ACPI components, can be notified the events.
- move subroutines in acpi_powerprofile.c (removed) to kern/subr_power.c - call power_profile_set_state() also from APM driver when AC-line status changes - add call-back function for Crusoe LongRun controlling on power profile changes for a example
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#
90960 |
|
20-Feb-2002 |
cjc |
Fix typos in some comments.
PR: i386/35114 Submitted by: Gavin Atkinson <gavin.atkinson@ury.york.ac.uk>
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#
90589 |
|
12-Feb-2002 |
dwmalone |
Move do_cpuid() from a identcpu.c into cpufunc.h.
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#
90468 |
|
10-Feb-2002 |
kato |
Cosmetic changes: - Collected i486 identification codes in one place like 586 and 686. - Merged two cases (0x470 and 0x490) for `Enhanced Am486DX4 Write-Back.' - Replaced `unknown' into `Unknown'.
Submitted by: chi@bd.mbn.or.jp (Chiharu Shibata)
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#
90425 |
|
09-Feb-2002 |
kato |
Recognize VIA C3 Samuel 2.
MFC after: 3 days
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#
89631 |
|
22-Jan-2002 |
peter |
List bit 18 (reserved, apparently present on thunderbird cpus) and bit 19 (athlon XP/MP rev 0x662 and later) for amd_features.
Submitted by: dwcjr
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#
89412 |
|
16-Jan-2002 |
peter |
Change <b28> to HTT (Hyperthreading technology). If this flag is set then cpuid with %eax=1 will return a logical cpu count in bits 16-23 of %ebx. Bit 29 is actually 'TM' according to AP-485. This signifies the presence of the thermal control circuit (which I believe can slow the clock down to reduce core temperature).
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#
87122 |
|
30-Nov-2001 |
peter |
cpuid bit 30 is 'IA64', for when you're running in i386 mode on an ia64 cpu. (This is for either userland apps running in i386 mode on an ia64 OS, or when the cpu is in i386 legacy mode running an i386 OS).
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#
84850 |
|
12-Oct-2001 |
jdp |
Correct the input/output/clobber specifications for the cpuid instruction. Stefan Keller <dres@earth.serd.org> noticed that CPU identification was broken when compiled with -O2, and tracked it down to the asm statement, which was storing values into memory without specifying that memory was modified. He submitted a patch which added "memory" as a clobber, but I refined it further to arrive at this version.
MFC after: 3 days
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#
83275 |
|
10-Sep-2001 |
peter |
gcc-3 has objections about the bluetrap6 and bluetrap13 inline asm functions. Apparently multi-line string asm arguments are deprecated.
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#
79137 |
|
03-Jul-2001 |
iwasaki |
Add Transmeta Crusoe LongRun support.
Submitted by: Tamotsu HATTORI <athlete@kta.att.ne.jp> Reviewed by: arch@ folks MFC after: 1 week
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#
78798 |
|
26-Jun-2001 |
kato |
Recognize FC-PGA2 Pentium III (Tualatin).
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#
78760 |
|
25-Jun-2001 |
dfr |
Add code to detect Transmeta Crusoe cpus.
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#
71098 |
|
16-Jan-2001 |
peter |
Stop doing runtime checking on i386 cpus for cpu class. The cpu is slow enough as it is, without having to constantly check that it really is an i386 still. It was possible to compile out the conditionals for faster cpus by leaving out 'I386_CPU', but it was not possible to unconditionally compile for the i386. You got the runtime checking whether you wanted it or not. This makes I386_CPU mutually exclusive with the other cpu types, and tidies things up a little in the process.
Reviewed by: alfred, markm, phk, benno, jlemon, jhb, jake, grog, msmith, jasone, dcs, des (and a bunch more people who encouraged it)
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#
69006 |
|
21-Nov-2000 |
markm |
Assembler fixes.
Fix opcodes that were typed as ".byte 0xNN, 0xMM" when an older assembler could not recognise the newer Pentium instructions. Reviewed by: jhb
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#
67882 |
|
29-Oct-2000 |
phk |
Remove unneeded #include <sys/proc.h> lines.
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#
66442 |
|
29-Sep-2000 |
peter |
Fill in some more missing bits from cpu_features according to the Intel Pentium4 cpuid docs.
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#
66441 |
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29-Sep-2000 |
peter |
First shot at identifying the Pentum 4 acording to our reading of the the cpu_id extensions in the Intel docs. There is more info available. See the following URL for more details. http://developer.intel.com/design/processor/future/manuals/CPUID_Supplement.htm
Requested by: Intel
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#
66407 |
|
27-Sep-2000 |
asmodai |
Fix spelling of Katmai [Katami].
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#
66383 |
|
26-Sep-2000 |
kato |
Recognize new Pentium III Xeon (stepping A0).
PR: 21233 Submitted by: ade
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#
65557 |
|
07-Sep-2000 |
jasone |
Major update to the way synchronization is done in the kernel. Highlights include:
* Mutual exclusion is used instead of spl*(). See mutex(9). (Note: The alpha port is still in transition and currently uses both.)
* Per-CPU idle processes.
* Interrupts are run in their own separate kernel threads and can be preempted (i386 only).
Partially contributed by: BSDi (BSD/OS) Submissions by (at least): cp, dfr, dillon, grog, jake, jhb, sheldonh
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#
61623 |
|
13-Jun-2000 |
kato |
Recognize Coppermine Celeron processors whose CPU ID = 0x68?. They were recognized as "Pentium III/Pentium III Xeon."
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#
59926 |
|
03-May-2000 |
dwhite |
I mentioned yesterday that I could use some work, and Kelly says, "Commit my PRs!" So here I go.
Add definitions for some of the AMD CPU feature bits. Also add a comment on where to find the rest of them. This is a purely cosmetic change.
PR: i386/14438 Submitted by: Kelly Yancey <kbyanc@egroups.net>
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#
56797 |
|
29-Jan-2000 |
kato |
Simplify messages of Pentium II, Pentium II Xeon, Celeron, Pentium III and Pentium III Xeon CPUs. If a CPU is one of Pentium II, Pentium II Xeon and Celeron, the message is always "Pentium II/Pentium II Xeon/Celeron". If a CPU is one of Pentium III and Pentium III Xeon, the message is always "Pentium III/Pentium III Xeon".
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#
56024 |
|
15-Jan-2000 |
tanimura |
A processor with the CPUID of 0x?8? is Pentium III. (aka Coppermine)
Noticed by: Satoshi Sawada <k-sawata@gnoc2.comminet.or.jp> Reviewd by: Takuma Yamada <fuzzy2@st.rim.or.jp>
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#
52469 |
|
24-Oct-1999 |
alc |
Add text for the Athlon's MMX and 3DNow! (DSP) instruction extensions to print_AMD_features.
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#
52237 |
|
14-Oct-1999 |
kato |
Recognize Pentium II w/ CPUID = 0x6XX and Pentium III Xeon w/ CPUID = 0x7XX.
Pointed out by: Brian Somers <brian@Awfulhak.org>
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#
51561 |
|
22-Sep-1999 |
luoqi |
Display CPU (BSP) clock speed on SMP systems.
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#
51130 |
|
10-Sep-1999 |
phk |
System clock don't update, because C6's TSC stop count up when run HALT instruction.
PR: 13683 Submitted by: IMAI Takeshi <take-i@ceres.dti.ne.jp> Reviewed by: phk
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#
51126 |
|
10-Sep-1999 |
peter |
Add text for the PN (Processor serial number) and XMM (extended SIMD/MMX2/ support), as well as a bunch of comments for what the various bits mean (those that I remember anyway).
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#
50477 |
|
28-Aug-1999 |
peter |
$Id$ -> $FreeBSD$
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#
50081 |
|
20-Aug-1999 |
kato |
There may exist two kinds of IBM BlueLightning CPU. One is that 5/2 test does not change undefined flag like Cyrix CPUs. Another is that 5/2 test changes undefined flag like Intel CPUs. Latter one could not be detected and was recognized 486DX CPU. To solve this, finishidentcpu() calls identblue() when cpu_vendor is null string (that is, CPUID instruction is not supported) and cpu == CPU_486. Tests have been done on IBM BlueLightning CPUs, i486SX and i486DX.
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#
48636 |
|
06-Jul-1999 |
peter |
Quieten gcc paranoia.
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#
48632 |
|
06-Jul-1999 |
peter |
Typo: s/0ff0/0xff0/
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#
48618 |
|
06-Jul-1999 |
green |
Add Centaur/IDT WinChip support.
Why in the world do people put breaks at the end of a switch's default case?
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#
48615 |
|
06-Jul-1999 |
green |
I made some cleanups, rearranged things a bit, and made AMD Features default printing on CPUs that have it. If there are no objections, I'll MFC all recent changes (harmless, really) to 3.2 and PAO.
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#
48572 |
|
05-Jul-1999 |
green |
Add an extra space to " AMD Features=" to make it line up well.
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#
48571 |
|
05-Jul-1999 |
green |
K6-III CPUs are now case:d in the appropriate switch; also, in print_AMD_info(), L2 internal cache is shown, as are AMD's special CPUID infos:
CPU: AMD-K6(tm) 3D processor (350.81-MHz 586-class CPU) Origin = "AuthenticAMD" Id = 0x58c Stepping=12 Features=0x8021bf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8,PGE,MMX> AMD Features=0x808029bf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8,SYSCALL,PGE,MMX,3DNow!>
PR: kern/12512 Submitted by: Louis A. Mamakos <louie@TransSys.COM>
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#
48200 |
|
24-Jun-1999 |
jlemon |
Only include AMD wt_alloc routines if I586_CPU is defined. Fixes CPU_WT_ALLOC for cyrix chips.
Submitted by: "Brian Smith" <dbsoft@technologist.com>
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#
48160 |
|
24-Jun-1999 |
green |
This commit gives support for the Rise mP6 CPU. It has two changes: 1. Rise is recognized in identdcpu.c. 2. The TSC is not written to. A workaround for the CPU bug is being applied to clock.c (the bug being that the mP6 has TSC enabled in its CPUID-capabilities, but it only supports reading it. If we try to write to it (MSR 16), a GPF occurs.) The new behavior is that FreeBSD will _not_ zero the TSC. Instead, we do a bit of 64-bit arithmetic.
Reviewed by: msmith Obtained from: unfurl & msmith
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#
47592 |
|
29-May-1999 |
phk |
Stop the TSC from being used as timecounter on K5/step0 machines.
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#
46881 |
|
10-May-1999 |
bde |
[Forgot to commit this in the batch a few days ago.]
Fixed profiling of elf kernels. Made high resolution profiling compile for elf kernels (it is broken for all kernels due to lack of egcs support).
Renaming of many assembler labels is avoided by declaring by declaring the labels that need to be visible to gprof as having type "function" and depending on the elf version of gprof being zealous about discarding the others. A few type declarations are still missing, mainly for SMP.
PR: 9413 Submitted by: Assar Westerlund <assar@sics.se> (initial parts)
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#
46381 |
|
03-May-1999 |
billf |
Add sysctl descriptions to many SYSCTL_XXXs
PR: kern/11197 Submitted by: Adrian Chadd <adrian@FreeBSD.org> Reviewed by: billf(spelling/style/minor nits) Looked at by: bde(style)
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#
44645 |
|
10-Mar-1999 |
roberto |
Fix two tests against hex. values for CPUID.
PR: i386/10050 Submitted by: Kevin Day <toasty@dragondata.com>
|
#
44168 |
|
20-Feb-1999 |
roberto |
Bit 24 of the Feature Flag is FXSR (for Fast FP Save and Restore).
Reminded by: Francis Dupont <Francis.Dupont@inria.fr>
|
#
43612 |
|
04-Feb-1999 |
kato |
Recognize Pentium II Xeon, Celeron and Pentium III cpus. Because CPU names are printed on their packages and shown by BIOS, kernel does not need to show details.
PR: 8751, 9320 and 9463
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#
42732 |
|
16-Jan-1999 |
kato |
There are two models of AMD K6-2 Model 8 (c.f. AMD's document), so the CPU stepping must be checked. Also, fixed print_AMD_info.
Submitted by: Akio Morita <amorita@meadow.scphys.kyoto-u.ac.jp>
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#
42428 |
|
09-Jan-1999 |
bde |
Don't put operands in clobber lists, since this is dubious for old versions of gcc and broken for current versions of egcs.
Cleaned up the asm statement for do_cpuid() a little.
Submitted by: "John S. Dyson" <dyson@iquest.net> but rewritten by me
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#
42406 |
|
08-Jan-1999 |
bde |
Moved declarations related to copying and zeroing to the right place.
|
#
42112 |
|
27-Dec-1998 |
msmith |
From the submitter:
CPU_WT_ALLOC does not work correctly for K6-2s of model 8+ and probably K6-3s (when they appear on the market soon). In addition, print_AMD_info() incorrectly printfs write allocation's size. I've fixed them, so they now Do The Right Thing, and added a "NO_MEMORY_HOLE" option to easily allow 15-16mb range handling for us K6 and K6-2 users.
Submitted by: Brian Feldman <green@unixhelp.org>
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#
41541 |
|
05-Dec-1998 |
kato |
Print out information for write-allocate of AMD CPUs.
Submitted by: Akio Morita <amorita@meadow.scphys.kyoto-u.ac.jp>
|
#
40003 |
|
06-Oct-1998 |
kato |
- Implement enabling write allocate on AMD K5/K6/K6-2 cpus. The code was originaly contributed by Kelly Yancey <kbyanc@freedomnet.com> in PR i386/6269 and revised by Akio Morita <amorita@meadow.scphys.kyoto-u.ac.jp> and me. Test was performed by Akio Morita and Toshiomi Moriki <moriki@db.is.kyushu-u.ac.jp>. - Fix stylistic bug in identcpu.c. - Update copyright in initcpu.c - Fix typo in LINT.
PR: 6269 and 6270
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#
37555 |
|
11-Jul-1998 |
bde |
Fixed printf format errors.
|
#
37553 |
|
11-Jul-1998 |
bde |
Don't pretend to support ix86's with 16-bit ints by using longs just to ensure 32-bit variables. Doing so mainly bogotified some printf formats.
Fixed disorder in md_var.h.
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#
37311 |
|
30-Jun-1998 |
phk |
Add PSE36 to the bits we know by name.
|
#
36303 |
|
22-May-1998 |
des |
Use switch instead of if/else chain for 686 model identification. Add precise model identification for 586-family CPUs.
|
#
36286 |
|
21-May-1998 |
des |
Correctly identify the precise CPU model within the 686 family: instead of just printing "Pentium Pro", check the model (cpu_id & 0xf0) and print the appropriate information.
|
#
36200 |
|
19-May-1998 |
peter |
Missing parens caused cpu features not to be printed for cyrix >= M2/MX. Althought the comments say the datasheet doesn't list the device ID registers on the M2/MX, they seem to be there and quite alive. (It's interesting to note that the M2/MX calls itself a 686 class cpu but is missing a heck of a lot of features, including VME, PGE, PSE, etc)
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#
35456 |
|
26-Apr-1998 |
dyson |
Add the PAT cpuid feature.
|
#
35210 |
|
15-Apr-1998 |
bde |
Support compiling with `gcc -ansi'.
|
#
33320 |
|
13-Feb-1998 |
kato |
Use RDMSR instruction instead of WRMSR.
|
#
32820 |
|
27-Jan-1998 |
kato |
Execute cpuid if BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
|
#
32781 |
|
25-Jan-1998 |
kato |
Undo previous commit. The cpuid symbol has been already used by SMP stuff.
Pointed-out by: Manfred Antar <root@mantar.slip.netcom.com>
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#
32771 |
|
25-Jan-1998 |
kato |
Execute cpuid if BIOS disables cpuid instruction of Cyrix 6x86MX CPU, and store its result into cpu_id and cpu_feature variables.
Tested by: Simon Coggins <chaos@ultra.net.au>
|
#
32765 |
|
25-Jan-1998 |
kato |
Even though BIOS writer's guide recommends cpuid instruction of Cyrix 6x86MX CPU is enabled (BIOS should not disable it), some BIOS disables it via CCR4. In this case, cpu variable becomes CPU_486 and identblue() is called. Because Cyrix 6x86MX has MSR and doesn't have MSR1002, wrmsr instruction generates general protection fault.
Tested by: Simon Coggins <chaos@ultra.net.au>
|
#
32203 |
|
03-Jan-1998 |
obrien |
AMD calls the PR166 and PR200, models 2 and 3 respectively.
|
#
32200 |
|
03-Jan-1998 |
obrien |
Update AMD URL for CPU recognition docs.
|
#
32005 |
|
26-Dec-1997 |
phk |
Rename "i586_ctr" to "tsc" (both upper and lower case instances). Fix a couple of printfs too.
Warning: This changes the names of a couple of kernel options!
|
#
31535 |
|
04-Dec-1997 |
jkh |
After consultation with David, change #ifndef NO_F00F_HACK to #if defined(I586_CPU) && !defined(NO_F00F_HACK)
|
#
31507 |
|
03-Dec-1997 |
sef |
Work around for the Intel Pentium F00F bug; this is Intel's recommended workaround. Note that this currently eats up two pages extra in the system; this could be alleviated by aligning idt correctly, and then only dealing with that (as opposed to the current method of allocated two pages and copying the IDT table to that, and then setting that to be the IDT table).
|
#
31016 |
|
07-Nov-1997 |
phk |
Remove a bunch of variables which were unused both in GENERIC and LINT.
Found by: -Wunused
|
#
30976 |
|
06-Nov-1997 |
kato |
Identify MediaGX CPU correctly. Old MeidaGX CPU and GXm CPU are distinguished. CPU-classes of MeidaGX CPU and GXm CPU are 486-class and 586-class, respectively.
PR: 4936
|
#
30964 |
|
05-Nov-1997 |
kato |
Fix rare 6x86 CPU whose DIR0 = 0x20 - 0x28 case.
|
#
30805 |
|
28-Oct-1997 |
bde |
Don't include <machine/cputypes.h> or declare cputype/class interfaces in <machine/cpu.h>. Moved the declarations to <machine/cputypes.h>. Fixed style bugs in the moved code. Fixed everything that depended on the nested include. Don't include <machine/cpu.h> (in the changed files) unless something in it is used directly.
|
#
30082 |
|
03-Oct-1997 |
kato |
Call identifycyrix() when 6x86MX CPU is found. The identifycyrix() function sets cyrix_did. Old code could not display correct variable.
Reviewed by: Hideyuki Suzuki <hideyuki@sat.t.u-tokyo.ac.jp>
|
#
29639 |
|
20-Sep-1997 |
phk |
For AMD chips, pick up the long description from the chip if possible. (This is not really a typographical improvement in the case of the K6 it seems, but AMD appearantly want it too look that way). Also if bootverbose, dump some more info about the chip.
|
#
27654 |
|
24-Jul-1997 |
kato |
Treat 6x86MX CPU as 686-class CPU instead of 586-class CPU.
|
#
27535 |
|
20-Jul-1997 |
bde |
Removed unused #includes.
|
#
26888 |
|
24-Jun-1997 |
kato |
Recognize AMD K5 PR166 and PR200 CPUs.
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26388 |
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02-Jun-1997 |
peter |
Fill in some gaps in the cpuid features list.. bit 10 is the old bit for MTRR (presumably this changed, an older P5 I have has got it, the newer cpus have the new MTRR bit set) bit 11 is SEP (fast syscalls), bit 23 is MMX Fill in the other reserved ones with a stub so that we can see them if they turn up.
Obtained from: Intel AP-485 rev.06
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26373 |
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02-Jun-1997 |
dfr |
Move interrupt handling code from isa.c to a new file. This should make isa.c (slightly) more portable and will make my life developing the really portable version much easier.
Reviewed by: peter, fsmp
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26298 |
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31-May-1997 |
kato |
- Use `6x86MX' instead of `M2'. Cyrix officially use `6x86MX' for the CPU code-named `M2'.
- Use the result of cpuid instruction instead of DIR to identify 6x86MX cpu. DIR0 and DIR1 are not documented in the data sheet, and cpuid instruction is enabled at reset time.
- Add a function, init_6x86MX() to initialize 6x86MX cpu. It supports CPU_SUSP_HLT and CPU_IORT options. It always sets NC1 (640K - 1M is not cached.), and enables L1 cache in write-back mode.
- Fix typo in the comment in identblue().
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26037 |
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23-May-1997 |
charnier |
typo (Cyirx -> Cyrix).
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25925 |
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19-May-1997 |
kato |
Recognize AMD 486 CPUs.
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25495 |
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05-May-1997 |
kato |
Use `MediaGX' instead of `Gx86'.
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25494 |
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05-May-1997 |
kato |
Use `M2' instead of `6x86 with MMX'. Cyrix seems to use `M2' officially.
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25164 |
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26-Apr-1997 |
peter |
Man the liferafts! Here comes the long awaited SMP -> -current merge!
There are various options documented in i386/conf/LINT, there is more to come over the next few days.
The kernel should run pretty much "as before" without the options to activate SMP mode.
There are a handful of known "loose ends" that need to be fixed, but have been put off since the SMP kernel is in a moderately good condition at the moment.
This commit is the result of the tinkering and testing over the last 14 months by many people. A special thanks to Steve Passe for implementing the APIC code!
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25159 |
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26-Apr-1997 |
kato |
Add new cpu type, CPU_CY486DX, which shows Cyrix 486S/DX series CPUs, and initialization routine for those CPUs.
Tested by: Bob Bishop <rb@gid.co.uk>
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25083 |
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22-Apr-1997 |
jdp |
Make the necessary changes so that an ELF kernel can be built. I have successfully built, booted, and run a number of different ELF kernel configurations, including GENERIC. LINT also builds and links cleanly, though I have not tried to boot it.
The impact on developers is virtually nil, except for two things. All linker sets that might possibly be present in the kernel must be listed in "sys/i386/i386/setdefs.h". And all C symbols that are also referenced from assembly language code must be listed in "sys/i386/include/asnames.h". It so happens that failure to do these things will have no impact on the a.out kernel. But it will break the build of the ELF kernel.
The ELF bootloader works, but it is not ready to commit quite yet.
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24112 |
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22-Mar-1997 |
kato |
Improved CPU identification and initialization routines. This supports All Cyrix CPUs, IBM Blue Lightning CPU and NexGen (now AMD) Nx586 CPU, and initialize special registers of Cyrix CPU and msr of IBM Blue Lightning CPU.
If revision of Cyrix 6x86 CPU < 2.7, CPU cache is enabled in write-through mode. This can be disabled by kernel configuration options.
Reviewed by: Bruce Evans <bde@freebsd.org> and Jordan K. Hubbard <jkh@freebsd.org>
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22975 |
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22-Feb-1997 |
peter |
Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are not ready for it yet.
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21974 |
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24-Jan-1997 |
obrien |
KNF style police.
Reported by: Bruce Thanks to: Bruce for also providing a diff.
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21857 |
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19-Jan-1997 |
obrien |
Add bits to identify AMD K5 and K6 cpu's. Tested only on my AMD K5 PR-133. Bit values for K6 taken from AMD document on how to test such things.
2.2 Candidate.
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21673 |
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14-Jan-1997 |
jkh |
Make the long-awaited change from $Id$ to $FreeBSD$
This will make a number of things easier in the future, as well as (finally!) avoiding the Id-smashing problem which has plagued developers for so long.
Boy, I'm glad we're not using sup anymore. This update would have been insane otherwise.
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19674 |
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12-Nov-1996 |
bde |
Removed #include of "opt_temporary.h". All the temporary options went away, so this header is no longer generated.
This change should be in 2.2. The old version shouldn;t have been in 2.2 (blush).
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19653 |
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11-Nov-1996 |
bde |
Replaced I586_OPTIMIZED_BCOPY and I586_OPTIMIZED_BZERO with boot-time negative-logic flags (flags 0x01 and 0x02 for npx0, defaulting to unset = on). This changes the default from off to on. The options have been in current for several months with no problems reported.
Added a boot-time negative-logic flag for the old I5886_FAST_BCOPY option which went away too soon (flag 0x04 for npx0, defaulting to unset = on).
Added a boot-time way to set the memory size (iosiz in config, iosize in userconfig for npx0).
LINT: Removed old options. Documented npx0's flags and iosiz.
options.i386: Removed old options.
identcpu.c: Don't set the function pointers here. Setting them has to be delayed until after userconfig has had a chance to disable them and until after a good npx0 has been detected.
machdep.c: Use npx0's iosize instead of MAXMEM if it is nonzero.
support.s: Added vectors and glue code for copyin() and copyout(). Fixed ifdefs for i586_bzero(). Added ifdefs for i586_bcopy().
npx.c: Set the function pointers here. Clear hw_float when an npx exists but is too broken to use. Restored style from a year or three ago in npxattach().
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18842 |
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09-Oct-1996 |
bde |
Put I*86_CPU defines in opt_cpu.h.
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18837 |
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09-Oct-1996 |
bde |
Enable the i586-optimized bcopy if the cpu is a "586" and option I586_OPTIMIZED_BCOPY is configured.
Similarly for bzero/I586_OPTIMIZED_BZERO.
Fake 586's had better have a hardware FPU with non-broken exception handling (we mask exceptions, but broken exception handling may trap on the instructions that do the masking). I guess this means that the routines won't work on most 386's or FPUless 486's even when they have a h/w FPU.
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18084 |
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06-Sep-1996 |
phk |
Remove devconf, it never grew up to be of any use.
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17490 |
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10-Aug-1996 |
peter |
Add recognition for the AMD 5x86 CPU models.
Submitted by: A JOSEPH KOSHY <koshy@india.hp.com>
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17488 |
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10-Aug-1996 |
peter |
Trivial cosmetic tweak to make the i[56]86 CPU MHz reprting round to the nearest .01 Mhz rather than simply truncating it downwards.
This hack makes this 89.999928 Mhz clock correctly round to the closer 90.00-MHz rather than 89.99-MHz: > i586 clock: 89999928 Hz, i8254 clock: 1193152 Hz > CPU: Pentium (90.00-MHz 586-class CPU)
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17395 |
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02-Aug-1996 |
bde |
Eliminated i586_ctr_rate. Use i586_ctr_freq instead.
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17014 |
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08-Jul-1996 |
wollman |
Fix something that's been bugging me for a long time: move the CPU type identification code out of machdep.c and into a new file of its own. Hopefully other grot can be moved out of machdep.c as well (by other people) into more descriptively-named files.
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