identcpu.c revision 191788
1/*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/amd64/amd64/identcpu.c 191788 2009-05-04 18:05:27Z jkim $"); 43 44#include "opt_cpu.h" 45 46#include <sys/param.h> 47#include <sys/bus.h> 48#include <sys/cpu.h> 49#include <sys/eventhandler.h> 50#include <sys/systm.h> 51#include <sys/kernel.h> 52#include <sys/sysctl.h> 53#include <sys/power.h> 54 55#include <machine/asmacros.h> 56#include <machine/clock.h> 57#include <machine/cputypes.h> 58#include <machine/frame.h> 59#include <machine/intr_machdep.h> 60#include <machine/segments.h> 61#include <machine/specialreg.h> 62#include <machine/md_var.h> 63 64#include <amd64/isa/icu.h> 65 66/* XXX - should be in header file: */ 67void printcpuinfo(void); 68void identify_cpu(void); 69void earlysetcpuclass(void); 70void panicifcpuunsupported(void); 71 72static u_int find_cpu_vendor_id(void); 73static void print_AMD_info(void); 74static void print_AMD_assoc(int i); 75static void print_via_padlock_info(void); 76 77int cpu_class; 78char machine[] = "amd64"; 79SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 80 machine, 0, "Machine class"); 81 82static char cpu_model[128]; 83SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 84 cpu_model, 0, "Machine model"); 85 86static int hw_clockrate; 87SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 88 &hw_clockrate, 0, "CPU instruction clock rate"); 89 90static char cpu_brand[48]; 91 92static struct { 93 char *cpu_name; 94 int cpu_class; 95} amd64_cpus[] = { 96 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 97 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 98}; 99 100static struct { 101 char *vendor; 102 u_int vendor_id; 103} cpu_vendors[] = { 104 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 105 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 106 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 107}; 108 109 110extern int pq_l2size; 111extern int pq_l2nways; 112 113void 114printcpuinfo(void) 115{ 116 u_int regs[4], i; 117 char *brand; 118 119 cpu_class = amd64_cpus[cpu].cpu_class; 120 printf("CPU: "); 121 strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model)); 122 123 /* Check for extended CPUID information and a processor name. */ 124 if (cpu_exthigh >= 0x80000004) { 125 brand = cpu_brand; 126 for (i = 0x80000002; i < 0x80000005; i++) { 127 do_cpuid(i, regs); 128 memcpy(brand, regs, sizeof(regs)); 129 brand += sizeof(regs); 130 } 131 } 132 133 switch (cpu_vendor_id) { 134 case CPU_VENDOR_INTEL: 135 /* Please make up your mind folks! */ 136 strcat(cpu_model, "EM64T"); 137 break; 138 case CPU_VENDOR_AMD: 139 /* 140 * Values taken from AMD Processor Recognition 141 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 142 * (also describes ``Features'' encodings. 143 */ 144 strcpy(cpu_model, "AMD "); 145 if ((cpu_id & 0xf00) == 0xf00) 146 strcat(cpu_model, "AMD64 Processor"); 147 else 148 strcat(cpu_model, "Unknown"); 149 break; 150 case CPU_VENDOR_CENTAUR: 151 strcpy(cpu_model, "VIA "); 152 if ((cpu_id & 0xff0) == 0x6f0) 153 strcat(cpu_model, "Nano Processor"); 154 else 155 strcat(cpu_model, "Unknown"); 156 break; 157 default: 158 strcat(cpu_model, "Unknown"); 159 break; 160 } 161 162 /* 163 * Replace cpu_model with cpu_brand minus leading spaces if 164 * we have one. 165 */ 166 brand = cpu_brand; 167 while (*brand == ' ') 168 ++brand; 169 if (*brand != '\0') 170 strcpy(cpu_model, brand); 171 172 printf("%s (", cpu_model); 173 switch(cpu_class) { 174 case CPUCLASS_K8: 175 hw_clockrate = (tsc_freq + 5000) / 1000000; 176 printf("%jd.%02d-MHz ", 177 (intmax_t)(tsc_freq + 4999) / 1000000, 178 (u_int)((tsc_freq + 4999) / 10000) % 100); 179 printf("K8"); 180 break; 181 default: 182 printf("Unknown"); /* will panic below... */ 183 } 184 printf("-class CPU)\n"); 185 if (*cpu_vendor) 186 printf(" Origin = \"%s\"", cpu_vendor); 187 if (cpu_id) 188 printf(" Id = 0x%x", cpu_id); 189 190 if (cpu_vendor_id == CPU_VENDOR_INTEL || 191 cpu_vendor_id == CPU_VENDOR_AMD || 192 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 193 printf(" Stepping = %u", cpu_id & 0xf); 194 if (cpu_high > 0) { 195 196 /* 197 * Here we should probably set up flags indicating 198 * whether or not various features are available. 199 * The interesting ones are probably VME, PSE, PAE, 200 * and PGE. The code already assumes without bothering 201 * to check that all CPUs >= Pentium have a TSC and 202 * MSRs. 203 */ 204 printf("\n Features=0x%b", cpu_feature, 205 "\020" 206 "\001FPU" /* Integral FPU */ 207 "\002VME" /* Extended VM86 mode support */ 208 "\003DE" /* Debugging Extensions (CR4.DE) */ 209 "\004PSE" /* 4MByte page tables */ 210 "\005TSC" /* Timestamp counter */ 211 "\006MSR" /* Machine specific registers */ 212 "\007PAE" /* Physical address extension */ 213 "\010MCE" /* Machine Check support */ 214 "\011CX8" /* CMPEXCH8 instruction */ 215 "\012APIC" /* SMP local APIC */ 216 "\013oldMTRR" /* Previous implementation of MTRR */ 217 "\014SEP" /* Fast System Call */ 218 "\015MTRR" /* Memory Type Range Registers */ 219 "\016PGE" /* PG_G (global bit) support */ 220 "\017MCA" /* Machine Check Architecture */ 221 "\020CMOV" /* CMOV instruction */ 222 "\021PAT" /* Page attributes table */ 223 "\022PSE36" /* 36 bit address space support */ 224 "\023PN" /* Processor Serial number */ 225 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 226 "\025<b20>" 227 "\026DTS" /* Debug Trace Store */ 228 "\027ACPI" /* ACPI support */ 229 "\030MMX" /* MMX instructions */ 230 "\031FXSR" /* FXSAVE/FXRSTOR */ 231 "\032SSE" /* Streaming SIMD Extensions */ 232 "\033SSE2" /* Streaming SIMD Extensions #2 */ 233 "\034SS" /* Self snoop */ 234 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 235 "\036TM" /* Thermal Monitor clock slowdown */ 236 "\037IA64" /* CPU can execute IA64 instructions */ 237 "\040PBE" /* Pending Break Enable */ 238 ); 239 240 if (cpu_feature2 != 0) { 241 printf("\n Features2=0x%b", cpu_feature2, 242 "\020" 243 "\001SSE3" /* SSE3 */ 244 "\002<b1>" 245 "\003DTES64" /* 64-bit Debug Trace */ 246 "\004MON" /* MONITOR/MWAIT Instructions */ 247 "\005DS_CPL" /* CPL Qualified Debug Store */ 248 "\006VMX" /* Virtual Machine Extensions */ 249 "\007SMX" /* Safer Mode Extensions */ 250 "\010EST" /* Enhanced SpeedStep */ 251 "\011TM2" /* Thermal Monitor 2 */ 252 "\012SSSE3" /* SSSE3 */ 253 "\013CNXT-ID" /* L1 context ID available */ 254 "\014<b11>" 255 "\015<b12>" 256 "\016CX16" /* CMPXCHG16B Instruction */ 257 "\017xTPR" /* Send Task Priority Messages*/ 258 "\020PDCM" /* Perf/Debug Capability MSR */ 259 "\021<b16>" 260 "\022<b17>" 261 "\023DCA" /* Direct Cache Access */ 262 "\024SSE4.1" 263 "\025SSE4.2" 264 "\026x2APIC" /* xAPIC Extensions */ 265 "\027<b22>" 266 "\030POPCNT" 267 "\031<b24>" 268 "\032<b25>" 269 "\033XSAVE" 270 "\034OSXSAVE" 271 "\035<b28>" 272 "\036<b29>" 273 "\037<b30>" 274 "\040<b31>" 275 ); 276 } 277 278 /* 279 * AMD64 Architecture Programmer's Manual Volume 3: 280 * General-Purpose and System Instructions 281 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf 282 * 283 * IA-32 Intel Architecture Software Developer's Manual, 284 * Volume 2A: Instruction Set Reference, A-M 285 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf 286 */ 287 if (amd_feature != 0) { 288 printf("\n AMD Features=0x%b", amd_feature, 289 "\020" /* in hex */ 290 "\001<s0>" /* Same */ 291 "\002<s1>" /* Same */ 292 "\003<s2>" /* Same */ 293 "\004<s3>" /* Same */ 294 "\005<s4>" /* Same */ 295 "\006<s5>" /* Same */ 296 "\007<s6>" /* Same */ 297 "\010<s7>" /* Same */ 298 "\011<s8>" /* Same */ 299 "\012<s9>" /* Same */ 300 "\013<b10>" /* Undefined */ 301 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 302 "\015<s12>" /* Same */ 303 "\016<s13>" /* Same */ 304 "\017<s14>" /* Same */ 305 "\020<s15>" /* Same */ 306 "\021<s16>" /* Same */ 307 "\022<s17>" /* Same */ 308 "\023<b18>" /* Reserved, unknown */ 309 "\024MP" /* Multiprocessor Capable */ 310 "\025NX" /* Has EFER.NXE, NX */ 311 "\026<b21>" /* Undefined */ 312 "\027MMX+" /* AMD MMX Extensions */ 313 "\030<s23>" /* Same */ 314 "\031<s24>" /* Same */ 315 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 316 "\033Page1GB" /* 1-GB large page support */ 317 "\034RDTSCP" /* RDTSCP */ 318 "\035<b28>" /* Undefined */ 319 "\036LM" /* 64 bit long mode */ 320 "\0373DNow!+" /* AMD 3DNow! Extensions */ 321 "\0403DNow!" /* AMD 3DNow! */ 322 ); 323 } 324 325 if (amd_feature2 != 0) { 326 printf("\n AMD Features2=0x%b", amd_feature2, 327 "\020" 328 "\001LAHF" /* LAHF/SAHF in long mode */ 329 "\002CMP" /* CMP legacy */ 330 "\003SVM" /* Secure Virtual Mode */ 331 "\004ExtAPIC" /* Extended APIC register */ 332 "\005CR8" /* CR8 in legacy mode */ 333 "\006ABM" /* LZCNT instruction */ 334 "\007SSE4A" /* SSE4A */ 335 "\010MAS" /* Misaligned SSE mode */ 336 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 337 "\012OSVW" /* OS visible workaround */ 338 "\013IBS" /* Instruction based sampling */ 339 "\014SSE5" /* SSE5 */ 340 "\015SKINIT" /* SKINIT/STGI */ 341 "\016WDT" /* Watchdog timer */ 342 "\017<b14>" 343 "\020<b15>" 344 "\021<b16>" 345 "\022<b17>" 346 "\023<b18>" 347 "\024<b19>" 348 "\025<b20>" 349 "\026<b21>" 350 "\027<b22>" 351 "\030<b23>" 352 "\031<b24>" 353 "\032<b25>" 354 "\033<b26>" 355 "\034<b27>" 356 "\035<b28>" 357 "\036<b29>" 358 "\037<b30>" 359 "\040<b31>" 360 ); 361 } 362 363 if (cpu_vendor_id == CPU_VENDOR_CENTAUR) 364 print_via_padlock_info(); 365 366 if ((cpu_feature & CPUID_HTT) && 367 cpu_vendor_id == CPU_VENDOR_AMD) 368 cpu_feature &= ~CPUID_HTT; 369 370 /* 371 * If this CPU supports P-state invariant TSC then 372 * mention the capability. 373 */ 374 switch (cpu_vendor_id) { 375 case CPU_VENDOR_AMD: 376 if ((amd_pminfo & AMDPM_TSC_INVARIANT) || 377 AMD64_CPU_FAMILY(cpu_id) >= 0x10 || 378 cpu_id == 0x60fb2) 379 tsc_is_invariant = 1; 380 break; 381 case CPU_VENDOR_INTEL: 382 if ((amd_pminfo & AMDPM_TSC_INVARIANT) || 383 (AMD64_CPU_FAMILY(cpu_id) == 0x6 && 384 AMD64_CPU_MODEL(cpu_id) >= 0xe) || 385 (AMD64_CPU_FAMILY(cpu_id) == 0xf && 386 AMD64_CPU_MODEL(cpu_id) >= 0x3)) 387 tsc_is_invariant = 1; 388 break; 389 case CPU_VENDOR_CENTAUR: 390 if (AMD64_CPU_FAMILY(cpu_id) == 0x6 && 391 AMD64_CPU_MODEL(cpu_id) >= 0xf && 392 (rdmsr(0x1203) & 0x100000000ULL) == 0) 393 tsc_is_invariant = 1; 394 break; 395 } 396 if (tsc_is_invariant) 397 printf("\n TSC: P-state invariant"); 398 399 } 400 } 401 /* Avoid ugly blank lines: only print newline when we have to. */ 402 if (*cpu_vendor || cpu_id) 403 printf("\n"); 404 405 if (!bootverbose) 406 return; 407 408 if (cpu_vendor_id == CPU_VENDOR_AMD) 409 print_AMD_info(); 410} 411 412void 413panicifcpuunsupported(void) 414{ 415 416#ifndef HAMMER 417#error "You need to specify a cpu type" 418#endif 419 /* 420 * Now that we have told the user what they have, 421 * let them know if that machine type isn't configured. 422 */ 423 switch (cpu_class) { 424 case CPUCLASS_X86: 425#ifndef HAMMER 426 case CPUCLASS_K8: 427#endif 428 panic("CPU class not configured"); 429 default: 430 break; 431 } 432} 433 434 435/* Update TSC freq with the value indicated by the caller. */ 436static void 437tsc_freq_changed(void *arg, const struct cf_level *level, int status) 438{ 439 /* 440 * If there was an error during the transition or 441 * TSC is P-state invariant, don't do anything. 442 */ 443 if (status != 0 || tsc_is_invariant) 444 return; 445 446 /* Total setting for this level gives the new frequency in MHz. */ 447 hw_clockrate = level->total_set.freq; 448} 449 450EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL, 451 EVENTHANDLER_PRI_ANY); 452 453/* 454 * Final stage of CPU identification. 455 */ 456void 457identify_cpu(void) 458{ 459 u_int regs[4]; 460 461 do_cpuid(0, regs); 462 cpu_high = regs[0]; 463 ((u_int *)&cpu_vendor)[0] = regs[1]; 464 ((u_int *)&cpu_vendor)[1] = regs[3]; 465 ((u_int *)&cpu_vendor)[2] = regs[2]; 466 cpu_vendor[12] = '\0'; 467 cpu_vendor_id = find_cpu_vendor_id(); 468 469 do_cpuid(1, regs); 470 cpu_id = regs[0]; 471 cpu_procinfo = regs[1]; 472 cpu_feature = regs[3]; 473 cpu_feature2 = regs[2]; 474 475 /* 476 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID 477 * function number again if it is set from BIOS. It is necessary 478 * for probing correct CPU topology later. 479 * XXX This is only done on the BSP package. 480 */ 481 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4) { 482 uint64_t msr; 483 msr = rdmsr(MSR_IA32_MISC_ENABLE); 484 if ((msr & 0x400000ULL) != 0) { 485 wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL); 486 do_cpuid(0, regs); 487 cpu_high = regs[0]; 488 } 489 } 490 491 if (cpu_vendor_id == CPU_VENDOR_INTEL || 492 cpu_vendor_id == CPU_VENDOR_AMD || 493 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 494 do_cpuid(0x80000000, regs); 495 cpu_exthigh = regs[0]; 496 } 497 if (cpu_exthigh >= 0x80000001) { 498 do_cpuid(0x80000001, regs); 499 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 500 amd_feature2 = regs[2]; 501 } 502 if (cpu_exthigh >= 0x80000007) { 503 do_cpuid(0x80000007, regs); 504 amd_pminfo = regs[3]; 505 } 506 if (cpu_exthigh >= 0x80000008) { 507 do_cpuid(0x80000008, regs); 508 cpu_procinfo2 = regs[2]; 509 } 510 511 /* XXX */ 512 cpu = CPU_CLAWHAMMER; 513} 514 515static u_int 516find_cpu_vendor_id(void) 517{ 518 int i; 519 520 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) 521 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 522 return (cpu_vendors[i].vendor_id); 523 return (0); 524} 525 526static void 527print_AMD_assoc(int i) 528{ 529 if (i == 255) 530 printf(", fully associative\n"); 531 else 532 printf(", %d-way associative\n", i); 533} 534 535static void 536print_AMD_l2_assoc(int i) 537{ 538 switch (i & 0x0f) { 539 case 0: printf(", disabled/not present\n"); break; 540 case 1: printf(", direct mapped\n"); break; 541 case 2: printf(", 2-way associative\n"); break; 542 case 4: printf(", 4-way associative\n"); break; 543 case 6: printf(", 8-way associative\n"); break; 544 case 8: printf(", 16-way associative\n"); break; 545 case 15: printf(", fully associative\n"); break; 546 default: printf(", reserved configuration\n"); break; 547 } 548} 549 550static void 551print_AMD_info(void) 552{ 553 u_int regs[4]; 554 555 if (cpu_exthigh < 0x80000005) 556 return; 557 558 do_cpuid(0x80000005, regs); 559 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 560 print_AMD_assoc(regs[0] >> 24); 561 562 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 563 print_AMD_assoc((regs[0] >> 8) & 0xff); 564 565 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 566 print_AMD_assoc(regs[1] >> 24); 567 568 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 569 print_AMD_assoc((regs[1] >> 8) & 0xff); 570 571 printf("L1 data cache: %d kbytes", regs[2] >> 24); 572 printf(", %d bytes/line", regs[2] & 0xff); 573 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 574 print_AMD_assoc((regs[2] >> 16) & 0xff); 575 576 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 577 printf(", %d bytes/line", regs[3] & 0xff); 578 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 579 print_AMD_assoc((regs[3] >> 16) & 0xff); 580 581 if (cpu_exthigh >= 0x80000006) { 582 do_cpuid(0x80000006, regs); 583 if ((regs[0] >> 16) != 0) { 584 printf("L2 2MB data TLB: %d entries", 585 (regs[0] >> 16) & 0xfff); 586 print_AMD_l2_assoc(regs[0] >> 28); 587 printf("L2 2MB instruction TLB: %d entries", 588 regs[0] & 0xfff); 589 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 590 } else { 591 printf("L2 2MB unified TLB: %d entries", 592 regs[0] & 0xfff); 593 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 594 } 595 if ((regs[1] >> 16) != 0) { 596 printf("L2 4KB data TLB: %d entries", 597 (regs[1] >> 16) & 0xfff); 598 print_AMD_l2_assoc(regs[1] >> 28); 599 600 printf("L2 4KB instruction TLB: %d entries", 601 (regs[1] >> 16) & 0xfff); 602 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 603 } else { 604 printf("L2 4KB unified TLB: %d entries", 605 (regs[1] >> 16) & 0xfff); 606 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 607 } 608 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 609 printf(", %d bytes/line", regs[2] & 0xff); 610 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 611 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 612 } 613} 614 615static void 616print_via_padlock_info(void) 617{ 618 u_int regs[4]; 619 620 /* Check for supported models. */ 621 switch (cpu_id & 0xff0) { 622 case 0x690: 623 if ((cpu_id & 0xf) < 3) 624 return; 625 case 0x6a0: 626 case 0x6d0: 627 case 0x6f0: 628 break; 629 default: 630 return; 631 } 632 633 do_cpuid(0xc0000000, regs); 634 if (regs[0] >= 0xc0000001) 635 do_cpuid(0xc0000001, regs); 636 else 637 return; 638 639 printf("\n VIA Padlock Features=0x%b", regs[3], 640 "\020" 641 "\003RNG" /* RNG */ 642 "\007AES" /* ACE */ 643 "\011AES-CTR" /* ACE2 */ 644 "\013SHA1,SHA256" /* PHE */ 645 "\015RSA" /* PMM */ 646 ); 647} 648