identcpu.c revision 160869
1/*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/amd64/amd64/identcpu.c 160869 2006-08-01 01:23:39Z obrien $"); 43 44#include "opt_cpu.h" 45 46#include <sys/param.h> 47#include <sys/bus.h> 48#include <sys/systm.h> 49#include <sys/kernel.h> 50#include <sys/sysctl.h> 51#include <sys/power.h> 52 53#include <machine/asmacros.h> 54#include <machine/clock.h> 55#include <machine/cputypes.h> 56#include <machine/frame.h> 57#include <machine/intr_machdep.h> 58#include <machine/segments.h> 59#include <machine/specialreg.h> 60#include <machine/md_var.h> 61 62#include <amd64/isa/icu.h> 63 64/* XXX - should be in header file: */ 65void printcpuinfo(void); 66void identify_cpu(void); 67void earlysetcpuclass(void); 68void panicifcpuunsupported(void); 69 70static void print_AMD_info(void); 71static void print_AMD_assoc(int i); 72void setPQL2(int *const size, int *const ways); 73static void setPQL2_AMD(int *const size, int *const ways); 74 75int cpu_class; 76char machine[] = "amd64"; 77SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 78 machine, 0, "Machine class"); 79 80static char cpu_model[128]; 81SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 82 cpu_model, 0, "Machine model"); 83 84static int hw_clockrate; 85SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 86 &hw_clockrate, 0, "CPU instruction clock rate"); 87 88static char cpu_brand[48]; 89 90static struct { 91 char *cpu_name; 92 int cpu_class; 93} amd64_cpus[] = { 94 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 95 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 96}; 97 98extern int pq_l2size; 99extern int pq_l2nways; 100 101void 102printcpuinfo(void) 103{ 104 u_int regs[4], i; 105 char *brand; 106 107 cpu_class = amd64_cpus[cpu].cpu_class; 108 printf("CPU: "); 109 strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model)); 110 111 /* Check for extended CPUID information and a processor name. */ 112 if (cpu_exthigh >= 0x80000004) { 113 brand = cpu_brand; 114 for (i = 0x80000002; i < 0x80000005; i++) { 115 do_cpuid(i, regs); 116 memcpy(brand, regs, sizeof(regs)); 117 brand += sizeof(regs); 118 } 119 } 120 121 if (strcmp(cpu_vendor, "GenuineIntel") == 0) { 122 /* Please make up your mind folks! */ 123 strcat(cpu_model, "EM64T"); 124 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 125 /* 126 * Values taken from AMD Processor Recognition 127 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 128 * (also describes ``Features'' encodings. 129 */ 130 strcpy(cpu_model, "AMD "); 131 switch (cpu_id & 0xF00) { 132 case 0xf00: 133 strcat(cpu_model, "AMD64 Processor"); 134 break; 135 default: 136 strcat(cpu_model, "Unknown"); 137 break; 138 } 139 } 140 141 /* 142 * Replace cpu_model with cpu_brand minus leading spaces if 143 * we have one. 144 */ 145 brand = cpu_brand; 146 while (*brand == ' ') 147 ++brand; 148 if (*brand != '\0') 149 strcpy(cpu_model, brand); 150 151 printf("%s (", cpu_model); 152 switch(cpu_class) { 153 case CPUCLASS_K8: 154 hw_clockrate = (tsc_freq + 5000) / 1000000; 155 printf("%jd.%02d-MHz ", 156 (intmax_t)(tsc_freq + 4999) / 1000000, 157 (u_int)((tsc_freq + 4999) / 10000) % 100); 158 printf("K8"); 159 break; 160 default: 161 printf("Unknown"); /* will panic below... */ 162 } 163 printf("-class CPU)\n"); 164 if(*cpu_vendor) 165 printf(" Origin = \"%s\"",cpu_vendor); 166 if(cpu_id) 167 printf(" Id = 0x%x", cpu_id); 168 169 if (strcmp(cpu_vendor, "GenuineIntel") == 0 || 170 strcmp(cpu_vendor, "AuthenticAMD") == 0) { 171 printf(" Stepping = %u", cpu_id & 0xf); 172 if (cpu_high > 0) { 173 u_int cmp = 1, htt = 1; 174 175 /* 176 * Here we should probably set up flags indicating 177 * whether or not various features are available. 178 * The interesting ones are probably VME, PSE, PAE, 179 * and PGE. The code already assumes without bothering 180 * to check that all CPUs >= Pentium have a TSC and 181 * MSRs. 182 */ 183 printf("\n Features=0x%b", cpu_feature, 184 "\020" 185 "\001FPU" /* Integral FPU */ 186 "\002VME" /* Extended VM86 mode support */ 187 "\003DE" /* Debugging Extensions (CR4.DE) */ 188 "\004PSE" /* 4MByte page tables */ 189 "\005TSC" /* Timestamp counter */ 190 "\006MSR" /* Machine specific registers */ 191 "\007PAE" /* Physical address extension */ 192 "\010MCE" /* Machine Check support */ 193 "\011CX8" /* CMPEXCH8 instruction */ 194 "\012APIC" /* SMP local APIC */ 195 "\013oldMTRR" /* Previous implementation of MTRR */ 196 "\014SEP" /* Fast System Call */ 197 "\015MTRR" /* Memory Type Range Registers */ 198 "\016PGE" /* PG_G (global bit) support */ 199 "\017MCA" /* Machine Check Architecture */ 200 "\020CMOV" /* CMOV instruction */ 201 "\021PAT" /* Page attributes table */ 202 "\022PSE36" /* 36 bit address space support */ 203 "\023PN" /* Processor Serial number */ 204 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 205 "\025<b20>" 206 "\026DTS" /* Debug Trace Store */ 207 "\027ACPI" /* ACPI support */ 208 "\030MMX" /* MMX instructions */ 209 "\031FXSR" /* FXSAVE/FXRSTOR */ 210 "\032SSE" /* Streaming SIMD Extensions */ 211 "\033SSE2" /* Streaming SIMD Extensions #2 */ 212 "\034SS" /* Self snoop */ 213 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 214 "\036TM" /* Thermal Monitor clock slowdown */ 215 "\037IA64" /* CPU can execute IA64 instructions */ 216 "\040PBE" /* Pending Break Enable */ 217 ); 218 219 if (cpu_feature2 != 0) { 220 printf("\n Features2=0x%b", cpu_feature2, 221 "\020" 222 "\001SSE3" /* SSE3 */ 223 "\002<b1>" 224 "\003RSVD2" /* "Reserved" bit 2 */ 225 "\004MON" /* MONITOR/MWAIT Instructions */ 226 "\005DS_CPL" /* CPL Qualified Debug Store */ 227 "\006VMX" /* Virtual Machine Extensions */ 228 "\007<b6>" 229 "\010EST" /* Enhanced SpeedStep */ 230 "\011TM2" /* Thermal Monitor 2 */ 231 "\012<b9>" 232 "\013CNTX-ID" /* L1 context ID available */ 233 "\014<b11>" 234 "\015<b12>" 235 "\016CX16" /* CMPXCHG16B Instruction */ 236 "\017XTPR" /* Send Task Priority Messages*/ 237 "\020<b15>" 238 "\021<b16>" 239 "\022<b17>" 240 "\023<b18>" 241 "\024<b19>" 242 "\025<b20>" 243 "\026<b21>" 244 "\027<b22>" 245 "\030<b23>" 246 "\031<b24>" 247 "\032<b25>" 248 "\033<b26>" 249 "\034<b27>" 250 "\035<b28>" 251 "\036<b29>" 252 "\037<b30>" 253 "\040<b31>" 254 ); 255 } 256 257 /* 258 * AMD64 Architecture Programmer's Manual Volume 3: 259 * General-Purpose and System Instructions 260 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf 261 * 262 * IA-32 Intel Architecture Software Developer's Manual, 263 * Volume 2A: Instruction Set Reference, A-M 264 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf 265 */ 266 if (amd_feature != 0) { 267 printf("\n AMD Features=0x%b", amd_feature, 268 "\020" /* in hex */ 269 "\001<s0>" /* Same */ 270 "\002<s1>" /* Same */ 271 "\003<s2>" /* Same */ 272 "\004<s3>" /* Same */ 273 "\005<s4>" /* Same */ 274 "\006<s5>" /* Same */ 275 "\007<s6>" /* Same */ 276 "\010<s7>" /* Same */ 277 "\011<s8>" /* Same */ 278 "\012<s9>" /* Same */ 279 "\013<b10>" /* Undefined */ 280 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 281 "\015<s12>" /* Same */ 282 "\016<s13>" /* Same */ 283 "\017<s14>" /* Same */ 284 "\020<s15>" /* Same */ 285 "\021<s16>" /* Same */ 286 "\022<s17>" /* Same */ 287 "\023<b18>" /* Reserved, unknown */ 288 "\024MP" /* Multiprocessor Capable */ 289 "\025NX" /* Has EFER.NXE, NX */ 290 "\026<b21>" /* Undefined */ 291 "\027MMX+" /* AMD MMX Extensions */ 292 "\030<s23>" /* Same */ 293 "\031<s24>" /* Same */ 294 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 295 "\033<b26>" /* Undefined */ 296 "\034RDTSCP" /* RDTSCP */ 297 "\035<b28>" /* Undefined */ 298 "\036LM" /* 64 bit long mode */ 299 "\0373DNow!+" /* AMD 3DNow! Extensions */ 300 "\0403DNow!" /* AMD 3DNow! */ 301 ); 302 } 303 304 if (amd_feature2 != 0) { 305 printf("\n AMD Features2=0x%b", amd_feature2, 306 "\020" 307 "\001LAHF" /* LAHF/SAHF in long mode */ 308 "\002CMP" /* CMP legacy */ 309 "\003SVM" /* Secure Virtual Mode */ 310 "\004ExtAPIC" /* Extended APIC register */ 311 "\005CR8" /* CR8 in legacy mode */ 312 "\006<b5>" 313 "\007<b6>" 314 "\010<b7>" 315 "\011<b8>" 316 "\012<b9>" 317 "\013<b10>" 318 "\014<b11>" 319 "\015<b12>" 320 "\016<b13>" 321 "\017<b14>" 322 "\020<b15>" 323 "\021<b16>" 324 "\022<b17>" 325 "\023<b18>" 326 "\024<b19>" 327 "\025<b20>" 328 "\026<b21>" 329 "\027<b22>" 330 "\030<b23>" 331 "\031<b24>" 332 "\032<b25>" 333 "\033<b26>" 334 "\034<b27>" 335 "\035<b28>" 336 "\036<b29>" 337 "\037<b30>" 338 "\040<b31>" 339 ); 340 } 341 342 if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor, 343 "AuthenticAMD") == 0) { 344 cpu_feature &= ~CPUID_HTT; 345 if (bootverbose) 346 printf("\nHTT bit cleared - FreeBSD" 347 " does not have licensing issues" 348 " requiring it.\n"); 349 } 350 351 /* 352 * If this CPU supports HTT or CMP then mention the 353 * number of physical/logical cores it contains. 354 */ 355 if (cpu_feature & CPUID_HTT) 356 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 357 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 && 358 (amd_feature2 & AMDID2_CMP)) 359 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 360 else if (strcmp(cpu_vendor, "GenuineIntel") == 0 && 361 (cpu_high >= 4)) { 362 cpuid_count(4, 0, regs); 363 if ((regs[0] & 0x1f) != 0) 364 cmp = ((regs[0] >> 26) & 0x3f) + 1; 365 } 366 if (cmp > 1) 367 printf("\n Cores per package: %d", cmp); 368 if ((htt / cmp) > 1) 369 printf("\n Logical CPUs per core: %d", 370 htt / cmp); 371 } 372 } 373 /* Avoid ugly blank lines: only print newline when we have to. */ 374 if (*cpu_vendor || cpu_id) 375 printf("\n"); 376 377 if (!bootverbose) 378 return; 379 380 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) 381 print_AMD_info(); 382} 383 384void 385panicifcpuunsupported(void) 386{ 387 388#ifndef HAMMER 389#error "You need to specify a cpu type" 390#endif 391 /* 392 * Now that we have told the user what they have, 393 * let them know if that machine type isn't configured. 394 */ 395 switch (cpu_class) { 396 case CPUCLASS_X86: 397#ifndef HAMMER 398 case CPUCLASS_K8: 399#endif 400 panic("CPU class not configured"); 401 default: 402 break; 403 } 404} 405 406 407/* 408 * Final stage of CPU identification. -- Should I check TI? 409 */ 410void 411identify_cpu(void) 412{ 413 u_int regs[4]; 414 415 do_cpuid(0, regs); 416 cpu_high = regs[0]; 417 ((u_int *)&cpu_vendor)[0] = regs[1]; 418 ((u_int *)&cpu_vendor)[1] = regs[3]; 419 ((u_int *)&cpu_vendor)[2] = regs[2]; 420 cpu_vendor[12] = '\0'; 421 422 do_cpuid(1, regs); 423 cpu_id = regs[0]; 424 cpu_procinfo = regs[1]; 425 cpu_feature = regs[3]; 426 cpu_feature2 = regs[2]; 427 428 if (strcmp(cpu_vendor, "GenuineIntel") == 0 || 429 strcmp(cpu_vendor, "AuthenticAMD") == 0) { 430 do_cpuid(0x80000000, regs); 431 cpu_exthigh = regs[0]; 432 } 433 if (cpu_exthigh >= 0x80000001) { 434 do_cpuid(0x80000001, regs); 435 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 436 amd_feature2 = regs[2]; 437 } 438 if (cpu_exthigh >= 0x80000008) { 439 do_cpuid(0x80000008, regs); 440 cpu_procinfo2 = regs[2]; 441 } 442 443 /* XXX */ 444 cpu = CPU_CLAWHAMMER; 445} 446 447static void 448print_AMD_assoc(int i) 449{ 450 if (i == 255) 451 printf(", fully associative\n"); 452 else 453 printf(", %d-way associative\n", i); 454} 455 456static void 457print_AMD_l2_assoc(int i) 458{ 459 switch (i & 0x0f) { 460 case 0: printf(", disabled/not present\n"); break; 461 case 1: printf(", direct mapped\n"); break; 462 case 2: printf(", 2-way associative\n"); break; 463 case 4: printf(", 4-way associative\n"); break; 464 case 6: printf(", 8-way associative\n"); break; 465 case 8: printf(", 16-way associative\n"); break; 466 case 15: printf(", fully associative\n"); break; 467 default: printf(", reserved configuration\n"); break; 468 } 469} 470 471static void 472print_AMD_info(void) 473{ 474 u_int regs[4]; 475 476 if (cpu_exthigh < 0x80000005) 477 return; 478 479 do_cpuid(0x80000005, regs); 480 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 481 print_AMD_assoc(regs[0] >> 24); 482 483 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 484 print_AMD_assoc((regs[0] >> 8) & 0xff); 485 486 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 487 print_AMD_assoc(regs[1] >> 24); 488 489 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 490 print_AMD_assoc((regs[1] >> 8) & 0xff); 491 492 printf("L1 data cache: %d kbytes", regs[2] >> 24); 493 printf(", %d bytes/line", regs[2] & 0xff); 494 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 495 print_AMD_assoc((regs[2] >> 16) & 0xff); 496 497 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 498 printf(", %d bytes/line", regs[3] & 0xff); 499 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 500 print_AMD_assoc((regs[3] >> 16) & 0xff); 501 502 if (cpu_exthigh >= 0x80000006) { 503 do_cpuid(0x80000006, regs); 504 if ((regs[0] >> 16) != 0) { 505 printf("L2 2MB data TLB: %d entries", 506 (regs[0] >> 16) & 0xfff); 507 print_AMD_l2_assoc(regs[0] >> 28); 508 printf("L2 2MB instruction TLB: %d entries", 509 regs[0] & 0xfff); 510 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 511 } else { 512 printf("L2 2MB unified TLB: %d entries", 513 regs[0] & 0xfff); 514 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 515 } 516 if ((regs[1] >> 16) != 0) { 517 printf("L2 4KB data TLB: %d entries", 518 (regs[1] >> 16) & 0xfff); 519 print_AMD_l2_assoc(regs[1] >> 28); 520 521 printf("L2 4KB instruction TLB: %d entries", 522 (regs[1] >> 16) & 0xfff); 523 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 524 } else { 525 printf("L2 4KB unified TLB: %d entries", 526 (regs[1] >> 16) & 0xfff); 527 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 528 } 529 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 530 printf(", %d bytes/line", regs[2] & 0xff); 531 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 532 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 533 } 534} 535 536static void 537setPQL2_AMD(int *const size, int *const ways) 538{ 539 if (cpu_exthigh >= 0x80000006) { 540 u_int regs[4]; 541 542 do_cpuid(0x80000006, regs); 543 *size = regs[2] >> 16; 544 *ways = (regs[2] >> 12) & 0x0f; 545 switch (*ways) { 546 case 0: /* disabled/not present */ 547 case 15: /* fully associative */ 548 default: *ways = 1; break; /* reserved configuration */ 549 case 4: *ways = 4; break; 550 case 6: *ways = 8; break; 551 case 8: *ways = 16; break; 552 } 553 } 554} 555 556void 557setPQL2(int *const size, int *const ways) 558{ 559 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) 560 setPQL2_AMD(size, ways); 561} 562