#
285830 |
|
23-Jul-2015 |
gjb |
- Copy stable/10@285827 to releng/10.2 in preparation for 10.2-RC1 builds. - Update newvers.sh to reflect RC1. - Update __FreeBSD_version to reflect 10.2. - Update default pkg(8) configuration to use the quarterly branch.[1]
Discussed with: re, portmgr [1] Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
#
265969 |
|
13-May-2014 |
ian |
MFC r256994, r257016, r257055, r257059, r257060, r257075
Add two new interfaces to ofw_bus: - ofw_bus_map_intr() Maps an (iparent, IRQ) tuple to a system-global interrupt number in some platform dependent way. This is meant to be implemented as a replacement for [FDT_]MAP_IRQ() that is an MI interface that knows about the bus hierarchy. - ofw_bus_config_intr() Configures an interrupt (previously mapped) based on firmware sense flags. This replaces manual interpretation of the sense field in bus drivers and will, in a follow-up, allow that interpretation to be redirected to the PIC drivers where it belongs. This will eventually replace the tables in /sys/dev/fdt/fdt_ARCH.c
The PowerPC/AIM code has been converted to use these globally, with an implementation in terms of MAP_IRQ() and powerpc_config_intr(), assuming OpenPIC, at the bus root in nexus(4). The ofw_bus_config_intr() will shortly be integrated into pic_if.m and bounced through nexus into the PIC tree.
Factor out MI portions of the PowerPC nexus device into /sys/dev/ofw. The sparc64 driver will be modified to use this shortly.
Allow PIC drivers to translate firmware sense codes for themselves. This is designed to replace the tables in dev/fdt/fdt_ARCH.c, but will not happen quite yet.
Do not map IRQs twice. This fixes PowerPC/FDT systems with multiple PICs, which would try to treat the previously-mapped interrupts from fdt_decode_intr() as interrupt line numbers on the same parent PIC.
Remove some of the code required for supporting ssm(4) on SPARC in favor of a more PowerPC/FDT-focused design. Whenever SPARC64 is integrated into this rework, this should be (trivially) revisited.
|
#
256281 |
|
10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
|
#
224552 |
|
31-Jul-2011 |
marcel |
Fix r222813: we need to include sys/cpuset.h. because the PIC interface uses cpuset_t. While here, fix the redundant inclusion of sys/bus.h and order the includes.
Approved by: re (blanket)
|
#
218075 |
|
29-Jan-2011 |
marcel |
Fix the interrupt code, broken 7 months ago. The interrupt framework already supported nested PICs, but was limited to having a nested AT-PIC only. With G5 support the need for nested OpenPIC controllers needed to be added. This was done the wrong way and broke the MPC8555 eval system in the process.
OFW, as well as FDT, describe the interrupt routing in terms of a controller and an interrupt pin on it. This needs to be mapped to a flat and global resource: the IRQ. The IRQ is the same as the PCI intline and as such needs to be representable in 8 bits. Secondly, ISA support pretty much dictates that IRQ 0-15 should be reserved for ISA interrupts, because of the internal workins of south bridges. Both were broken.
This change reverts revision 209298 for a big part and re-implements it simpler. In particular: o The id() method of the PIC I/F is removed again. It's not needed. o The openpic_attach() function has been changed to take the OFW or FDT phandle of the controller as a second argument. All bus attachments that previously used openpic_attach() as the attach method of the device I/F now implement as bus-specific method and pass the phandle_t to the renamed openpic_attach(). o Change powerpc_register_pic() to take a few more arguments. In particular: - Pass the number of IPIs specificly. The number of IRQs carved out for a PIC is the sum of the number of int. pins and IPIs. - Pass a flag indicating whether the PIC is an AT-PIC or not. This tells the interrupt framework whether to assign IRQ 0-15 or some other range. o Until we implement proper multi-pass bus enumeration, we have to handle the case where we need to map from PIC+pin to IRQ *before* the PIC gets registered. This is done in a similar way as before, but rather than carving out 256 IRQs per PIC, we carve out 128 IRQs (124 pins + 4 IPIs). This is supposed to handle the G5 case, but should really be fixed properly using multiple passes. o Have the interrupt framework set root_pic in most cases and not put that burden in PIC drivers (for the most part). o Remove powerpc_ign_lookup() and replace it with powerpc_get_irq(). Remove IGN_SHIFT, INTR_INTLINE and INTR_IGN.
Related to the above, fix the Freescale PCI controller driver, broken by the FDT code. Besides not attaching properly, bus numbers were assigned improperly and enumeration was broken in general. This prevented the AT PIC from being discovered and interrupt routing to work properly. Consequently, the ata(4) controller stopped functioning.
Fix the driver, and FDT PCI support, enough to get the MPC8555CDS going again. The FDT PCI code needs a whole lot more work.
No breakages are expected, but lackiong G5 hardware, it's possible that there are unpleasant side-effects. At least MPC85xx support is back to where it was 7 months ago -- it's amazing how badly support can be broken in just 7 months...
Sponsored by: Juniper Networks
|
#
209908 |
|
11-Jul-2010 |
raj |
Convert Freescale PowerPC platforms to FDT convention.
The following systems are affected:
- MPC8555CDS - MPC8572DS
This overhaul covers the following major changes:
- All integrated peripherals drivers for Freescale MPC85XX SoC, which are currently in the FreeBSD source tree are reworked and adjusted so they derive config data out of the device tree blob (instead of hard coded / tabelarized values).
- This includes: LBC, PCI / PCI-Express, I2C, DS1553, OpenPIC, TSEC, SEC, QUICC, UART, CFI.
- Thanks to the common FDT infrastrucutre (fdtbus, simplebus) we retire ocpbus(4) driver, which was based on hard-coded config data.
Note that world for these platforms has to be built WITH_FDT.
Reviewed by: imp Sponsored by: The FreeBSD Foundation
|
#
209724 |
|
06-Jul-2010 |
nwhitehorn |
Move the EOI logic when starting ithreads into intr_machdep instead of relying on it as a side effect of PIC_MASK() in the PIC drivers, and add an inmplementation of assign_cpu() for the kernel interrupt layer.
|
#
209639 |
|
02-Jul-2010 |
marcel |
Remove the unneeded header <machine/intr.h>.
|
#
209493 |
|
24-Jun-2010 |
marcel |
Pass the device_t of the AT PIC driver to atpic_intr() so that we don't have to use a global variable. Pass a NULL frame pointer to the dispatch function just like openpic(4).
|
#
209298 |
|
18-Jun-2010 |
nwhitehorn |
Provide for multiple, cascaded PICs on PowerPC systems, and extend the OFW interrupt map interface to also return the device's interrupt parent.
MFC after: 8.1-RELEASE
|
#
193144 |
|
31-May-2009 |
marcel |
Mark the cascaded AT interrupt handler as MP safe to avoid having it grab Giant. The next step would be to make it a filter.
|
#
191450 |
|
24-Apr-2009 |
marcel |
Add suppport for ISA and ISA interrupts to make the ATA controller in the VIA southbridge functional in the CDS (Configurable Development System) for MPC85XX. The embedded USB controllers look operational but the interrupt steering is still wrong.
|