atpic.c revision 191450 
1/*-
2 * Copyright (c) 2009 Marcel Moolenaar
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/atpic.c 191450 2009-04-24 03:51:11Z marcel $");
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/kernel.h>
32#include <sys/module.h>
33#include <sys/bus.h>
34#include <sys/rman.h>
35#include <sys/bus.h>
36
37#include <machine/bus.h>
38#include <machine/intr.h>
39#include <machine/intr_machdep.h>
40#include <machine/pio.h>
41
42#include <powerpc/mpc85xx/ocpbus.h>
43
44#include <dev/ic/i8259.h>
45
46#include <isa/isareg.h>
47#include <isa/isavar.h>
48
49#include "pic_if.h"
50
51#define	ATPIC_MASTER	0
52#define	ATPIC_SLAVE	1
53
54struct atpic_softc {
55	device_t	sc_dev;
56
57	/* I/O port resources for master & slave. */
58	struct resource	*sc_res[2];
59	int		sc_rid[2];
60
61	/* Our "routing" interrupt */
62	struct resource *sc_ires;
63	void		*sc_icookie;
64	int		sc_irid;
65
66	int		sc_vector[16];
67	uint8_t		sc_mask[2];
68};
69
70static int	atpic_isa_attach(device_t);
71static void	atpic_isa_identify(driver_t *, device_t);
72static int	atpic_isa_probe(device_t);
73
74static void atpic_config(device_t, u_int, enum intr_trigger,
75    enum intr_polarity);
76static void atpic_dispatch(device_t, struct trapframe *);
77static void atpic_enable(device_t, u_int, u_int);
78static void atpic_eoi(device_t, u_int);
79static void atpic_ipi(device_t, u_int);
80static void atpic_mask(device_t, u_int);
81static void atpic_unmask(device_t, u_int);
82
83static device_method_t atpic_isa_methods[] = {
84	/* Device interface */
85	DEVMETHOD(device_identify, 	atpic_isa_identify),
86	DEVMETHOD(device_probe,		atpic_isa_probe),
87	DEVMETHOD(device_attach,	atpic_isa_attach),
88
89	/* PIC interface */
90	DEVMETHOD(pic_config,		atpic_config),
91	DEVMETHOD(pic_dispatch,		atpic_dispatch),
92	DEVMETHOD(pic_enable,		atpic_enable),
93	DEVMETHOD(pic_eoi,		atpic_eoi),
94	DEVMETHOD(pic_ipi,		atpic_ipi),
95	DEVMETHOD(pic_mask,		atpic_mask),
96	DEVMETHOD(pic_unmask,		atpic_unmask),
97
98	{ 0, 0 },
99};
100
101static driver_t atpic_isa_driver = {
102	"atpic",
103	atpic_isa_methods,
104	sizeof(struct atpic_softc)
105};
106
107static devclass_t atpic_devclass;
108
109DRIVER_MODULE(atpic, isa, atpic_isa_driver, atpic_devclass, 0, 0);
110
111static struct isa_pnp_id atpic_ids[] = {
112	{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
113	{ 0 }
114};
115
116static __inline uint8_t
117atpic_read(struct atpic_softc *sc, int icu, int ofs)
118{
119	uint8_t val;
120
121	val = bus_read_1(sc->sc_res[icu], ofs);
122	return (val);
123}
124
125static __inline void
126atpic_write(struct atpic_softc *sc, int icu, int ofs, uint8_t val)
127{
128
129	bus_write_1(sc->sc_res[icu], ofs, val);
130	bus_barrier(sc->sc_res[icu], ofs, 2 - ofs,
131	    BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
132}
133
134static void
135atpic_intr(void *arg)
136{
137
138	atpic_dispatch(pic8259, arg);
139}
140
141static void
142atpic_isa_identify(driver_t *drv, device_t parent)
143{
144	device_t child;
145
146	child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, drv->name, -1);
147	device_set_driver(child, drv);
148	isa_set_logicalid(child, atpic_ids[0].ip_id);
149	isa_set_vendorid(child, atpic_ids[0].ip_id);
150
151	bus_set_resource(child, SYS_RES_IOPORT, ATPIC_MASTER, IO_ICU1, 2);
152	bus_set_resource(child, SYS_RES_IOPORT, ATPIC_SLAVE, IO_ICU2, 2);
153
154	/* ISA interrupts are routed through external interrupt 0. */
155	bus_set_resource(child, SYS_RES_IRQ, 0, PIC_IRQ_EXT(0), 1);
156}
157
158static int
159atpic_isa_probe(device_t dev)
160{
161	int res;
162
163	res = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
164	if (res > 0)
165		return (res);
166
167	device_set_desc(dev, "PC/AT compatible PIC");
168	return (res);
169}
170
171static void
172atpic_init(struct atpic_softc *sc, int icu)
173{
174
175	sc->sc_mask[icu] = 0xff - ((icu == ATPIC_MASTER) ? 4 : 0);
176
177	atpic_write(sc, icu, 0, ICW1_RESET | ICW1_IC4);
178	atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 8 : 0);
179	atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 2 : 4);
180	atpic_write(sc, icu, 1, ICW4_8086);
181	atpic_write(sc, icu, 1, sc->sc_mask[icu]);
182	atpic_write(sc, icu, 0, OCW3_SEL | OCW3_RR);
183}
184
185static int
186atpic_isa_attach(device_t dev)
187{
188	struct atpic_softc *sc;
189	int error;
190
191	sc = device_get_softc(dev);
192	sc->sc_dev = dev;
193
194	error = ENXIO;
195
196	sc->sc_rid[ATPIC_MASTER] = 0;
197	sc->sc_res[ATPIC_MASTER] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
198	    &sc->sc_rid[ATPIC_MASTER], RF_ACTIVE);
199	if (sc->sc_res[ATPIC_MASTER] == NULL)
200		goto fail;
201
202	sc->sc_rid[ATPIC_SLAVE] = 1;
203	sc->sc_res[ATPIC_SLAVE] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
204	    &sc->sc_rid[ATPIC_SLAVE], RF_ACTIVE);
205	if (sc->sc_res[ATPIC_SLAVE] == NULL)
206		goto fail;
207
208	sc->sc_irid = 0;
209	sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
210	    RF_ACTIVE);
211	if (sc->sc_ires == NULL)
212		goto fail;
213
214	error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_MISC | INTR_FAST,
215	    NULL, atpic_intr, NULL, &sc->sc_icookie);
216	if (error)
217		goto fail;
218
219	atpic_init(sc, ATPIC_SLAVE);
220	atpic_init(sc, ATPIC_MASTER);
221
222	powerpc_register_8259(dev);
223	return (0);
224
225 fail:
226	if (sc->sc_ires != NULL)
227		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
228		    sc->sc_ires);
229	if (sc->sc_res[ATPIC_SLAVE] != NULL)
230		bus_release_resource(dev, SYS_RES_IOPORT,
231		    sc->sc_rid[ATPIC_SLAVE], sc->sc_res[ATPIC_SLAVE]);
232	if (sc->sc_res[ATPIC_MASTER] != NULL)
233		bus_release_resource(dev, SYS_RES_IOPORT,
234		    sc->sc_rid[ATPIC_MASTER], sc->sc_res[ATPIC_MASTER]);
235	return (error);
236}
237
238
239/*
240 * PIC interface.
241 */
242
243static void
244atpic_config(device_t dev, u_int irq, enum intr_trigger trig,
245    enum intr_polarity pol)
246{
247}
248
249static void
250atpic_dispatch(device_t dev, struct trapframe *tf)
251{
252	struct atpic_softc *sc;
253	uint8_t irq;
254
255	sc = device_get_softc(dev);
256	atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_P);
257	irq = atpic_read(sc, ATPIC_MASTER, 0);
258	atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_RR);
259	if ((irq & 0x80) == 0)
260		return;
261
262	if (irq == 0x82) {
263		atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_P);
264		irq = atpic_read(sc, ATPIC_SLAVE, 0) + 8;
265		atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_RR);
266		if ((irq & 0x80) == 0)
267			return;
268	}
269
270	powerpc_dispatch_intr(sc->sc_vector[irq & 0x0f], tf);
271}
272
273static void
274atpic_enable(device_t dev, u_int irq, u_int vector)
275{
276	struct atpic_softc *sc;
277
278	sc = device_get_softc(dev);
279	sc->sc_vector[irq] = vector;
280	atpic_unmask(dev, irq);
281}
282
283static void
284atpic_eoi(device_t dev, u_int irq)
285{
286	struct atpic_softc *sc;
287
288	sc = device_get_softc(dev);
289	if (irq > 7)
290		atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI);
291	atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI);
292}
293
294static void
295atpic_ipi(device_t dev, u_int cpu)
296{
297	/* No SMP support. */
298}
299
300static void
301atpic_mask(device_t dev, u_int irq)
302{
303	struct atpic_softc *sc;
304
305	sc = device_get_softc(dev);
306	if (irq > 7) {
307		sc->sc_mask[ATPIC_SLAVE] |= 1 << (irq - 8);
308		atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
309		atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI);
310	} else {
311		sc->sc_mask[ATPIC_MASTER] |= 1 << irq;
312		atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
313	}
314	atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI);
315}
316
317static void
318atpic_unmask(device_t dev, u_int irq)
319{
320	struct atpic_softc *sc;
321
322	sc = device_get_softc(dev);
323	if (irq > 7) {
324		sc->sc_mask[ATPIC_SLAVE] &= ~(1 << (irq - 8));
325		atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
326	} else {
327		sc->sc_mask[ATPIC_MASTER] &= ~(1 << irq);
328		atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
329	}
330}
331