atpic.c revision 209493 
1/*-
2 * Copyright (c) 2009 Marcel Moolenaar
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/atpic.c 209493 2010-06-24 05:05:18Z marcel $");
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/kernel.h>
32#include <sys/module.h>
33#include <sys/bus.h>
34#include <sys/rman.h>
35#include <sys/bus.h>
36
37#include <machine/bus.h>
38#include <machine/intr.h>
39#include <machine/intr_machdep.h>
40#include <machine/ocpbus.h>
41#include <machine/pio.h>
42
43#include <powerpc/mpc85xx/ocpbus.h>
44
45#include <dev/ic/i8259.h>
46
47#include <isa/isareg.h>
48#include <isa/isavar.h>
49
50#include "pic_if.h"
51
52#define	ATPIC_MASTER	0
53#define	ATPIC_SLAVE	1
54
55struct atpic_softc {
56	device_t	sc_dev;
57
58	/* I/O port resources for master & slave. */
59	struct resource	*sc_res[2];
60	int		sc_rid[2];
61
62	/* Our "routing" interrupt */
63	struct resource *sc_ires;
64	void		*sc_icookie;
65	int		sc_irid;
66
67	int		sc_vector[16];
68	uint8_t		sc_mask[2];
69};
70
71static int	atpic_isa_attach(device_t);
72static void	atpic_isa_identify(driver_t *, device_t);
73static int	atpic_isa_probe(device_t);
74
75static void atpic_config(device_t, u_int, enum intr_trigger,
76    enum intr_polarity);
77static void atpic_dispatch(device_t, struct trapframe *);
78static void atpic_enable(device_t, u_int, u_int);
79static void atpic_eoi(device_t, u_int);
80static void atpic_ipi(device_t, u_int);
81static void atpic_mask(device_t, u_int);
82static void atpic_unmask(device_t, u_int);
83static uint32_t atpic_id (device_t dev);
84
85static device_method_t atpic_isa_methods[] = {
86	/* Device interface */
87	DEVMETHOD(device_identify, 	atpic_isa_identify),
88	DEVMETHOD(device_probe,		atpic_isa_probe),
89	DEVMETHOD(device_attach,	atpic_isa_attach),
90
91	/* PIC interface */
92	DEVMETHOD(pic_config,		atpic_config),
93	DEVMETHOD(pic_dispatch,		atpic_dispatch),
94	DEVMETHOD(pic_enable,		atpic_enable),
95	DEVMETHOD(pic_eoi,		atpic_eoi),
96	DEVMETHOD(pic_ipi,		atpic_ipi),
97	DEVMETHOD(pic_mask,		atpic_mask),
98	DEVMETHOD(pic_unmask,		atpic_unmask),
99	DEVMETHOD(pic_id,		atpic_id),
100
101	{ 0, 0 },
102};
103
104static driver_t atpic_isa_driver = {
105	"atpic",
106	atpic_isa_methods,
107	sizeof(struct atpic_softc)
108};
109
110static devclass_t atpic_devclass;
111
112DRIVER_MODULE(atpic, isa, atpic_isa_driver, atpic_devclass, 0, 0);
113
114static struct isa_pnp_id atpic_ids[] = {
115	{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
116	{ 0 }
117};
118
119static __inline uint8_t
120atpic_read(struct atpic_softc *sc, int icu, int ofs)
121{
122	uint8_t val;
123
124	val = bus_read_1(sc->sc_res[icu], ofs);
125	return (val);
126}
127
128static __inline void
129atpic_write(struct atpic_softc *sc, int icu, int ofs, uint8_t val)
130{
131
132	bus_write_1(sc->sc_res[icu], ofs, val);
133	bus_barrier(sc->sc_res[icu], ofs, 2 - ofs,
134	    BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
135}
136
137static void
138atpic_intr(void *arg)
139{
140
141	atpic_dispatch(arg, NULL);
142}
143
144static void
145atpic_isa_identify(driver_t *drv, device_t parent)
146{
147	device_t child;
148
149	child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, drv->name, -1);
150	device_set_driver(child, drv);
151	isa_set_logicalid(child, atpic_ids[0].ip_id);
152	isa_set_vendorid(child, atpic_ids[0].ip_id);
153
154	bus_set_resource(child, SYS_RES_IOPORT, ATPIC_MASTER, IO_ICU1, 2);
155	bus_set_resource(child, SYS_RES_IOPORT, ATPIC_SLAVE, IO_ICU2, 2);
156
157	/* ISA interrupts are routed through external interrupt 0. */
158	bus_set_resource(child, SYS_RES_IRQ, 0, PIC_IRQ_EXT(0), 1);
159}
160
161static int
162atpic_isa_probe(device_t dev)
163{
164	int res;
165
166	res = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
167	if (res > 0)
168		return (res);
169
170	device_set_desc(dev, "PC/AT compatible PIC");
171	return (res);
172}
173
174static void
175atpic_init(struct atpic_softc *sc, int icu)
176{
177
178	sc->sc_mask[icu] = 0xff - ((icu == ATPIC_MASTER) ? 4 : 0);
179
180	atpic_write(sc, icu, 0, ICW1_RESET | ICW1_IC4);
181	atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 8 : 0);
182	atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 2 : 4);
183	atpic_write(sc, icu, 1, ICW4_8086);
184	atpic_write(sc, icu, 1, sc->sc_mask[icu]);
185	atpic_write(sc, icu, 0, OCW3_SEL | OCW3_RR);
186}
187
188static int
189atpic_isa_attach(device_t dev)
190{
191	struct atpic_softc *sc;
192	int error;
193
194	sc = device_get_softc(dev);
195	sc->sc_dev = dev;
196
197	error = ENXIO;
198
199	sc->sc_rid[ATPIC_MASTER] = 0;
200	sc->sc_res[ATPIC_MASTER] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
201	    &sc->sc_rid[ATPIC_MASTER], RF_ACTIVE);
202	if (sc->sc_res[ATPIC_MASTER] == NULL)
203		goto fail;
204
205	sc->sc_rid[ATPIC_SLAVE] = 1;
206	sc->sc_res[ATPIC_SLAVE] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
207	    &sc->sc_rid[ATPIC_SLAVE], RF_ACTIVE);
208	if (sc->sc_res[ATPIC_SLAVE] == NULL)
209		goto fail;
210
211	sc->sc_irid = 0;
212	sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
213	    RF_ACTIVE);
214	if (sc->sc_ires == NULL)
215		goto fail;
216
217	error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_MISC | INTR_MPSAFE,
218	    NULL, atpic_intr, dev, &sc->sc_icookie);
219	if (error)
220		goto fail;
221
222	atpic_init(sc, ATPIC_SLAVE);
223	atpic_init(sc, ATPIC_MASTER);
224
225	powerpc_register_pic(dev, 0x10);
226	return (0);
227
228 fail:
229	if (sc->sc_ires != NULL)
230		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
231		    sc->sc_ires);
232	if (sc->sc_res[ATPIC_SLAVE] != NULL)
233		bus_release_resource(dev, SYS_RES_IOPORT,
234		    sc->sc_rid[ATPIC_SLAVE], sc->sc_res[ATPIC_SLAVE]);
235	if (sc->sc_res[ATPIC_MASTER] != NULL)
236		bus_release_resource(dev, SYS_RES_IOPORT,
237		    sc->sc_rid[ATPIC_MASTER], sc->sc_res[ATPIC_MASTER]);
238	return (error);
239}
240
241
242/*
243 * PIC interface.
244 */
245
246static void
247atpic_config(device_t dev, u_int irq, enum intr_trigger trig,
248    enum intr_polarity pol)
249{
250}
251
252static void
253atpic_dispatch(device_t dev, struct trapframe *tf)
254{
255	struct atpic_softc *sc;
256	uint8_t irq;
257
258	sc = device_get_softc(dev);
259	atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_P);
260	irq = atpic_read(sc, ATPIC_MASTER, 0);
261	atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_RR);
262	if ((irq & 0x80) == 0)
263		return;
264
265	if (irq == 0x82) {
266		atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_P);
267		irq = atpic_read(sc, ATPIC_SLAVE, 0) + 8;
268		atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_RR);
269		if ((irq & 0x80) == 0)
270			return;
271	}
272
273	powerpc_dispatch_intr(sc->sc_vector[irq & 0x0f], tf);
274}
275
276static void
277atpic_enable(device_t dev, u_int irq, u_int vector)
278{
279	struct atpic_softc *sc;
280
281	sc = device_get_softc(dev);
282	sc->sc_vector[irq] = vector;
283	atpic_unmask(dev, irq);
284}
285
286static void
287atpic_eoi(device_t dev, u_int irq)
288{
289	struct atpic_softc *sc;
290
291	sc = device_get_softc(dev);
292	if (irq > 7)
293		atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI);
294	atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI);
295}
296
297static void
298atpic_ipi(device_t dev, u_int cpu)
299{
300	/* No SMP support. */
301}
302
303static void
304atpic_mask(device_t dev, u_int irq)
305{
306	struct atpic_softc *sc;
307
308	sc = device_get_softc(dev);
309	if (irq > 7) {
310		sc->sc_mask[ATPIC_SLAVE] |= 1 << (irq - 8);
311		atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
312		atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI);
313	} else {
314		sc->sc_mask[ATPIC_MASTER] |= 1 << irq;
315		atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
316	}
317	atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI);
318}
319
320static void
321atpic_unmask(device_t dev, u_int irq)
322{
323	struct atpic_softc *sc;
324
325	sc = device_get_softc(dev);
326	if (irq > 7) {
327		sc->sc_mask[ATPIC_SLAVE] &= ~(1 << (irq - 8));
328		atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
329	} else {
330		sc->sc_mask[ATPIC_MASTER] &= ~(1 << irq);
331		atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
332	}
333}
334
335static uint32_t
336atpic_id (device_t dev)
337{
338
339	return (ATPIC_ID);
340}
341
342