1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
4 *
5 * Based on davinci_dvevm.h. Original Copyrights follow:
6 *
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * Board
15 */
16
17/*
18 * SoC Configuration
19 */
20#define CFG_SYS_EXCEPTION_VECTORS_HIGH
21#define CFG_SYS_OSCIN_FREQ		24000000
22#define CFG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
23#define CFG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
24
25#ifdef CONFIG_MTD_NOR_FLASH
26#define CFG_SYS_DV_NOR_BOOT_CFG	(0x11)
27#endif
28
29/*
30 * Memory Info
31 */
32#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
33#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
34#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
35/* memtest start addr */
36
37/* memtest will be run on 16MB */
38
39#define CFG_SYS_DA850_SYSCFG_SUSPSRC (	\
40	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
41	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
42	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
43	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
44	DAVINCI_SYSCFG_SUSPSRC_I2C)
45
46/*
47 * PLL configuration
48 */
49
50#define CFG_SYS_DA850_PLL0_PLLM     24
51#define CFG_SYS_DA850_PLL1_PLLM     21
52
53/*
54 * DDR2 memory configuration
55 */
56#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
57					DV_DDR_PHY_EXT_STRBEN | \
58					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
59
60#define CFG_SYS_DA850_DDR2_SDBCR (		\
61	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |	\
62	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
63	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
64	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
65	(0x3 << DV_DDR_SDCR_CL_SHIFT) |		\
66	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) |	\
67	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
68
69/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
70#define CFG_SYS_DA850_DDR2_SDBCR2 0
71
72#define CFG_SYS_DA850_DDR2_SDTIMR (		\
73	(14 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
74	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
75	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
76	(1 << DV_DDR_SDTMR1_WR_SHIFT) |		\
77	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
78	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
79	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
80	(0 << DV_DDR_SDTMR1_WTR_SHIFT))
81
82#define CFG_SYS_DA850_DDR2_SDTIMR2 (		\
83	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
84	(0 << DV_DDR_SDTMR2_XP_SHIFT) |		\
85	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
86	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
87	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
88	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
89	(0 << DV_DDR_SDTMR2_CKE_SHIFT))
90
91#define CFG_SYS_DA850_DDR2_SDRCR    0x00000494
92#define CFG_SYS_DA850_DDR2_PBBPR    0x30
93
94/*
95 * Serial Driver info
96 */
97#define CFG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
98
99#define CFG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
100
101/*
102 * I2C Configuration
103 */
104#define CFG_SYS_I2C_EXPANDER_ADDR   0x20
105
106/*
107 * Flash & Environment
108 */
109#ifdef CONFIG_MTD_RAW_NAND
110#define CFG_SYS_NAND_CS		3
111#define CFG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
112#define CFG_SYS_NAND_MASK_CLE		0x10
113#define CFG_SYS_NAND_MASK_ALE		0x8
114#define CFG_SYS_NAND_U_BOOT_SIZE	0x40000
115#define CFG_SYS_NAND_U_BOOT_DST	0xc1080000
116#define CFG_SYS_NAND_U_BOOT_START	CFG_SYS_NAND_U_BOOT_DST
117#define CFG_SYS_NAND_ECCPOS		{				\
118				24, 25, 26, 27, 28, \
119				29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
120				39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
121				49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
122				59, 60, 61, 62, 63 }
123#define CFG_SYS_NAND_ECCSIZE		512
124#define CFG_SYS_NAND_ECCBYTES	10
125#endif
126
127#ifdef CONFIG_MTD_NOR_FLASH
128#define CFG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
129#define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
130#endif
131
132/*
133 * U-Boot general configuration
134 */
135
136/*
137 * Linux Information
138 */
139#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
140
141#define DEFAULT_LINUX_BOOT_ENV \
142	"loadaddr=0xc0700000\0" \
143	"fdtaddr=0xc0600000\0" \
144	"scriptaddr=0xc0600000\0"
145
146#include <env/ti/mmc.h>
147
148#define CFG_EXTRA_ENV_SETTINGS \
149	DEFAULT_LINUX_BOOT_ENV \
150	DEFAULT_MMC_TI_ARGS \
151	"bootpart=0:2\0" \
152	"bootdir=/boot\0" \
153	"bootfile=zImage\0" \
154	"fdtfile=da850-evm.dtb\0" \
155	"boot_fdt=yes\0" \
156	"boot_fit=0\0" \
157	"console=ttyS2,115200n8\0" \
158	"hwconfig=dsp:wake=yes"
159
160#ifdef CONFIG_SPL_BUILD
161/* defines for SPL */
162
163#endif
164
165/* Load U-Boot Image From MMC */
166
167/* additions for new relocation code, must added to all boards */
168#define CFG_SYS_SDRAM_BASE		0xc0000000
169
170#include <asm/arch/hardware.h>
171
172#endif /* __CONFIG_H */
173