1menu "FPGA support" 2 3config FPGA 4 bool 5 6config FPGA_ALTERA 7 bool "Enable Altera FPGA drivers" 8 select FPGA 9 help 10 Say Y here to enable the Altera FPGA driver 11 12 This provides basic infrastructure to support Altera FPGA devices. 13 Enable Altera FPGA specific functions which includes bitstream 14 (in BIT format), fpga and device validation. 15 16config FPGA_SOCFPGA 17 bool "Enable Gen5 and Arria10 common FPGA drivers" 18 select FPGA_ALTERA 19 help 20 Say Y here to enable the Gen5 and Arria10 common FPGA driver 21 22 This provides common functionality for Gen5 and Arria10 devices. 23 24config FPGA_STRATIX_II 25 bool "Enable Stratix II FPGA drivers" 26 depends on FPGA_ALTERA 27 help 28 Say Y here to enable the Altera Stratix II FPGA-specific driver. 29 30config FPGA_STRATIX_V 31 bool "Enable Stratix V FPGA drivers" 32 depends on FPGA_ALTERA 33 help 34 Say Y here to enable the Altera Stratix V FPGA specific driver. 35 36config FPGA_ACEX1K 37 bool "Enable Altera ACEX 1K driver" 38 depends on FPGA_ALTERA 39 help 40 Say Y here to enable the Altera ACEX 1K FPGA specific driver. 41 42config FPGA_CYCLON2 43 bool "Enable Altera FPGA driver for Cyclone II" 44 depends on FPGA_ALTERA 45 help 46 Say Y here to enable the Altera Cyclone II FPGA specific driver 47 48 This provides common functionality for Altera Cyclone II devices. 49 Enable FPGA driver for loading bitstream in BIT and BIN format 50 on Altera Cyclone II device. 51 52config FPGA_INTEL_SDM_MAILBOX 53 bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" 54 depends on TARGET_SOCFPGA_SOC64 55 select FPGA_ALTERA 56 help 57 Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver 58 59 This provides common functionality for Intel FPGA devices. 60 Enable FPGA driver for writing full bitstream into Intel FPGA 61 devices through SDM (Secure Device Manager) Mailbox. 62 63config FPGA_LATTICE 64 bool "Enable Lattice FPGA driver" 65 help 66 This is used for the lattice FPGAs. Please check the source code as 67 there is no documentation for this at present. 68 69config FPGA_XILINX 70 bool "Enable Xilinx FPGA drivers" 71 select FPGA 72 help 73 Enable Xilinx FPGA specific functions which includes bitstream 74 (in BIT format), fpga and device validation. 75 76config FPGA_ZYNQMPPL 77 bool "Enable Xilinx FPGA driver for ZynqMP" 78 depends on FPGA_XILINX && ZYNQMP_FIRMWARE 79 help 80 Enable FPGA driver for loading bitstream in BIT and BIN format 81 on Xilinx Zynq UltraScale+ (ZynqMP) device. 82 83config FPGA_VERSALPL 84 bool "Enable Xilinx FPGA driver for Versal" 85 depends on FPGA_XILINX 86 help 87 Enable FPGA driver for loading bitstream in PDI format on Xilinx 88 Versal device. PDI is a new programmable device image format for 89 Versal. The bitstream will only be generated as PDI for Versal 90 platform. 91 92config FPGA_SPARTAN2 93 bool "Enable Spartan2 FPGA driver" 94 depends on FPGA_XILINX 95 help 96 Enable Spartan2 FPGA driver. 97 98config FPGA_SPARTAN3 99 bool "Enable Spartan3 FPGA driver" 100 depends on FPGA_XILINX 101 help 102 Enable Spartan3 FPGA driver for loading in BIT format. 103 104config FPGA_VIRTEX2 105 bool "Enable Xilinx Virtex-II and later FPGA driver" 106 depends on FPGA_XILINX 107 help 108 Enable Virtex-II FPGA driver for loading in BIT format. This driver 109 also supports many newer Xilinx FPGA families. 110 111config SYS_FPGA_CHECK_BUSY 112 bool "Perform busy check during load from FPGA" 113 depends on FPGA_SPARTAN2 || FPGA_SPARTAN3 || FPGA_VIRTEX2 114 115config FPGA_ZYNQPL 116 bool "Enable Xilinx FPGA for Zynq" 117 depends on ARCH_ZYNQ 118 help 119 Enable FPGA driver for loading bitstream in BIT and BIN format 120 on Xilinx Zynq devices. 121 122config SYS_FPGA_CHECK_CTRLC 123 bool "Allow Control-C to interrupt FPGA configuration" 124 depends on FPGA 125 help 126 User can interrupt FPGA configuration by pressing CTRL+C. 127 128config SYS_FPGA_PROG_FEEDBACK 129 bool "Progress output during FPGA configuration" 130 depends on FPGA 131 default y if FPGA_VIRTEX2 132 help 133 Enable printing of hash marks during FPGA configuration. 134 135config FPGA_LOAD_SECURE 136 bool "Enable loading secure bitstreams" 137 depends on FPGA 138 help 139 Enables the fpga loads() functions that are used to load secure 140 (authenticated or encrypted or both) bitstreams on to FPGA. 141 142config SPL_FPGA_LOAD_SECURE 143 bool "Enable loading secure bitstreams for SPL" 144 depends on SPL_FPGA 145 help 146 Enables the fpga loads() functions that are used to load secure 147 (authenticated or encrypted or both) bitstreams on to FPGA. 148 149config DM_FPGA 150 bool "Enable Driver Model for FPGA drivers" 151 depends on DM 152 select FPGA 153 help 154 Enable driver model for Field-Programmable Gate Array (FPGA) devices. 155 The devices cover a wide range of applications and are configured at 156 runtime by loading a bitstream into the FPGA device. 157 Loading a bitstream from any kind of storage is the main task of the 158 FPGA drivers. 159 For now this uclass has no methods yet. 160 161config SANDBOX_FPGA 162 bool "Enable sandbox FPGA driver" 163 depends on SANDBOX && DM_FPGA 164 help 165 This is a driver model based FPGA driver for sandbox. 166 Currently it is a stub only, as there are no usable uclass methods yet. 167 168config MAX_FPGA_DEVICES 169 int "Maximum number of FPGA devices" 170 depends on FPGA 171 default 5 172 173endmenu 174