#
6d87b157 |
|
01-Feb-2023 |
Algapally Santosh Sagar <santoshsagar.algapally@amd.com> |
arm64: zynqmp: Add missing ZYNQMP_FIRMWARE dependencies There are missing Kconfig dependencies in the code which is using firmware interface. The commit 71efd45a5fc7 ("arm64: zynqmp: Change firmware dependency") add option to also disable ZYNQMP_FIRMWARE. But not all Kconfig dependencies were properly described and also sdhci and gem drivers didn't protect the code properly. So, add the missing ZYNQMP_FIRMWARE dependencies. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230201095553.11219-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
1edc21a7 |
|
01-Feb-2023 |
Simon Glass <sjg@chromium.org> |
fpga: Add a FPGA_STRATIX_II option There is no Kconfig option for this code, but it seems to be useful. Add one. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8badd336 |
|
01-Feb-2023 |
Simon Glass <sjg@chromium.org> |
fpga: Add a LATTICE option There is no Kconfig option for this code, but it seems to be useful. Add one. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8fe042be |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
fpga: Migrate CONFIG_MAX_FPGA_DEVICES to Kconfig This is always defined to 5, so use that as the default. Cc: Michal Simek <michal.simek@amd.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Michal Simek <michal.simek@amd.com> |
#
f00f676a |
|
04-Dec-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FPGA_CHECK_BUSY to Kconfig This converts the following to Kconfig: CONFIG_SYS_FPGA_CHECK_BUSY Signed-off-by: Tom Rini <trini@konsulko.com> |
#
312c4b11 |
|
07-Oct-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Add missing Kconfig symbols for old FPGA drivers Those drivers could not be built anymore without those options present. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-2-ada@thorsis.com |
#
1323d08b |
|
30-Sep-2022 |
Alexander Dahl <post@lespocky.de> |
dm: fpga: Introduce new uclass For future DM based FPGA drivers and for now to have a meaningful logging class for old FPGA drivers. Suggested-by: Michal Simek <michal.simek@amd.com> Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Dahl <post@lespocky.de> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20220930120430.42307-2-post@lespocky.de Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
fb2b8856 |
|
22-Jul-2022 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
fpga: add option for loading FPGA secure bitstreams It allows using this feature without enabling the "fpga loads" command. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Co-developed-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-2-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
8c09cb6f |
|
21-Jul-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig This converts the following to Kconfig: SYS_FPGA_PROG_FEEDBACK Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-3-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e8ffc1df |
|
21-Jul-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Convert SYS_FPGA_CHECK_CTRLC to Kconfig After commit 8cca60a2cbf2 ("Kconfig: Remove some symbols from the whitelist") downstream builds failed for boards setting this in include/configs/… Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-2-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
6e52cb25 |
|
12-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_FPGA_STRATIX_V to Kconfig This converts the following to Kconfig: CONFIG_FPGA_STRATIX_V Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9a5bbdfd |
|
01-Mar-2021 |
Siew Chin Lim <elly.siew.chin.lim@intel.com> |
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> |
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> |
#
a225f810 |
|
23-Jul-2018 |
Michal Simek <michal.simek@amd.com> |
fpga: Kconfig: Replace spaces with tabs Trivial Kconfig cleanup. Use tabs instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
3990c9d6 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
f4158346 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
fpga: Added Kconfig support for FPGA_SPARTAN3 This patch added Kconfig support for FPGA_SPARTAN3 and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
fa23ba1a |
|
25-Jul-2017 |
Tien Fong Chee <tien.fong.chee@intel.com> |
kconfig: Convert FPGA_SOCFPGA configuration to Kconfig This converts the following to Kconfig: CONFIG_FPGA_SOCFPGA Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org> |
#
98d62e61 |
|
04-Nov-2016 |
Patrick Bruenn <p.bruenn@beckhoff.com> |
arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com> |
#
6b245014 |
|
13-Jan-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
6ded73aa |
|
19-Sep-2016 |
Michal Simek <michal.simek@amd.com> |
fpga: Add Kconfig to fpga subsystem Add missing Kconfig to fpga subsystem to be able to add new options. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
1edc21a7 |
|
01-Feb-2023 |
Simon Glass <sjg@chromium.org> |
fpga: Add a FPGA_STRATIX_II option There is no Kconfig option for this code, but it seems to be useful. Add one. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8badd336 |
|
01-Feb-2023 |
Simon Glass <sjg@chromium.org> |
fpga: Add a LATTICE option There is no Kconfig option for this code, but it seems to be useful. Add one. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8fe042be |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
fpga: Migrate CONFIG_MAX_FPGA_DEVICES to Kconfig This is always defined to 5, so use that as the default. Cc: Michal Simek <michal.simek@amd.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Michal Simek <michal.simek@amd.com> |
#
f00f676a |
|
04-Dec-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FPGA_CHECK_BUSY to Kconfig This converts the following to Kconfig: CONFIG_SYS_FPGA_CHECK_BUSY Signed-off-by: Tom Rini <trini@konsulko.com> |
#
312c4b11 |
|
07-Oct-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Add missing Kconfig symbols for old FPGA drivers Those drivers could not be built anymore without those options present. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-2-ada@thorsis.com |
#
1323d08b |
|
30-Sep-2022 |
Alexander Dahl <post@lespocky.de> |
dm: fpga: Introduce new uclass For future DM based FPGA drivers and for now to have a meaningful logging class for old FPGA drivers. Suggested-by: Michal Simek <michal.simek@amd.com> Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Dahl <post@lespocky.de> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20220930120430.42307-2-post@lespocky.de Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
fb2b8856 |
|
22-Jul-2022 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
fpga: add option for loading FPGA secure bitstreams It allows using this feature without enabling the "fpga loads" command. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Co-developed-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-2-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
8c09cb6f |
|
21-Jul-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig This converts the following to Kconfig: SYS_FPGA_PROG_FEEDBACK Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-3-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e8ffc1df |
|
21-Jul-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Convert SYS_FPGA_CHECK_CTRLC to Kconfig After commit 8cca60a2cbf2 ("Kconfig: Remove some symbols from the whitelist") downstream builds failed for boards setting this in include/configs/… Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-2-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
6e52cb25 |
|
12-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_FPGA_STRATIX_V to Kconfig This converts the following to Kconfig: CONFIG_FPGA_STRATIX_V Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9a5bbdfd |
|
01-Mar-2021 |
Siew Chin Lim <elly.siew.chin.lim@intel.com> |
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> |
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> |
#
a225f810 |
|
23-Jul-2018 |
Michal Simek <michal.simek@amd.com> |
fpga: Kconfig: Replace spaces with tabs Trivial Kconfig cleanup. Use tabs instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
3990c9d6 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
f4158346 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
fpga: Added Kconfig support for FPGA_SPARTAN3 This patch added Kconfig support for FPGA_SPARTAN3 and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
fa23ba1a |
|
25-Jul-2017 |
Tien Fong Chee <tien.fong.chee@intel.com> |
kconfig: Convert FPGA_SOCFPGA configuration to Kconfig This converts the following to Kconfig: CONFIG_FPGA_SOCFPGA Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org> |
#
98d62e61 |
|
04-Nov-2016 |
Patrick Bruenn <p.bruenn@beckhoff.com> |
arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com> |
#
6b245014 |
|
13-Jan-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
6ded73aa |
|
19-Sep-2016 |
Michal Simek <michal.simek@amd.com> |
fpga: Add Kconfig to fpga subsystem Add missing Kconfig to fpga subsystem to be able to add new options. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
8fe042be |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
fpga: Migrate CONFIG_MAX_FPGA_DEVICES to Kconfig This is always defined to 5, so use that as the default. Cc: Michal Simek <michal.simek@amd.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Michal Simek <michal.simek@amd.com> |
#
f00f676a |
|
04-Dec-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FPGA_CHECK_BUSY to Kconfig This converts the following to Kconfig: CONFIG_SYS_FPGA_CHECK_BUSY Signed-off-by: Tom Rini <trini@konsulko.com> |
#
312c4b11 |
|
07-Oct-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Add missing Kconfig symbols for old FPGA drivers Those drivers could not be built anymore without those options present. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-2-ada@thorsis.com |
#
1323d08b |
|
30-Sep-2022 |
Alexander Dahl <post@lespocky.de> |
dm: fpga: Introduce new uclass For future DM based FPGA drivers and for now to have a meaningful logging class for old FPGA drivers. Suggested-by: Michal Simek <michal.simek@amd.com> Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Dahl <post@lespocky.de> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20220930120430.42307-2-post@lespocky.de Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
fb2b8856 |
|
22-Jul-2022 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
fpga: add option for loading FPGA secure bitstreams It allows using this feature without enabling the "fpga loads" command. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Co-developed-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-2-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
8c09cb6f |
|
21-Jul-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig This converts the following to Kconfig: SYS_FPGA_PROG_FEEDBACK Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-3-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e8ffc1df |
|
21-Jul-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Convert SYS_FPGA_CHECK_CTRLC to Kconfig After commit 8cca60a2cbf2 ("Kconfig: Remove some symbols from the whitelist") downstream builds failed for boards setting this in include/configs/… Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-2-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
6e52cb25 |
|
12-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_FPGA_STRATIX_V to Kconfig This converts the following to Kconfig: CONFIG_FPGA_STRATIX_V Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9a5bbdfd |
|
01-Mar-2021 |
Siew Chin Lim <elly.siew.chin.lim@intel.com> |
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> |
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> |
#
a225f810 |
|
23-Jul-2018 |
Michal Simek <michal.simek@amd.com> |
fpga: Kconfig: Replace spaces with tabs Trivial Kconfig cleanup. Use tabs instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
3990c9d6 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
f4158346 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
fpga: Added Kconfig support for FPGA_SPARTAN3 This patch added Kconfig support for FPGA_SPARTAN3 and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
fa23ba1a |
|
25-Jul-2017 |
Tien Fong Chee <tien.fong.chee@intel.com> |
kconfig: Convert FPGA_SOCFPGA configuration to Kconfig This converts the following to Kconfig: CONFIG_FPGA_SOCFPGA Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org> |
#
98d62e61 |
|
04-Nov-2016 |
Patrick Bruenn <p.bruenn@beckhoff.com> |
arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com> |
#
6b245014 |
|
13-Jan-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
6ded73aa |
|
19-Sep-2016 |
Michal Simek <michal.simek@amd.com> |
fpga: Add Kconfig to fpga subsystem Add missing Kconfig to fpga subsystem to be able to add new options. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
f00f676a |
|
04-Dec-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FPGA_CHECK_BUSY to Kconfig This converts the following to Kconfig: CONFIG_SYS_FPGA_CHECK_BUSY Signed-off-by: Tom Rini <trini@konsulko.com> |
#
312c4b11 |
|
07-Oct-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Add missing Kconfig symbols for old FPGA drivers Those drivers could not be built anymore without those options present. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-2-ada@thorsis.com |
#
1323d08b |
|
30-Sep-2022 |
Alexander Dahl <post@lespocky.de> |
dm: fpga: Introduce new uclass For future DM based FPGA drivers and for now to have a meaningful logging class for old FPGA drivers. Suggested-by: Michal Simek <michal.simek@amd.com> Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Dahl <post@lespocky.de> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20220930120430.42307-2-post@lespocky.de Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
fb2b8856 |
|
22-Jul-2022 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
fpga: add option for loading FPGA secure bitstreams It allows using this feature without enabling the "fpga loads" command. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Co-developed-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-2-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
8c09cb6f |
|
21-Jul-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig This converts the following to Kconfig: SYS_FPGA_PROG_FEEDBACK Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-3-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e8ffc1df |
|
21-Jul-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Convert SYS_FPGA_CHECK_CTRLC to Kconfig After commit 8cca60a2cbf2 ("Kconfig: Remove some symbols from the whitelist") downstream builds failed for boards setting this in include/configs/… Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-2-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
6e52cb25 |
|
12-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_FPGA_STRATIX_V to Kconfig This converts the following to Kconfig: CONFIG_FPGA_STRATIX_V Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9a5bbdfd |
|
01-Mar-2021 |
Siew Chin Lim <elly.siew.chin.lim@intel.com> |
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> |
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> |
#
a225f810 |
|
23-Jul-2018 |
Michal Simek <michal.simek@amd.com> |
fpga: Kconfig: Replace spaces with tabs Trivial Kconfig cleanup. Use tabs instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
3990c9d6 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
f4158346 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
fpga: Added Kconfig support for FPGA_SPARTAN3 This patch added Kconfig support for FPGA_SPARTAN3 and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
fa23ba1a |
|
25-Jul-2017 |
Tien Fong Chee <tien.fong.chee@intel.com> |
kconfig: Convert FPGA_SOCFPGA configuration to Kconfig This converts the following to Kconfig: CONFIG_FPGA_SOCFPGA Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org> |
#
98d62e61 |
|
04-Nov-2016 |
Patrick Bruenn <p.bruenn@beckhoff.com> |
arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com> |
#
6b245014 |
|
13-Jan-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
6ded73aa |
|
19-Sep-2016 |
Michal Simek <michal.simek@amd.com> |
fpga: Add Kconfig to fpga subsystem Add missing Kconfig to fpga subsystem to be able to add new options. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
312c4b11 |
|
07-Oct-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Add missing Kconfig symbols for old FPGA drivers Those drivers could not be built anymore without those options present. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-2-ada@thorsis.com |
#
1323d08b |
|
30-Sep-2022 |
Alexander Dahl <post@lespocky.de> |
dm: fpga: Introduce new uclass For future DM based FPGA drivers and for now to have a meaningful logging class for old FPGA drivers. Suggested-by: Michal Simek <michal.simek@amd.com> Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Dahl <post@lespocky.de> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20220930120430.42307-2-post@lespocky.de Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
fb2b8856 |
|
22-Jul-2022 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
fpga: add option for loading FPGA secure bitstreams It allows using this feature without enabling the "fpga loads" command. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Co-developed-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-2-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
8c09cb6f |
|
21-Jul-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig This converts the following to Kconfig: SYS_FPGA_PROG_FEEDBACK Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-3-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e8ffc1df |
|
21-Jul-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Convert SYS_FPGA_CHECK_CTRLC to Kconfig After commit 8cca60a2cbf2 ("Kconfig: Remove some symbols from the whitelist") downstream builds failed for boards setting this in include/configs/… Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-2-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
6e52cb25 |
|
12-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_FPGA_STRATIX_V to Kconfig This converts the following to Kconfig: CONFIG_FPGA_STRATIX_V Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9a5bbdfd |
|
01-Mar-2021 |
Siew Chin Lim <elly.siew.chin.lim@intel.com> |
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> |
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> |
#
a225f810 |
|
23-Jul-2018 |
Michal Simek <michal.simek@amd.com> |
fpga: Kconfig: Replace spaces with tabs Trivial Kconfig cleanup. Use tabs instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
3990c9d6 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
f4158346 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
fpga: Added Kconfig support for FPGA_SPARTAN3 This patch added Kconfig support for FPGA_SPARTAN3 and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
fa23ba1a |
|
25-Jul-2017 |
Tien Fong Chee <tien.fong.chee@intel.com> |
kconfig: Convert FPGA_SOCFPGA configuration to Kconfig This converts the following to Kconfig: CONFIG_FPGA_SOCFPGA Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org> |
#
98d62e61 |
|
04-Nov-2016 |
Patrick Bruenn <p.bruenn@beckhoff.com> |
arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com> |
#
6b245014 |
|
13-Jan-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
6ded73aa |
|
19-Sep-2016 |
Michal Simek <michal.simek@amd.com> |
fpga: Add Kconfig to fpga subsystem Add missing Kconfig to fpga subsystem to be able to add new options. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
fb2b8856 |
|
22-Jul-2022 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
fpga: add option for loading FPGA secure bitstreams It allows using this feature without enabling the "fpga loads" command. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Co-developed-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-2-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
8c09cb6f |
|
21-Jul-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig This converts the following to Kconfig: SYS_FPGA_PROG_FEEDBACK Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-3-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e8ffc1df |
|
21-Jul-2022 |
Alexander Dahl <ada@thorsis.com> |
fpga: Convert SYS_FPGA_CHECK_CTRLC to Kconfig After commit 8cca60a2cbf2 ("Kconfig: Remove some symbols from the whitelist") downstream builds failed for boards setting this in include/configs/… Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-2-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
6e52cb25 |
|
12-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_FPGA_STRATIX_V to Kconfig This converts the following to Kconfig: CONFIG_FPGA_STRATIX_V Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9a5bbdfd |
|
01-Mar-2021 |
Siew Chin Lim <elly.siew.chin.lim@intel.com> |
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> |
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> |
#
a225f810 |
|
23-Jul-2018 |
Michal Simek <michal.simek@amd.com> |
fpga: Kconfig: Replace spaces with tabs Trivial Kconfig cleanup. Use tabs instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
3990c9d6 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
f4158346 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
fpga: Added Kconfig support for FPGA_SPARTAN3 This patch added Kconfig support for FPGA_SPARTAN3 and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
fa23ba1a |
|
25-Jul-2017 |
Tien Fong Chee <tien.fong.chee@intel.com> |
kconfig: Convert FPGA_SOCFPGA configuration to Kconfig This converts the following to Kconfig: CONFIG_FPGA_SOCFPGA Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org> |
#
98d62e61 |
|
04-Nov-2016 |
Patrick Bruenn <p.bruenn@beckhoff.com> |
arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com> |
#
6b245014 |
|
13-Jan-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
6ded73aa |
|
19-Sep-2016 |
Michal Simek <michal.simek@amd.com> |
fpga: Add Kconfig to fpga subsystem Add missing Kconfig to fpga subsystem to be able to add new options. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
6e52cb25 |
|
12-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_FPGA_STRATIX_V to Kconfig This converts the following to Kconfig: CONFIG_FPGA_STRATIX_V Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9a5bbdfd |
|
01-Mar-2021 |
Siew Chin Lim <elly.siew.chin.lim@intel.com> |
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> |
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> |
#
a225f810 |
|
23-Jul-2018 |
Michal Simek <michal.simek@amd.com> |
fpga: Kconfig: Replace spaces with tabs Trivial Kconfig cleanup. Use tabs instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
3990c9d6 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
f4158346 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
fpga: Added Kconfig support for FPGA_SPARTAN3 This patch added Kconfig support for FPGA_SPARTAN3 and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
fa23ba1a |
|
25-Jul-2017 |
Tien Fong Chee <tien.fong.chee@intel.com> |
kconfig: Convert FPGA_SOCFPGA configuration to Kconfig This converts the following to Kconfig: CONFIG_FPGA_SOCFPGA Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org> |
#
98d62e61 |
|
04-Nov-2016 |
Patrick Bruenn <p.bruenn@beckhoff.com> |
arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com> |
#
6b245014 |
|
13-Jan-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
6ded73aa |
|
19-Sep-2016 |
Michal Simek <michal.simek@amd.com> |
fpga: Add Kconfig to fpga subsystem Add missing Kconfig to fpga subsystem to be able to add new options. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
9a5bbdfd |
|
01-Mar-2021 |
Siew Chin Lim <elly.siew.chin.lim@intel.com> |
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> |
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> |
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> |
#
a225f810 |
|
23-Jul-2018 |
Michal Simek <michal.simek@xilinx.com> |
fpga: Kconfig: Replace spaces with tabs Trivial Kconfig cleanup. Use tabs instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
3990c9d6 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
f4158346 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
fpga: Added Kconfig support for FPGA_SPARTAN3 This patch added Kconfig support for FPGA_SPARTAN3 and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
#
fa23ba1a |
|
25-Jul-2017 |
Tien Fong Chee <tien.fong.chee@intel.com> |
kconfig: Convert FPGA_SOCFPGA configuration to Kconfig This converts the following to Kconfig: CONFIG_FPGA_SOCFPGA Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org> |
#
98d62e61 |
|
04-Nov-2016 |
Patrick Bruenn <p.bruenn@beckhoff.com> |
arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com> |
#
6b245014 |
|
13-Jan-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
6ded73aa |
|
19-Sep-2016 |
Michal Simek <michal.simek@xilinx.com> |
fpga: Add Kconfig to fpga subsystem Add missing Kconfig to fpga subsystem to be able to add new options. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
bd99fa59 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
d2170168 |
|
06-Aug-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
25d63a36 |
|
18-Jun-2019 |
Robert Hancock <hancock@sedsystems.ca> |
fpga: virtex2: added Kconfig option Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
c41e660b |
|
19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
|
#
a225f810 |
|
23-Jul-2018 |
Michal Simek <michal.simek@xilinx.com> |
fpga: Kconfig: Replace spaces with tabs Trivial Kconfig cleanup. Use tabs instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
3990c9d6 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
|
#
f4158346 |
|
16-Feb-2018 |
Vipul Kumar <vipul.kumar@xilinx.com> |
fpga: Added Kconfig support for FPGA_SPARTAN3 This patch added Kconfig support for FPGA_SPARTAN3 and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
|
#
fa23ba1a |
|
25-Jul-2017 |
Tien Fong Chee <tien.fong.chee@intel.com> |
kconfig: Convert FPGA_SOCFPGA configuration to Kconfig This converts the following to Kconfig: CONFIG_FPGA_SOCFPGA Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
|
#
98d62e61 |
|
04-Nov-2016 |
Patrick Bruenn <p.bruenn@beckhoff.com> |
arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
|
#
6b245014 |
|
13-Jan-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
6ded73aa |
|
19-Sep-2016 |
Michal Simek <michal.simek@xilinx.com> |
fpga: Add Kconfig to fpga subsystem Add missing Kconfig to fpga subsystem to be able to add new options. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|