1// SPDX-License-Identifier: BSD-3-Clause AND GPL-2.0 2/* 3 * Clock and reset drivers for Qualcomm platforms Global Clock 4 * Controller (GCC). 5 * 6 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> 7 * (C) Copyright 2020 Sartura Ltd. (reset driver) 8 * Author: Robert Marko <robert.marko@sartura.hr> 9 * (C) Copyright 2022 Linaro Ltd. (reset driver) 10 * Author: Sumit Garg <sumit.garg@linaro.org> 11 * 12 * Based on Little Kernel driver, simplified 13 */ 14 15#include <common.h> 16#include <clk-uclass.h> 17#include <dm.h> 18#include <dm/device-internal.h> 19#include <dm/lists.h> 20#include <errno.h> 21#include <asm/io.h> 22#include <linux/bug.h> 23#include <linux/delay.h> 24#include <linux/bitops.h> 25#include <linux/iopoll.h> 26#include <reset-uclass.h> 27#include <power-domain-uclass.h> 28 29#include "clock-qcom.h" 30 31/* CBCR register fields */ 32#define CBCR_BRANCH_ENABLE_BIT BIT(0) 33#define CBCR_BRANCH_OFF_BIT BIT(31) 34 35#define GDSC_SW_COLLAPSE_MASK BIT(0) 36#define GDSC_POWER_DOWN_COMPLETE BIT(15) 37#define GDSC_POWER_UP_COMPLETE BIT(16) 38#define GDSC_PWR_ON_MASK BIT(31) 39#define CFG_GDSCR_OFFSET 0x4 40#define GDSC_STATUS_POLL_TIMEOUT_US 1500 41 42/* Enable clock controlled by CBC soft macro */ 43void clk_enable_cbc(phys_addr_t cbcr) 44{ 45 setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT); 46 47 while (readl(cbcr) & CBCR_BRANCH_OFF_BIT) 48 ; 49} 50 51void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0) 52{ 53 if (readl(base + gpll0->status) & gpll0->status_bit) 54 return; /* clock already enabled */ 55 56 setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit); 57 58 while ((readl(base + gpll0->status) & gpll0->status_bit) == 0) 59 ; 60} 61 62#define BRANCH_ON_VAL (0) 63#define BRANCH_NOC_FSM_ON_VAL BIT(29) 64#define BRANCH_CHECK_MASK GENMASK(31, 28) 65 66void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) 67{ 68 u32 val; 69 70 setbits_le32(base + vclk->ena_vote, vclk->vote_bit); 71 do { 72 val = readl(base + vclk->cbcr_reg); 73 val &= BRANCH_CHECK_MASK; 74 } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL)); 75} 76 77#define APPS_CMD_RCGR_UPDATE BIT(0) 78 79/* Update clock command via CMD_RCGR */ 80void clk_bcr_update(phys_addr_t apps_cmd_rcgr) 81{ 82 u32 count; 83 setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE); 84 85 /* Wait for frequency to be updated. */ 86 for (count = 0; count < 50000; count++) { 87 if (!(readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE)) 88 break; 89 udelay(1); 90 } 91 WARN(count == 50000, "WARNING: RCG @ %#llx [%#010x] stuck at off\n", 92 apps_cmd_rcgr, readl(apps_cmd_rcgr)); 93} 94 95#define CFG_SRC_DIV_MASK 0b11111 96#define CFG_SRC_SEL_SHIFT 8 97#define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT) 98#define CFG_MODE_SHIFT 12 99#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT) 100#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT) 101#define CFG_HW_CLK_CTRL_MASK BIT(20) 102 103/* 104 * root set rate for clocks with half integer and MND divider 105 * div should be pre-calculated ((div * 2) - 1) 106 */ 107void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, 108 int div, int m, int n, int source, u8 mnd_width) 109{ 110 u32 cfg; 111 /* M value for MND divider. */ 112 u32 m_val = m; 113 u32 n_minus_m = n - m; 114 /* NOT(N-M) value for MND divider. */ 115 u32 n_val = ~n_minus_m * !!(n); 116 /* NOT 2D value for MND divider. */ 117 u32 d_val = ~(clamp_t(u32, n, m, n_minus_m)); 118 u32 mask = BIT(mnd_width) - 1; 119 120 debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask); 121 122 /* Program MND values */ 123 writel(m_val & mask, base + cmd_rcgr + RCG_M_REG); 124 writel(n_val & mask, base + cmd_rcgr + RCG_N_REG); 125 writel(d_val & mask, base + cmd_rcgr + RCG_D_REG); 126 127 /* setup src select and divider */ 128 cfg = readl(base + cmd_rcgr + RCG_CFG_REG); 129 cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK | 130 CFG_SRC_DIV_MASK); 131 cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */ 132 133 if (div) 134 cfg |= div & CFG_SRC_DIV_MASK; 135 136 if (n && n != m) 137 cfg |= CFG_MODE_DUAL_EDGE; 138 139 writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */ 140 141 /* Inform h/w to start using the new config. */ 142 clk_bcr_update(base + cmd_rcgr); 143} 144 145/* root set rate for clocks with half integer and mnd_width=0 */ 146void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, 147 int source) 148{ 149 u32 cfg; 150 151 /* setup src select and divider */ 152 cfg = readl(base + cmd_rcgr + RCG_CFG_REG); 153 cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); 154 cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ 155 156 /* 157 * Set the divider; HW permits fraction dividers (+0.5), but 158 * for simplicity, we will support integers only 159 */ 160 if (div) 161 cfg |= (2 * div - 1) & CFG_SRC_DIV_MASK; 162 163 writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */ 164 165 /* Inform h/w to start using the new config. */ 166 clk_bcr_update(base + cmd_rcgr); 167} 168 169const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) 170{ 171 if (!f) 172 return NULL; 173 174 if (!f->freq) 175 return f; 176 177 for (; f->freq; f++) 178 if (rate <= f->freq) 179 return f; 180 181 /* Default to our fastest rate */ 182 return f - 1; 183} 184 185static int msm_clk_probe(struct udevice *dev) 186{ 187 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); 188 struct msm_clk_priv *priv = dev_get_priv(dev); 189 190 priv->base = dev_read_addr(dev); 191 if (priv->base == FDT_ADDR_T_NONE) 192 return -EINVAL; 193 194 priv->data = data; 195 196 return 0; 197} 198 199static ulong msm_clk_set_rate(struct clk *clk, ulong rate) 200{ 201 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(clk->dev); 202 203 if (data->set_rate) 204 return data->set_rate(clk, rate); 205 206 return 0; 207} 208 209static int msm_clk_enable(struct clk *clk) 210{ 211 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(clk->dev); 212 213 if (data->enable) 214 return data->enable(clk); 215 216 return 0; 217} 218 219static struct clk_ops msm_clk_ops = { 220 .set_rate = msm_clk_set_rate, 221 .enable = msm_clk_enable, 222}; 223 224U_BOOT_DRIVER(qcom_clk) = { 225 .name = "qcom_clk", 226 .id = UCLASS_CLK, 227 .ops = &msm_clk_ops, 228 .priv_auto = sizeof(struct msm_clk_priv), 229 .probe = msm_clk_probe, 230 .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, 231}; 232 233int qcom_cc_bind(struct udevice *parent) 234{ 235 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent); 236 struct udevice *clkdev = NULL, *rstdev = NULL, *pwrdev; 237 struct driver *drv; 238 int ret; 239 240 /* Get a handle to the common clk handler */ 241 drv = lists_driver_lookup_name("qcom_clk"); 242 if (!drv) 243 return -ENOENT; 244 245 /* Register the clock controller */ 246 ret = device_bind_with_driver_data(parent, drv, "qcom_clk", (ulong)data, 247 dev_ofnode(parent), &clkdev); 248 if (ret) 249 return ret; 250 251 if (data->resets) { 252 /* Get a handle to the common reset handler */ 253 drv = lists_driver_lookup_name("qcom_reset"); 254 if (!drv) { 255 ret = -ENOENT; 256 goto unbind_clkdev; 257 } 258 259 /* Register the reset controller */ 260 ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data, 261 dev_ofnode(parent), &rstdev); 262 if (ret) 263 goto unbind_clkdev; 264 } 265 266 if (data->power_domains) { 267 /* Get a handle to the common power domain handler */ 268 drv = lists_driver_lookup_name("qcom_power"); 269 if (!drv) { 270 ret = -ENOENT; 271 goto unbind_rstdev; 272 } 273 /* Register the power domain controller */ 274 ret = device_bind_with_driver_data(parent, drv, "qcom_power", (ulong)data, 275 dev_ofnode(parent), &pwrdev); 276 if (ret) 277 goto unbind_rstdev; 278 } 279 280 return 0; 281 282unbind_rstdev: 283 device_unbind(rstdev); 284unbind_clkdev: 285 device_unbind(clkdev); 286 287 return ret; 288} 289 290static int qcom_reset_set(struct reset_ctl *rst, bool assert) 291{ 292 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(rst->dev); 293 void __iomem *base = dev_get_priv(rst->dev); 294 const struct qcom_reset_map *map; 295 u32 value; 296 297 map = &data->resets[rst->id]; 298 299 value = readl(base + map->reg); 300 301 if (assert) 302 value |= BIT(map->bit); 303 else 304 value &= ~BIT(map->bit); 305 306 writel(value, base + map->reg); 307 308 return 0; 309} 310 311static int qcom_reset_assert(struct reset_ctl *rst) 312{ 313 return qcom_reset_set(rst, true); 314} 315 316static int qcom_reset_deassert(struct reset_ctl *rst) 317{ 318 return qcom_reset_set(rst, false); 319} 320 321static const struct reset_ops qcom_reset_ops = { 322 .rst_assert = qcom_reset_assert, 323 .rst_deassert = qcom_reset_deassert, 324}; 325 326static int qcom_reset_probe(struct udevice *dev) 327{ 328 /* Set our priv pointer to the base address */ 329 dev_set_priv(dev, (void *)dev_read_addr(dev)); 330 331 return 0; 332} 333 334U_BOOT_DRIVER(qcom_reset) = { 335 .name = "qcom_reset", 336 .id = UCLASS_RESET, 337 .ops = &qcom_reset_ops, 338 .probe = qcom_reset_probe, 339}; 340 341static int qcom_power_set(struct power_domain *pwr, bool on) 342{ 343 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev); 344 void __iomem *base = dev_get_priv(pwr->dev); 345 const struct qcom_power_map *map; 346 u32 value; 347 int ret; 348 349 if (pwr->id >= data->num_power_domains) 350 return -ENODEV; 351 352 map = &data->power_domains[pwr->id]; 353 354 if (!map->reg) 355 return -ENODEV; 356 357 value = readl(base + map->reg); 358 359 if (on) 360 value &= ~GDSC_SW_COLLAPSE_MASK; 361 else 362 value |= GDSC_SW_COLLAPSE_MASK; 363 364 writel(value, base + map->reg); 365 366 if (on) 367 ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET, 368 value, 369 (value & GDSC_POWER_UP_COMPLETE) || 370 (value & GDSC_PWR_ON_MASK), 371 GDSC_STATUS_POLL_TIMEOUT_US); 372 373 else 374 ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET, 375 value, 376 (value & GDSC_POWER_DOWN_COMPLETE) || 377 !(value & GDSC_PWR_ON_MASK), 378 GDSC_STATUS_POLL_TIMEOUT_US); 379 380 381 if (ret == -ETIMEDOUT) 382 printf("WARNING: GDSC %lu is stuck during power on/off\n", 383 pwr->id); 384 return ret; 385} 386 387static int qcom_power_on(struct power_domain *pwr) 388{ 389 return qcom_power_set(pwr, true); 390} 391 392static int qcom_power_off(struct power_domain *pwr) 393{ 394 return qcom_power_set(pwr, false); 395} 396 397static const struct power_domain_ops qcom_power_ops = { 398 .on = qcom_power_on, 399 .off = qcom_power_off, 400}; 401 402static int qcom_power_probe(struct udevice *dev) 403{ 404 /* Set our priv pointer to the base address */ 405 dev_set_priv(dev, (void *)dev_read_addr(dev)); 406 407 return 0; 408} 409 410U_BOOT_DRIVER(qcom_power) = { 411 .name = "qcom_power", 412 .id = UCLASS_POWER_DOMAIN, 413 .ops = &qcom_power_ops, 414 .probe = qcom_power_probe, 415 .flags = DM_FLAG_PRE_RELOC, 416}; 417