#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d33d4e0a |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use offsets for RCG registers The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8670cb40 |
|
03-Apr-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
mach-snapdragon: disable power-domains for pre-reloc drivers Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
b563e766 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: add support for power domains uclass Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
054eb877 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> [caleb: minor wording fix] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
37ea1343 |
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06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
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#
3ead6616 |
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06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
fac2121a |
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06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
a623c14f |
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06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
d5db46cf |
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06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
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#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d5db46cf |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: fix rcg divider value The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
6acc4431 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
37ea1343 |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: use function pointers for enable and set_rate Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: remove additional sysmap-sdm845.h mention]
|
#
3ead6616 |
|
06-Nov-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk/qcom: handle resets and clocks in one device Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
fac2121a |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a623c14f |
|
06-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
clk/qcom: move from mach-snapdragon Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|