1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2021 Gateworks Corporation 4 */ 5 6#include <fdt_support.h> 7#include <init.h> 8#include <led.h> 9#include <mmc.h> 10#include <miiphy.h> 11#include <mmc.h> 12#include <asm/arch/clock.h> 13#include <asm/arch/sys_proto.h> 14#include <asm/mach-imx/boot_mode.h> 15 16#include "eeprom.h" 17 18int board_phys_sdram_size(phys_size_t *size) 19{ 20 if (!size) 21 return -EINVAL; 22 23 *size = get_ram_size((void *)PHYS_SDRAM, (long)PHYS_SDRAM_SIZE + (long)PHYS_SDRAM_2_SIZE); 24 25 return 0; 26} 27 28int board_fit_config_name_match(const char *path) 29{ 30 const char *name = path + strlen("freescale/"); 31 static char init; 32 const char *dtb; 33 char buf[32]; 34 int i = 0; 35 36 do { 37 dtb = eeprom_get_dtb_name(i++, buf, sizeof(buf)); 38 if (!strcmp(dtb, name)) { 39 if (!init++) 40 printf("DTB : %s\n", name); 41 return 0; 42 } 43 } while (dtb); 44 45 return -1; 46} 47 48static int __maybe_unused setup_fec(void) 49{ 50 struct iomuxc_gpr_base_regs *gpr = 51 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 52 53#ifndef CONFIG_IMX8MP 54 /* Use 125M anatop REF_CLK1 for ENET1, not from external */ 55 clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); 56#else 57 /* Enable RGMII TX clk output */ 58 setbits_le32(&gpr->gpr[1], BIT(22)); 59#endif 60 61 return 0; 62} 63 64#if (IS_ENABLED(CONFIG_NET)) 65int board_phy_config(struct phy_device *phydev) 66{ 67 unsigned short val; 68 69 switch (phydev->phy_id) { 70 case 0x2000a231: /* TI DP83867 GbE PHY */ 71 puts("DP83867 "); 72 /* LED configuration */ 73 val = 0; 74 val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */ 75 val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */ 76 phy_write(phydev, MDIO_DEVAD_NONE, 24, val); 77 break; 78 } 79 80 if (phydev->drv->config) 81 phydev->drv->config(phydev); 82 83 return 0; 84} 85#endif // IS_ENABLED(CONFIG_NET) 86 87int board_init(void) 88{ 89 venice_eeprom_init(1); 90 91 if (IS_ENABLED(CONFIG_FEC_MXC)) 92 setup_fec(); 93 94 return 0; 95} 96 97int board_late_init(void) 98{ 99 const char *str; 100 struct mmc *mmc = NULL; 101 char env[32]; 102 int ret, i; 103 u8 enetaddr[6]; 104 char fdt[64]; 105 int bootdev; 106 107 /* Set board serial/model */ 108 if (!env_get("serial#")) 109 env_set_ulong("serial#", eeprom_get_serial()); 110 env_set("model", eeprom_get_model()); 111 112 /* Set fdt_file vars */ 113 i = 0; 114 do { 115 str = eeprom_get_dtb_name(i, fdt, sizeof(fdt)); 116 if (str) { 117 sprintf(env, "fdt_file%d", i + 1); 118 strcat(fdt, ".dtb"); 119 env_set(env, fdt); 120 } 121 i++; 122 } while (str); 123 124 /* Set mac addrs */ 125 i = 0; 126 do { 127 if (i) 128 sprintf(env, "eth%daddr", i); 129 else 130 sprintf(env, "ethaddr"); 131 str = env_get(env); 132 if (!str) { 133 ret = eeprom_getmac(i, enetaddr); 134 if (!ret) 135 eth_env_set_enetaddr(env, enetaddr); 136 } 137 i++; 138 } while (!ret); 139 140 /* 141 * set bootdev/bootblk/bootpart (used in firmware_update script) 142 * dynamically depending on boot device and SoC 143 */ 144 bootdev = -1; 145 switch (get_boot_device()) { 146 case SD1_BOOT: 147 case MMC1_BOOT: /* SDHC1 */ 148 bootdev = 0; 149 break; 150 case SD2_BOOT: 151 case MMC2_BOOT: /* SDHC2 */ 152 bootdev = 1; 153 break; 154 case SD3_BOOT: 155 case MMC3_BOOT: /* SDHC3 */ 156 bootdev = 2; 157 break; 158 default: 159 bootdev = 2; /* assume SDHC3 (eMMC) if booting over SDP */ 160 break; 161 } 162 if (bootdev != -1) 163 mmc = find_mmc_device(bootdev); 164 if (mmc) { 165 int bootblk; 166 167 if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) 168 bootblk = 32 * SZ_1K / 512; 169 else 170 bootblk = 33 * SZ_1K / 512; 171 mmc_init(mmc); 172 if (!IS_SD(mmc)) { 173 int bootpart; 174 175 switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { 176 case 1: /* boot0 */ 177 bootpart = 1; 178 break; 179 case 2: /* boot1 */ 180 bootpart = 2; 181 break; 182 case 7: /* user */ 183 default: 184 bootpart = 0; 185 break; 186 } 187 /* IMX8MP/IMX8MN BOOTROM v2 uses offset=0 for boot parts */ 188 if ((IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) && 189 (bootpart == 1 || bootpart == 2)) 190 bootblk = 0; 191 env_set_hex("bootpart", bootpart); 192 env_set_hex("bootblk", bootblk); 193 } else { /* SD */ 194 env_set("bootpart", ""); 195 env_set_hex("bootblk", bootblk); 196 } 197 env_set_hex("dev", bootdev); 198 } 199 200 /* override soc=imx8m to provide a more specific soc name */ 201 if (IS_ENABLED(CONFIG_IMX8MN)) 202 env_set("soc", "imx8mn"); 203 else if (IS_ENABLED(CONFIG_IMX8MP)) 204 env_set("soc", "imx8mp"); 205 else if (IS_ENABLED(CONFIG_IMX8MM)) 206 env_set("soc", "imx8mm"); 207 208 return 0; 209} 210 211int board_mmc_get_env_dev(int devno) 212{ 213 return devno; 214} 215 216uint mmc_get_env_part(struct mmc *mmc) 217{ 218 if (!IS_SD(mmc)) { 219 switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { 220 case 1: 221 return 1; 222 case 2: 223 return 2; 224 } 225 } 226 227 return 0; 228} 229 230int ft_board_setup(void *fdt, struct bd_info *bd) 231{ 232 const char *base_model = eeprom_get_baseboard_model(); 233 const char *path; 234 char pcbrev; 235 int off; 236 237 /* set board model dt prop */ 238 fdt_setprop_string(fdt, 0, "board", eeprom_get_model()); 239 240 if (!strncmp(base_model, "GW73", 4)) { 241 pcbrev = get_pcb_rev(base_model); 242 path = fdt_get_alias(fdt, "ethernet1"); 243 244 if (pcbrev > 'B' && pcbrev < 'E' && path && !strncmp(path, "/soc@0/pcie@", 12)) { 245 printf("adjusting %s pcie\n", base_model); 246 /* 247 * revC/D/E has PCIe 4-port switch which changes 248 * ethernet1 PCIe GbE: 249 * from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0 250 * to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0 251 */ 252 off = fdt_path_offset(fdt, "ethernet1"); 253 if (off > 0) { 254 u32 reg[5]; 255 256 fdt_set_name(fdt, off, "pcie@5,0"); 257 off = fdt_parent_offset(fdt, off); 258 fdt_set_name(fdt, off, "pcie@2,3"); 259 memset(reg, 0, sizeof(reg)); 260 reg[0] = cpu_to_fdt32(PCI_DEVFN(3, 0)); 261 fdt_setprop(fdt, off, "reg", reg, sizeof(reg)); 262 } 263 } 264 } 265 266 return 0; 267} 268