1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 * Copyright 2021 NXP 5 */ 6 7#include <common.h> 8#include <command.h> 9#include <fdt_support.h> 10#include <hang.h> 11#include <i2c.h> 12#include <asm/cache.h> 13#include <init.h> 14#include <asm/global_data.h> 15#include <asm/io.h> 16#include <asm/arch/clock.h> 17#include <asm/arch/fsl_serdes.h> 18#include <asm/arch/mmu.h> 19#include <asm/arch/soc.h> 20#include <hwconfig.h> 21#include <ahci.h> 22#include <mmc.h> 23#include <scsi.h> 24#include <fsl_esdhc.h> 25#include <env_internal.h> 26#include <fsl_mmdc.h> 27#include <netdev.h> 28#include <net/pfe_eth/pfe/pfe_hw.h> 29 30DECLARE_GLOBAL_DATA_PTR; 31 32#define BOOT_FROM_UPPER_BANK 0x2 33#define BOOT_FROM_LOWER_BANK 0x1 34 35int checkboard(void) 36{ 37#ifdef CONFIG_TARGET_LS1012ARDB 38 u8 in1; 39 int ret, bus_num = 0; 40 41 puts("Board: LS1012ARDB "); 42 43 /* Initialize i2c early for Serial flash bank information */ 44#if CONFIG_IS_ENABLED(DM_I2C) 45 struct udevice *dev; 46 47 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR, 48 1, &dev); 49 if (ret) { 50 printf("%s: Cannot find udev for a bus %d\n", __func__, 51 bus_num); 52 return -ENXIO; 53 } 54 ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1); 55#else /* Non DM I2C support - will be removed */ 56 i2c_set_bus_num(bus_num); 57 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1); 58#endif 59 if (ret < 0) { 60 printf("Error reading i2c boot information!\n"); 61 return 0; /* Don't want to hang() on this error */ 62 } 63 64 puts("Version"); 65 switch (in1 & SW_REV_MASK) { 66 case SW_REV_A: 67 puts(": RevA"); 68 break; 69 case SW_REV_B: 70 puts(": RevB"); 71 break; 72 case SW_REV_C: 73 puts(": RevC"); 74 break; 75 case SW_REV_C1: 76 puts(": RevC1"); 77 break; 78 case SW_REV_C2: 79 puts(": RevC2"); 80 break; 81 case SW_REV_D: 82 puts(": RevD"); 83 break; 84 case SW_REV_E: 85 puts(": RevE"); 86 break; 87 default: 88 puts(": unknown"); 89 break; 90 } 91 92 printf(", boot from QSPI"); 93 if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU) 94 puts(": emu\n"); 95 else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1) 96 puts(": bank1\n"); 97 else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2) 98 puts(": bank2\n"); 99 else 100 puts("unknown\n"); 101#else 102 103 puts("Board: LS1012A2G5RDB "); 104#endif 105 return 0; 106} 107 108#ifdef CONFIG_TFABOOT 109int dram_init(void) 110{ 111 gd->ram_size = tfa_get_dram_size(); 112 if (!gd->ram_size) 113 gd->ram_size = CFG_SYS_SDRAM_SIZE; 114 115 return 0; 116} 117#else 118int dram_init(void) 119{ 120#ifndef CONFIG_TFABOOT 121 static const struct fsl_mmdc_info mparam = { 122 0x05180000, /* mdctl */ 123 0x00030035, /* mdpdc */ 124 0x12554000, /* mdotc */ 125 0xbabf7954, /* mdcfg0 */ 126 0xdb328f64, /* mdcfg1 */ 127 0x01ff00db, /* mdcfg2 */ 128 0x00001680, /* mdmisc */ 129 0x0f3c8000, /* mdref */ 130 0x00002000, /* mdrwd */ 131 0x00bf1023, /* mdor */ 132 0x0000003f, /* mdasp */ 133 0x0000022a, /* mpodtctrl */ 134 0xa1390003, /* mpzqhwctrl */ 135 }; 136 137 mmdc_init(&mparam); 138#endif 139 140 gd->ram_size = CFG_SYS_SDRAM_SIZE; 141#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 142 /* This will break-before-make MMU for DDR */ 143 update_early_mmu_table(); 144#endif 145 146 return 0; 147} 148#endif 149 150 151int board_early_init_f(void) 152{ 153 fsl_lsch2_early_init_f(); 154 155 return 0; 156} 157 158int board_init(void) 159{ 160 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 161 CONFIG_SYS_CCI400_OFFSET); 162 /* 163 * Set CCI-400 control override register to enable barrier 164 * transaction 165 */ 166 if (current_el() == 3) 167 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 168 169#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 170 erratum_a010315(); 171#endif 172 173 return 0; 174} 175 176#ifdef CONFIG_FSL_PFE 177void board_quiesce_devices(void) 178{ 179 pfe_command_stop(0, NULL); 180} 181#endif 182 183#ifdef CONFIG_TARGET_LS1012ARDB 184int esdhc_status_fixup(void *blob, const char *compat) 185{ 186 char esdhc1_path[] = "/soc/esdhc@1580000"; 187 bool sdhc2_en = false; 188 u8 mux_sdhc2; 189 u8 io = 0; 190 int ret, bus_num = 0; 191 192#if CONFIG_IS_ENABLED(DM_I2C) 193 struct udevice *dev; 194 195 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR, 196 1, &dev); 197 if (ret) { 198 printf("%s: Cannot find udev for a bus %d\n", __func__, 199 bus_num); 200 return -ENXIO; 201 } 202 ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1); 203#else 204 i2c_set_bus_num(bus_num); 205 /* IO1[7:3] is the field of board revision info. */ 206 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1); 207#endif 208 if (ret < 0) { 209 printf("Error reading i2c boot information!\n"); 210 return 0; 211 } 212 213 /* hwconfig method is used for RevD and later versions. */ 214 if ((io & SW_REV_MASK) <= SW_REV_D) { 215#ifdef CONFIG_HWCONFIG 216 if (hwconfig("esdhc1")) 217 sdhc2_en = true; 218#endif 219 } else { 220 /* 221 * The I2C IO-expander for mux select is used to control 222 * the muxing of various onboard interfaces. 223 * 224 * IO0[3:2] indicates SDHC2 interface demultiplexer 225 * select lines. 226 * 00 - SDIO wifi 227 * 01 - GPIO (to Arduino) 228 * 10 - eMMC Memory 229 * 11 - SPI 230 */ 231#if CONFIG_IS_ENABLED(DM_I2C) 232 ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1); 233#else 234 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1); 235#endif 236 if (ret < 0) { 237 printf("Error reading i2c boot information!\n"); 238 return 0; 239 } 240 241 mux_sdhc2 = (io & 0x0c) >> 2; 242 /* Enable SDHC2 only when use SDIO wifi and eMMC */ 243 if (mux_sdhc2 == 2 || mux_sdhc2 == 0) 244 sdhc2_en = true; 245 } 246 if (sdhc2_en) 247 do_fixup_by_path(blob, esdhc1_path, "status", "okay", 248 sizeof("okay"), 1); 249 else 250 do_fixup_by_path(blob, esdhc1_path, "status", "disabled", 251 sizeof("disabled"), 1); 252 return 0; 253} 254#endif 255 256int ft_board_setup(void *blob, struct bd_info *bd) 257{ 258 arch_fixup_fdt(blob); 259 260 ft_cpu_setup(blob, bd); 261 262 return 0; 263} 264 265static int switch_to_bank1(void) 266{ 267 u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03; 268 int ret, bus_num = 0; 269 270#if CONFIG_IS_ENABLED(DM_I2C) 271 struct udevice *dev; 272 273 ret = i2c_get_chip_for_busnum(bus_num, chip_addr, 274 1, &dev); 275 if (ret) { 276 printf("%s: Cannot find udev for a bus %d\n", __func__, 277 bus_num); 278 return -ENXIO; 279 } 280 /* 281 * -------------------------------------------------------------------- 282 * |bus |I2C address| Device | Notes | 283 * -------------------------------------------------------------------- 284 * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General | 285 * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output| 286 * | | | KW41GPIO) - NXP | (GPIO) expansion for the | 287 * | | | PCAL9555AHF | I2C bus | 288 * ----- -------------------------------------------------------------- 289 * - mount three IO expander(PCAL9555AHF) on I2C1 290 * 291 * PCAL9555A device address 292 * slave address 293 * -------------------------------------- 294 * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W | 295 * -------------------------------------- 296 * | fixed | hardware selectable| 297 * 298 * Output port 1(Pinter register bits = 0x03) 299 * 300 * P1_[7~0] = 0xf4 301 * P1_0 <---> CFG_MUX_QSPI_S0 302 * P1_1 <---> CFG_MUX_QSPI_S1 303 * CFG_MUX_QSPI_S[1:0] = 0b00 304 * 305 * QSPI chip-select demultiplexer select 306 * --------------------------------------------------------------------- 307 * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values 308 * --------------------------------------------------------------------- 309 * 0 | 0 |CS routed to SPI memory bank1(default) 310 * --------------------------------------------------------------------- 311 * 0 | 1 |CS routed to SPI memory bank2 312 * --------------------------------------------------------------------- 313 * 314 */ 315 ret = dm_i2c_write(dev, offset_addr, &data, 1); 316#else /* Non DM I2C support - will be removed */ 317 i2c_set_bus_num(bus_num); 318 ret = i2c_write(chip_addr, offset_addr, 1, &data, 1); 319#endif 320 321 if (ret) { 322 printf("i2c write error to chip : %u, addr : %u, data : %u\n", 323 chip_addr, offset_addr, data); 324 } 325 326 return ret; 327} 328 329static int switch_to_bank2(void) 330{ 331 u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3}; 332 u8 chip_addr = 0x24; 333 int ret, i, bus_num = 0; 334 335#if CONFIG_IS_ENABLED(DM_I2C) 336 struct udevice *dev; 337 338 ret = i2c_get_chip_for_busnum(bus_num, chip_addr, 339 1, &dev); 340 if (ret) { 341 printf("%s: Cannot find udev for a bus %d\n", __func__, 342 bus_num); 343 return -ENXIO; 344 } 345#else /* Non DM I2C support - will be removed */ 346 i2c_set_bus_num(bus_num); 347#endif 348 349 /* 350 * 1th step: config port 1 351 * - the port 1 pin is enabled as an output 352 * 2th step: output port 1 353 * - P1_[7:0] output 0xf5, 354 * then CFG_MUX_QSPI_S[1:0] equal to 0b01, 355 * CS routed to SPI memory bank2 356 */ 357 for (i = 0; i < sizeof(data); i++) { 358#if CONFIG_IS_ENABLED(DM_I2C) 359 ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1); 360#else /* Non DM I2C support - will be removed */ 361 ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1); 362#endif 363 if (ret) { 364 printf("i2c write error to chip : %u, addr : %u, data : %u\n", 365 chip_addr, offset_addr[i], data[i]); 366 goto err; 367 } 368 } 369 370err: 371 return ret; 372} 373 374static int convert_flash_bank(int bank) 375{ 376 int ret = 0; 377 378 switch (bank) { 379 case BOOT_FROM_UPPER_BANK: 380 ret = switch_to_bank2(); 381 break; 382 case BOOT_FROM_LOWER_BANK: 383 ret = switch_to_bank1(); 384 break; 385 default: 386 ret = CMD_RET_USAGE; 387 break; 388 }; 389 390 return ret; 391} 392 393static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc, 394 char *const argv[]) 395{ 396 if (argc != 2) 397 return CMD_RET_USAGE; 398 if (strcmp(argv[1], "1") == 0) 399 convert_flash_bank(BOOT_FROM_LOWER_BANK); 400 else if (strcmp(argv[1], "2") == 0) 401 convert_flash_bank(BOOT_FROM_UPPER_BANK); 402 else 403 return CMD_RET_USAGE; 404 405 return 0; 406} 407 408U_BOOT_CMD( 409 boot_bank, 2, 0, flash_bank_cmd, 410 "Flash bank Selection Control", 411 "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)" 412); 413