1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some init for sunxi platform. 10 */ 11 12#include <cpu_func.h> 13#include <init.h> 14#include <log.h> 15#include <mmc.h> 16#include <i2c.h> 17#include <serial.h> 18#include <spl.h> 19#include <sunxi_gpio.h> 20#include <asm/cache.h> 21#include <asm/gpio.h> 22#include <asm/io.h> 23#include <asm/arch/clock.h> 24#include <asm/arch/spl.h> 25#include <asm/arch/sys_proto.h> 26#include <asm/arch/timer.h> 27#include <asm/arch/tzpc.h> 28#include <asm/arch/mmc.h> 29 30#include <linux/compiler.h> 31 32struct fel_stash { 33 uint32_t sp; 34 uint32_t lr; 35 uint32_t cpsr; 36 uint32_t sctlr; 37 uint32_t vbar; 38}; 39 40struct fel_stash fel_stash __section(".data"); 41 42#ifdef CONFIG_ARM64 43#include <asm/armv8/mmu.h> 44 45static struct mm_region sunxi_mem_map[] = { 46 { 47 /* SRAM, MMIO regions */ 48 .virt = 0x0UL, 49 .phys = 0x0UL, 50 .size = 0x40000000UL, 51 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 52 PTE_BLOCK_NON_SHARE 53 }, { 54 /* RAM */ 55 .virt = 0x40000000UL, 56 .phys = 0x40000000UL, 57 .size = CONFIG_SUNXI_DRAM_MAX_SIZE, 58 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 59 PTE_BLOCK_INNER_SHARE 60 }, { 61 /* List terminator */ 62 0, 63 } 64}; 65struct mm_region *mem_map = sunxi_mem_map; 66 67phys_addr_t board_get_usable_ram_top(phys_size_t total_size) 68{ 69 /* Some devices (like the EMAC) have a 32-bit DMA limit. */ 70 if (gd->ram_top > (1ULL << 32)) 71 return 1ULL << 32; 72 73 return gd->ram_top; 74} 75#endif /* CONFIG_ARM64 */ 76 77#ifdef CONFIG_SPL_BUILD 78static int gpio_init(void) 79{ 80 __maybe_unused uint val; 81#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) 82#if defined(CONFIG_MACH_SUN4I) || \ 83 defined(CONFIG_MACH_SUN7I) || \ 84 defined(CONFIG_MACH_SUN8I_R40) 85 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ 86 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); 87 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); 88#endif 89#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || \ 90 defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I_R40) || \ 91 defined(CONFIG_MACH_SUN9I) 92 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); 93 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); 94#else 95 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); 96 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); 97#endif 98 sunxi_gpio_set_pull(SUNXI_GPF(4), SUNXI_GPIO_PULL_UP); 99#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV) 100 sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0); 101 sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0); 102 sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP); 103#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \ 104 defined(CONFIG_MACH_SUN7I) || \ 105 defined(CONFIG_MACH_SUN8I_R40)) 106 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); 107 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); 108 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); 109#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) 110 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); 111 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); 112 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); 113#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) 114 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); 115 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); 116 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); 117#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) 118 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); 119 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); 120 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); 121#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5) 122 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); 123 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); 124 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); 125#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I) 126 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); 127 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); 128 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); 129#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6) 130 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0); 131 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0); 132 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); 133#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616) 134 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0); 135 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0); 136 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); 137#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) 138 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); 139 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); 140 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); 141#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S) 142 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); 143 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); 144 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); 145#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) 146 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); 147 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); 148 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); 149#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528) 150 sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6); 151 sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6); 152 sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP); 153#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV) 154 sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); 155 sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); 156 sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); 157#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) 158 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); 159 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); 160 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); 161#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3) 162 sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2); 163 sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2); 164 sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP); 165#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) 166 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); 167 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); 168 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); 169#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528) 170 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7); 171 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7); 172 sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP); 173#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) 174 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); 175 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); 176 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); 177#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \ 178 !defined(CONFIG_MACH_SUN8I_R40) 179 sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1); 180 sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1); 181 sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP); 182#else 183#error Unsupported console port number. Please fix pin mux settings in board.c 184#endif 185 186 /* 187 * Update PIO power bias configuration by copying the hardware 188 * detected value. 189 */ 190 if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || 191 IS_ENABLED(CONFIG_SUN50I_GEN_NCAT2)) { 192 val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); 193 writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); 194 } 195 if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) { 196 val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); 197 writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); 198 } 199 200 return 0; 201} 202 203static int spl_board_load_image(struct spl_image_info *spl_image, 204 struct spl_boot_device *bootdev) 205{ 206 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); 207 return_to_fel(fel_stash.sp, fel_stash.lr); 208 209 return 0; 210} 211SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image); 212#endif /* CONFIG_SPL_BUILD */ 213 214#define SUNXI_INVALID_BOOT_SOURCE -1 215 216static int suniv_get_boot_source(void) 217{ 218 /* Get the last function call from BootROM's stack. */ 219 u32 brom_call = *(u32 *)(uintptr_t)(fel_stash.sp - 4); 220 221 /* translate SUNIV BootROM stack to standard SUNXI boot sources */ 222 switch (brom_call) { 223 case SUNIV_BOOTED_FROM_MMC0: 224 return SUNXI_BOOTED_FROM_MMC0; 225 case SUNIV_BOOTED_FROM_SPI: 226 return SUNXI_BOOTED_FROM_SPI; 227 case SUNIV_BOOTED_FROM_MMC1: 228 return SUNXI_BOOTED_FROM_MMC2; 229 /* SPI NAND is not supported yet. */ 230 case SUNIV_BOOTED_FROM_NAND: 231 return SUNXI_INVALID_BOOT_SOURCE; 232 } 233 /* If we get here something went wrong try to boot from FEL.*/ 234 printf("Unknown boot source from BROM: 0x%x\n", brom_call); 235 return SUNXI_INVALID_BOOT_SOURCE; 236} 237 238static int sunxi_egon_valid(struct boot_file_head *egon_head) 239{ 240 return !memcmp(egon_head->magic, BOOT0_MAGIC, 8); /* eGON.BT0 */ 241} 242 243static int sunxi_toc0_valid(struct toc0_main_info *toc0_info) 244{ 245 return !memcmp(toc0_info->name, TOC0_MAIN_INFO_NAME, 8); /* TOC0.GLH */ 246} 247 248static int sunxi_get_boot_source(void) 249{ 250 struct boot_file_head *egon_head = (void *)SPL_ADDR; 251 struct toc0_main_info *toc0_info = (void *)SPL_ADDR; 252 253 /* 254 * On the ARMv5 SoCs, the SPL header in SRAM is overwritten by the 255 * exception vectors in U-Boot proper, so we won't find any 256 * information there. Also the FEL stash is only valid in the SPL, 257 * so we can't use that either. So if this is called from U-Boot 258 * proper, just return MMC0 as a placeholder, for now. 259 */ 260 if (IS_ENABLED(CONFIG_MACH_SUNIV) && 261 !IS_ENABLED(CONFIG_SPL_BUILD)) 262 return SUNXI_BOOTED_FROM_MMC0; 263 264 if (IS_ENABLED(CONFIG_MACH_SUNIV)) 265 return suniv_get_boot_source(); 266 if (sunxi_egon_valid(egon_head)) 267 return readb(&egon_head->boot_media); 268 if (sunxi_toc0_valid(toc0_info)) 269 return readb(&toc0_info->platform[0]); 270 271 /* Not a valid image, so we must have been booted via FEL. */ 272 return SUNXI_INVALID_BOOT_SOURCE; 273} 274 275/* The sunxi internal brom will try to loader external bootloader 276 * from mmc0, nand flash, mmc2. 277 */ 278uint32_t sunxi_get_boot_device(void) 279{ 280 int boot_source = sunxi_get_boot_source(); 281 282 /* 283 * When booting from the SD card or NAND memory, the "eGON.BT0" 284 * signature is expected to be found in memory at the address 0x0004 285 * (see the "mksunxiboot" tool, which generates this header). 286 * 287 * When booting in the FEL mode over USB, this signature is patched in 288 * memory and replaced with something else by the 'fel' tool. This other 289 * signature is selected in such a way, that it can't be present in a 290 * valid bootable SD card image (because the BROM would refuse to 291 * execute the SPL in this case). 292 * 293 * This checks for the signature and if it is not found returns to 294 * the FEL code in the BROM to wait and receive the main u-boot 295 * binary over USB. If it is found, it determines where SPL was 296 * read from. 297 */ 298 switch (boot_source) { 299 case SUNXI_INVALID_BOOT_SOURCE: 300 return BOOT_DEVICE_BOARD; 301 case SUNXI_BOOTED_FROM_MMC0: 302 case SUNXI_BOOTED_FROM_MMC0_HIGH: 303 return BOOT_DEVICE_MMC1; 304 case SUNXI_BOOTED_FROM_NAND: 305 return BOOT_DEVICE_NAND; 306 case SUNXI_BOOTED_FROM_MMC2: 307 case SUNXI_BOOTED_FROM_MMC2_HIGH: 308 return BOOT_DEVICE_MMC2; 309 case SUNXI_BOOTED_FROM_SPI: 310 return BOOT_DEVICE_SPI; 311 } 312 313 panic("Unknown boot source %d\n", boot_source); 314 return -1; /* Never reached */ 315} 316 317#ifdef CONFIG_SPL_BUILD 318uint32_t sunxi_get_spl_size(void) 319{ 320 struct boot_file_head *egon_head = (void *)SPL_ADDR; 321 struct toc0_main_info *toc0_info = (void *)SPL_ADDR; 322 323 if (sunxi_egon_valid(egon_head)) 324 return readl(&egon_head->length); 325 if (sunxi_toc0_valid(toc0_info)) 326 return readl(&toc0_info->length); 327 328 /* Not a valid image, so use the default U-Boot offset. */ 329 return 0; 330} 331 332/* 333 * The eGON SPL image can be located at 8KB or at 128KB into an SD card or 334 * an eMMC device. The boot source has bit 4 set in the latter case. 335 * By adding 120KB to the normal offset when booting from a "high" location 336 * we can support both cases. 337 * Also U-Boot proper is located at least 32KB after the SPL, but will 338 * immediately follow the SPL if that is bigger than that. 339 */ 340unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, 341 unsigned long raw_sect) 342{ 343 unsigned long spl_size = sunxi_get_spl_size(); 344 unsigned long sector; 345 346 sector = max(raw_sect, spl_size / 512); 347 348 switch (sunxi_get_boot_source()) { 349 case SUNXI_BOOTED_FROM_MMC0_HIGH: 350 case SUNXI_BOOTED_FROM_MMC2_HIGH: 351 sector += (128 - 8) * 2; 352 break; 353 } 354 355 return sector; 356} 357 358u32 spl_boot_device(void) 359{ 360 return sunxi_get_boot_device(); 361} 362 363__weak void sunxi_sram_init(void) 364{ 365} 366 367/* 368 * When booting from an eMMC boot partition, the SPL puts the same boot 369 * source code into SRAM A1 as when loading the SPL from the normal 370 * eMMC user data partition: 0x2. So to know where we have been loaded 371 * from, we repeat the BROM algorithm here: checking for a valid eGON boot 372 * image at offset 0 of a (potentially) selected boot partition. 373 * If any of the conditions is not met, it must have been the eMMC user 374 * data partition. 375 */ 376static bool sunxi_valid_emmc_boot(struct mmc *mmc) 377{ 378 struct blk_desc *bd = mmc_get_blk_desc(mmc); 379 u32 *buffer = (void *)(uintptr_t)CONFIG_TEXT_BASE; 380 struct boot_file_head *egon_head = (void *)buffer; 381 struct toc0_main_info *toc0_info = (void *)buffer; 382 int bootpart = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); 383 uint32_t spl_size, emmc_checksum, chksum = 0; 384 ulong count; 385 386 /* The BROM requires BOOT_ACK to be enabled. */ 387 if (!EXT_CSD_EXTRACT_BOOT_ACK(mmc->part_config)) 388 return false; 389 390 /* 391 * The BOOT_BUS_CONDITION register must be 4-bit SDR, with (0x09) 392 * or without (0x01) high speed timings. 393 */ 394 if ((mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x01 && 395 (mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x09) 396 return false; 397 398 /* Partition 0 is the user data partition, bootpart must be 1 or 2. */ 399 if (bootpart != 1 && bootpart != 2) 400 return false; 401 402 /* Failure to switch to the boot partition is fatal. */ 403 if (mmc_switch_part(mmc, bootpart)) 404 return false; 405 406 /* Read the first block to do some sanity checks on the eGON header. */ 407 count = blk_dread(bd, 0, 1, buffer); 408 if (count != 1) 409 return false; 410 411 if (sunxi_egon_valid(egon_head)) 412 spl_size = egon_head->length; 413 else if (sunxi_toc0_valid(toc0_info)) 414 spl_size = toc0_info->length; 415 else 416 return false; 417 418 /* Read the rest of the SPL now we know it's halfway sane. */ 419 count = blk_dread(bd, 1, DIV_ROUND_UP(spl_size, bd->blksz) - 1, 420 buffer + bd->blksz / 4); 421 422 /* Save the checksum and replace it with the "stamp value". */ 423 emmc_checksum = buffer[3]; 424 buffer[3] = 0x5f0a6c39; 425 426 /* The checksum is a simple ignore-carry addition of all words. */ 427 for (count = 0; count < spl_size / 4; count++) 428 chksum += buffer[count]; 429 430 debug("eMMC boot part SPL checksum: stored: 0x%08x, computed: 0x%08x\n", 431 emmc_checksum, chksum); 432 433 return emmc_checksum == chksum; 434} 435 436u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) 437{ 438 static u32 result = ~0; 439 440 if (result != ~0) 441 return result; 442 443 result = MMCSD_MODE_RAW; 444 if (!IS_SD(mmc) && IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) { 445 if (sunxi_valid_emmc_boot(mmc)) 446 result = MMCSD_MODE_EMMCBOOT; 447 else 448 mmc_switch_part(mmc, 0); 449 } 450 451 debug("%s(): %s part\n", __func__, 452 result == MMCSD_MODE_RAW ? "user" : "boot"); 453 454 return result; 455} 456 457void board_init_f(ulong dummy) 458{ 459 sunxi_sram_init(); 460 461 /* Enable non-secure access to some peripherals */ 462 tzpc_init(); 463 464 clock_init(); 465 timer_init(); 466 gpio_init(); 467 468 spl_init(); 469 preloader_console_init(); 470 471#if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY) 472 /* Needed early by sunxi_board_init if PMU is enabled */ 473 i2c_init_board(); 474 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 475#endif 476 sunxi_board_init(); 477} 478#endif /* CONFIG_SPL_BUILD */ 479 480#if !CONFIG_IS_ENABLED(SYSRESET) 481void reset_cpu(void) 482{ 483#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40) 484 static const struct sunxi_wdog *wdog = 485 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; 486 487 /* Set the watchdog for its shortest interval (.5s) and wait */ 488 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); 489 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); 490 491 while (1) { 492 /* sun5i sometimes gets stuck without this */ 493 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); 494 } 495#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) 496#if defined(CONFIG_MACH_SUN50I_H6) 497 /* WDOG is broken for some H6 rev. use the R_WDOG instead */ 498 static const struct sunxi_wdog *wdog = 499 (struct sunxi_wdog *)SUNXI_R_WDOG_BASE; 500#else 501 static const struct sunxi_wdog *wdog = 502 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; 503#endif 504 /* Set the watchdog for its shortest interval (.5s) and wait */ 505 writel(WDT_CFG_RESET, &wdog->cfg); 506 writel(WDT_MODE_EN, &wdog->mode); 507 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); 508 while (1) { } 509#endif 510} 511#endif /* CONFIG_SYSRESET */ 512 513#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A) 514void enable_caches(void) 515{ 516 /* Enable D-cache. I-cache is already enabled in start.S */ 517 dcache_enable(); 518} 519#endif 520