1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 Rockchip Electronics Co., Ltd
4 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
5 */
6
7#include <common.h>
8#include <asm/arch-rockchip/bootrom.h>
9#include <asm/arch-rockchip/hardware.h>
10#include <asm/arch-rockchip/grf_rv1126.h>
11
12#define FIREWALL_APB_BASE	0xffa60000
13#define FW_DDR_CON_REG		0x80
14#define GRF_BASE		0xFE000000
15
16const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
17	[BROM_BOOTSOURCE_EMMC] = "/mmc@ffc50000",
18	[BROM_BOOTSOURCE_SPINOR] = "/spi@ffc90000/flash@0",
19	[BROM_BOOTSOURCE_SD] = "/mmc@ffc60000",
20};
21
22/* GRF_GPIO3A_IOMUX_L */
23enum {
24	GPIO3A3_SHIFT		= 12,
25	GPIO3A3_MASK		= GENMASK(14, 12),
26	GPIO3A3_GPIO		= 0,
27	GPIO3A3_UART2_RX_M1,
28	GPIO3A3_A7_JTAG_TMS_M1,
29
30	GPIO3A2_SHIFT		= 8,
31	GPIO3A2_MASK		= GENMASK(10, 8),
32	GPIO3A2_GPIO		= 0,
33	GPIO3A2_UART2_TX_M1,
34	GPIO3A2_A7_JTAG_TCK_M1,
35};
36
37/* GRF_IOFUNC_CON2 */
38enum {
39	UART2_IO_SEL_SHIFT	= 8,
40	UART2_IO_SEL_MASK	= GENMASK(8, 8),
41	UART2_IO_SEL_M0		= 0,
42	UART2_IO_SEL_M1,
43};
44
45void board_debug_uart_init(void)
46{
47	static struct rv1126_grf * const grf = (void *)GRF_BASE;
48
49	/* Enable early UART2 channel m1 on the rv1126 */
50	rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK,
51		     UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
52
53	/* Switch iomux */
54	rk_clrsetreg(&grf->gpio3a_iomux_l,
55		     GPIO3A3_MASK | GPIO3A2_MASK,
56		     GPIO3A3_UART2_RX_M1 << GPIO3A3_SHIFT |
57		     GPIO3A2_UART2_TX_M1 << GPIO3A2_SHIFT);
58}
59
60#ifndef CONFIG_TPL_BUILD
61int arch_cpu_init(void)
62{
63	/**
64	 * Set dram area unsecure in spl
65	 *
66	 * usb & mmc & sfc controllers can read data to dram
67	 * since they are unsecure.
68	 * (Note: only secure-world can access this register)
69	 */
70	if (IS_ENABLED(CONFIG_SPL_BUILD))
71		writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG);
72
73	return 0;
74}
75#endif
76