1if ROCKCHIP_PX30 2 3config TARGET_EVB_PX30 4 bool "EVB_PX30" 5 help 6 This target config option used for below listed px30 boards. 7 8 EVB_PX30: 9 * EVB_PX30 is an evaluation board for Rockchip PX30. 10 11config TARGET_ODROID_GO2 12 bool "ODROID_GO2" 13 14config TARGET_PX30_CORE 15 bool "Engicam PX30.Core" 16 help 17 PX30.Core EDIMM2.2: 18 * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. 19 * EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam. 20 * PX30.Core needs to mount on top of EDIMM2.2 for creating complete 21 PX30.Core EDIMM2.2 Starter Kit. 22 23 PX30.Core CTOUCH2: 24 * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. 25 * CTOUCH2.0 is a general purpose Carrier board with capacitive 26 touch interface support. 27 * PX30.Core needs to mount on top of CTOUCH2.0 for creating complete 28 PX30.Core C.TOUCH Carrier board. 29 30 PX30.Core CTOUCH2-OF10: 31 * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. 32 * CTOUCH2.0 is a general purpose Carrier board with capacitive 33 touch interface support. 34 * 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. 35 * PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged 36 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. 37 38config TARGET_RINGNECK_PX30 39 bool "Theobroma Systems PX30-uQ7 (Ringneck)" 40 help 41 The PX30-uQ7 (Ringneck) SoM is a uQseven-compatible (40mmx70mm, 42 MXM-230 connector) system-on-module from Theobroma Systems[1], 43 featuring the Rockchip PX30. 44 45 It provides the following feature set: 46 * up to 4GB DDR4 47 * up to 128GB on-module eMMC (with 8-bit 1.8V interface) 48 * SD card (on a baseboard) via edge connector 49 * Fast Ethernet with on-module TI DP83825I PHY 50 * MIPI-DSI/LVDS 51 * MIPI-CSI 52 * USB 53 - 1x USB 2.0 dual-role 54 - 3x USB 2.0 host 55 * on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing: 56 - low-power RTC functionality (ISL1208 emulation) 57 - fan controller (AMC6821 emulation) 58 - USB<->CAN bridge controller (STM32 only) 59 * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi 60 * on-module NXP SE05x Secure Element 61 62config ROCKCHIP_BOOT_MODE_REG 63 default 0xff010200 64 65config ROCKCHIP_STIMER_BASE 66 default 0xff220020 67 68config SYS_SOC 69 default "px30" 70 71config ROCKCHIP_COMMON_STACK_ADDR 72 default y 73 74config SYS_MALLOC_F_LEN 75 default 0x400 if !SPL_SHARES_INIT_SP_ADDR 76 77config SPL_SERIAL 78 default y 79 80config TPL_LDSCRIPT 81 default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" 82 83config TPL_TEXT_BASE 84 default 0xff0e1000 85 86config TPL_STACK 87 default 0xff0e4fff 88 89config TPL_SYS_MALLOC_F_LEN 90 default 0x600 91 92config DEBUG_UART_CHANNEL 93 int "Mux channel to use for debug UART2/UART3" 94 depends on DEBUG_UART_BOARD_INIT 95 default 0 96 help 97 UART2 and UART3 can use two different set of pins to route the output. 98 For using the UART for early debugging the route to use needs 99 to be declared (0 or 1). 100 101source "board/engicam/px30_core/Kconfig" 102source "board/hardkernel/odroid_go2/Kconfig" 103source "board/rockchip/evb_px30/Kconfig" 104source "board/theobroma-systems/ringneck_px30/Kconfig" 105 106endif 107