1config ARCH_MAP_SYSMEM 2 depends on SANDBOX 3 def_bool y 4 5config CREATE_ARCH_SYMLINK 6 bool 7 8config HAVE_ARCH_IOREMAP 9 bool 10 11config SYS_CACHE_SHIFT_4 12 bool 13 14config SYS_CACHE_SHIFT_5 15 bool 16 17config SYS_CACHE_SHIFT_6 18 bool 19 20config SYS_CACHE_SHIFT_7 21 bool 22 23config 32BIT 24 bool 25 26config 64BIT 27 bool 28 29config SYS_CACHELINE_SIZE 30 int 31 default 128 if SYS_CACHE_SHIFT_7 32 default 64 if SYS_CACHE_SHIFT_6 33 default 32 if SYS_CACHE_SHIFT_5 34 default 16 if SYS_CACHE_SHIFT_4 35 # Fall-back for MIPS 36 default 32 if MIPS 37 38config LINKER_LIST_ALIGN 39 int 40 default 32 if SANDBOX 41 default 8 if ARM64 || X86 42 default 4 43 help 44 Force the each linker list to be aligned to this boundary. This 45 is required if ll_entry_get() is used, since otherwise the linker 46 may add padding into the table, thus breaking it. 47 See linker_lists.rst for full details. 48 49choice 50 prompt "Architecture select" 51 default SANDBOX 52 53config ARC 54 bool "ARC architecture" 55 select ARC_TIMER 56 select CLK 57 select DM 58 select HAVE_PRIVATE_LIBGCC 59 select SUPPORT_OF_CONTROL 60 select SYS_CACHE_SHIFT_7 61 select TIMER 62 select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN 63 select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN 64 65config ARM 66 bool "ARM architecture" 67 select ARCH_SUPPORTS_LTO 68 select CREATE_ARCH_SYMLINK 69 select HAVE_PRIVATE_LIBGCC if !ARM64 70 select SUPPORT_ACPI 71 select SUPPORT_OF_CONTROL 72 73config M68K 74 bool "M68000 architecture" 75 select HAVE_PRIVATE_LIBGCC 76 select USE_PRIVATE_LIBGCC 77 select SYS_BOOT_GET_CMDLINE 78 select SYS_BOOT_GET_KBD 79 select SYS_CACHE_SHIFT_4 80 select SUPPORT_OF_CONTROL 81 82config MICROBLAZE 83 bool "MicroBlaze architecture" 84 select SUPPORT_OF_CONTROL 85 imply CMD_TIMER 86 imply SPL_REGMAP if SPL 87 imply SPL_TIMER if SPL 88 imply TIMER 89 imply XILINX_TIMER 90 91config MIPS 92 bool "MIPS architecture" 93 select HAVE_ARCH_IOREMAP 94 select HAVE_PRIVATE_LIBGCC 95 select SUPPORT_OF_CONTROL 96 select SPL_SEPARATE_BSS if SPL 97 98config NIOS2 99 bool "Nios II architecture" 100 select CPU 101 select DM 102 select DM_EVENT 103 select OF_CONTROL 104 select SUPPORT_OF_CONTROL 105 imply CMD_DM 106 107config PPC 108 bool "PowerPC architecture" 109 select HAVE_PRIVATE_LIBGCC 110 select SUPPORT_OF_CONTROL 111 select SYS_BOOT_GET_CMDLINE 112 select SYS_BOOT_GET_KBD 113 114config RISCV 115 bool "RISC-V architecture" 116 select CREATE_ARCH_SYMLINK 117 select SUPPORT_ACPI 118 select SUPPORT_OF_CONTROL 119 select OF_CONTROL 120 select DM 121 select DM_EVENT 122 imply SPL_SEPARATE_BSS if SPL 123 imply DM_SERIAL 124 imply DM_MMC 125 imply DM_SPI 126 imply DM_SPI_FLASH 127 imply BLK 128 imply CLK 129 imply MTD 130 imply TIMER 131 imply CMD_DM 132 imply SPL_DM 133 imply SPL_OF_CONTROL 134 imply SPL_LIBCOMMON_SUPPORT 135 imply SPL_LIBGENERIC_SUPPORT 136 imply SPL_SERIAL 137 imply SPL_TIMER 138 139config SANDBOX 140 bool "Sandbox" 141 select ARCH_SUPPORTS_LTO 142 select BOARD_LATE_INIT 143 select BZIP2 144 select CMD_POWEROFF if CMDLINE 145 select DM 146 select DM_EVENT 147 select DM_FUZZING_ENGINE 148 select DM_GPIO 149 select DM_I2C 150 select DM_KEYBOARD 151 select DM_MMC 152 select DM_SERIAL 153 select DM_SPI 154 select DM_SPI_FLASH 155 select GZIP_COMPRESSED 156 select IO_TRACE 157 select LZO 158 select MTD 159 select OF_BOARD_SETUP 160 select PCI_ENDPOINT 161 select SPI 162 select SUPPORT_OF_CONTROL 163 select SYSRESET_CMD_POWEROFF if CMD_POWEROFF 164 select SYS_CACHE_SHIFT_4 165 select IRQ 166 select SUPPORT_EXTENSION_SCAN if CMDLINE 167 select SUPPORT_ACPI 168 imply BITREVERSE 169 select BLOBLIST 170 imply LTO 171 imply CMD_DM 172 imply CMD_EXCEPTION 173 imply CMD_GETTIME 174 imply CMD_HASH 175 imply CMD_IO 176 imply CMD_IOTRACE 177 imply CMD_LZMADEC 178 imply CMD_SF 179 imply CMD_SF_TEST 180 imply CRC32_VERIFY 181 imply FAT_WRITE 182 imply FIRMWARE 183 imply FUZZING_ENGINE_SANDBOX 184 imply HASH_VERIFY 185 imply LZMA 186 imply TEE 187 imply AVB_VERIFY 188 imply LIBAVB 189 imply CMD_AVB 190 imply PARTITION_TYPE_GUID 191 imply SCP03 192 imply CMD_SCP03 193 imply UDP_FUNCTION_FASTBOOT 194 imply VIRTIO_MMIO 195 imply VIRTIO_PCI 196 imply VIRTIO_SANDBOX 197 imply VIRTIO_BLK 198 imply VIRTIO_NET 199 imply DM_SOUND 200 imply PCI_SANDBOX_EP 201 imply PCH 202 imply PHYLIB 203 imply DM_MDIO 204 imply DM_MDIO_MUX 205 imply ACPI 206 imply ACPI_PMC 207 imply ACPI_PMC_SANDBOX 208 imply CMD_PMC 209 imply CMD_CLONE 210 imply SILENT_CONSOLE 211 imply BOOTARGS_SUBST 212 imply PHY_FIXED 213 imply DM_DSA 214 imply CMD_EXTENSION 215 imply KEYBOARD 216 imply PHYSMEM 217 imply GENERATE_ACPI_TABLE 218 imply BINMAN 219 imply CMD_MBR 220 imply CMD_MMC 221 imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE 222 imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE 223 imply CMD_SYSBOOT if BOOTSTD_FULL 224 225config SH 226 bool "SuperH architecture" 227 select HAVE_PRIVATE_LIBGCC 228 select SUPPORT_OF_CONTROL 229 230config X86 231 bool "x86 architecture" 232 select SUPPORT_SPL 233 select SUPPORT_TPL 234 select CREATE_ARCH_SYMLINK 235 select DM 236 select HAVE_ARCH_IOMAP 237 select HAVE_PRIVATE_LIBGCC 238 select OF_CONTROL 239 select PCI 240 select SUPPORT_ACPI 241 select SUPPORT_OF_CONTROL 242 select SYS_CACHE_SHIFT_6 243 select TIMER 244 select USE_PRIVATE_LIBGCC 245 select X86_TSC_TIMER 246 select IRQ 247 imply HAS_ROM if X86_RESET_VECTOR 248 imply BLK 249 imply CMD_DM 250 imply CMD_FPGA_LOADMK 251 imply CMD_GETTIME 252 imply CMD_IO 253 imply CMD_IRQ 254 imply CMD_PCI 255 imply CMD_SF 256 imply CMD_SF_TEST 257 imply DM_GPIO 258 imply DM_KEYBOARD 259 imply DM_MMC 260 imply DM_RTC 261 imply SCSI 262 imply DM_SERIAL 263 imply MTD 264 imply DM_SPI 265 imply DM_SPI_FLASH 266 imply DM_USB 267 imply LAST_STAGE_INIT 268 imply VIDEO 269 imply SYSRESET 270 imply SPL_SYSRESET 271 imply SYSRESET_X86 272 imply USB_ETHER_ASIX 273 imply USB_ETHER_SMSC95XX 274 imply USB_HOST_ETHER 275 imply PCH 276 imply PHYSMEM 277 imply RTC_MC146818 278 imply ACPI 279 imply ACPIGEN if !QEMU && !EFI_APP 280 imply SYSINFO if GENERATE_SMBIOS_TABLE 281 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE 282 imply TIMESTAMP 283 284 # Thing to enable for when SPL/TPL are enabled: SPL 285 imply SPL_DM 286 imply SPL_OF_LIBFDT 287 imply SPL_DRIVERS_MISC 288 imply SPL_GPIO 289 imply SPL_PINCTRL 290 imply SPL_LIBCOMMON_SUPPORT 291 imply SPL_LIBGENERIC_SUPPORT 292 imply SPL_SERIAL 293 imply SPL_SPI_FLASH_SUPPORT 294 imply SPL_SPI 295 imply SPL_OF_CONTROL 296 imply SPL_TIMER 297 imply SPL_REGMAP 298 imply SPL_SYSCON 299 # TPL 300 imply TPL_DM 301 imply TPL_DRIVERS_MISC 302 imply TPL_GPIO 303 imply TPL_PINCTRL 304 imply TPL_LIBCOMMON_SUPPORT 305 imply TPL_LIBGENERIC_SUPPORT 306 imply TPL_SERIAL 307 imply TPL_OF_CONTROL 308 imply TPL_TIMER 309 imply TPL_REGMAP 310 imply TPL_SYSCON 311 312config XTENSA 313 bool "Xtensa architecture" 314 select CREATE_ARCH_SYMLINK 315 select SUPPORT_OF_CONTROL 316 317endchoice 318 319config SYS_ARCH 320 string 321 help 322 This option should contain the architecture name to build the 323 appropriate arch/<CONFIG_SYS_ARCH> directory. 324 All the architectures should specify this option correctly. 325 326config SYS_CPU 327 string 328 help 329 This option should contain the CPU name to build the correct 330 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory. 331 332 This is optional. For those targets without the CPU directory, 333 leave this option empty. 334 335config SYS_SOC 336 string 337 help 338 This option should contain the SoC name to build the directory 339 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>. 340 341 This is optional. For those targets without the SoC directory, 342 leave this option empty. 343 344config SYS_VENDOR 345 string 346 help 347 This option should contain the vendor name of the target board. 348 If it is set and 349 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common 350 directory is compiled. 351 If CONFIG_SYS_BOARD is also set, the sources under 352 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled. 353 354 This is optional. For those targets without the vendor directory, 355 leave this option empty. 356 357config SYS_BOARD 358 string 359 help 360 This option should contain the name of the target board. 361 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> 362 or board/<CONFIG_SYS_BOARD> directory is compiled depending on 363 whether CONFIG_SYS_VENDOR is set or not. 364 365 This is optional. For those targets without the board directory, 366 leave this option empty. 367 368config SYS_CONFIG_NAME 369 string "Board header file" if ARCH_MESON || ARCH_VERSAL || \ 370 ARCH_VERSAL_NET || ARCH_ZYNQ || ARCH_ZYNQMP || \ 371 ARCH_ZYNQMP_R5 || MICROBLAZE || NIOS2 372 default "meson64" if ARCH_MESON 373 default "microblaze-generic" if MICROBLAZE 374 default "xilinx_versal" if ARCH_VERSAL 375 default "xilinx_versal_net" if ARCH_VERSAL_NET 376 default "xilinx_zynqmp" if ARCH_ZYNQMP 377 default "xilinx_zynqmp_r5" if ARCH_ZYNQMP_R5 378 default "zynq-common" if ARCH_ZYNQ 379 help 380 This option should contain the base name of board header file. 381 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h 382 should be included from include/config.h. 383 384config SYS_DISABLE_DCACHE_OPS 385 bool 386 help 387 This option disables dcache flush and dcache invalidation 388 operations. For example, on coherent systems where cache 389 operatios are not required, enable this option to avoid them. 390 Note that, its up to the individual architectures to implement 391 this functionality. 392 393config SYS_IMMR 394 hex "Address for the Internal Memory-Mapped Registers (IMMR) window" 395 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A 396 default 0xFF000000 if MPC8xx 397 default 0xF0000000 if ARCH_MPC8313 398 default 0xE0000000 if MPC83xx && !ARCH_MPC8313 399 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 400 default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \ 401 ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \ 402 ARCH_P2020 403 default SYS_CCSRBAR_DEFAULT 404 help 405 Address for the Internal Memory-Mapped Registers (IMMR) window used 406 to configure the features of many Freescale / NXP SoCs. 407 408config MONITOR_IS_IN_RAM 409 bool "U-Boot is loaded in to RAM by a pre-loader" 410 depends on M68K || NIOS2 411 412menu "Skipping low level initialization functions" 413 depends on ARM || MIPS || RISCV 414 415config SKIP_LOWLEVEL_INIT 416 bool "Skip calls to certain low level initialization functions" 417 help 418 If enabled, then certain low level initializations (like setting up 419 the memory controller) are omitted and/or U-Boot does not relocate 420 itself into RAM. 421 Normally this variable MUST NOT be defined. The only exception is 422 when U-Boot is loaded (to RAM) by some other boot loader or by a 423 debugger which performs these initializations itself. 424 425config SPL_SKIP_LOWLEVEL_INIT 426 bool "Skip calls to certain low level initialization functions in SPL" 427 depends on SPL 428 help 429 If enabled, then certain low level initializations (like setting up 430 the memory controller) are omitted and/or U-Boot does not relocate 431 itself into RAM. 432 Normally this variable MUST NOT be defined. The only exception is 433 when U-Boot is loaded (to RAM) by some other boot loader or by a 434 debugger which performs these initializations itself. 435 436config TPL_SKIP_LOWLEVEL_INIT 437 bool "Skip calls to certain low level initialization functions in TPL" 438 depends on SPL && ARM 439 help 440 If enabled, then certain low level initializations (like setting up 441 the memory controller) are omitted and/or U-Boot does not relocate 442 itself into RAM. 443 Normally this variable MUST NOT be defined. The only exception is 444 when U-Boot is loaded (to RAM) by some other boot loader or by a 445 debugger which performs these initializations itself. 446 447config SKIP_LOWLEVEL_INIT_ONLY 448 bool "Skip call to lowlevel_init during early boot ONLY" 449 depends on ARM 450 help 451 This allows just the call to lowlevel_init() to be skipped. The 452 normal CP15 init (such as enabling the instruction cache) is still 453 performed. 454 455config SPL_SKIP_LOWLEVEL_INIT_ONLY 456 bool "Skip call to lowlevel_init during early SPL boot ONLY" 457 depends on SPL && ARM 458 help 459 This allows just the call to lowlevel_init() to be skipped. The 460 normal CP15 init (such as enabling the instruction cache) is still 461 performed. 462 463config TPL_SKIP_LOWLEVEL_INIT_ONLY 464 bool "Skip call to lowlevel_init during early TPL boot ONLY" 465 depends on TPL && ARM 466 help 467 This allows just the call to lowlevel_init() to be skipped. The 468 normal CP15 init (such as enabling the instruction cache) is still 469 performed. 470 471endmenu 472 473config SYS_HAS_NONCACHED_MEMORY 474 bool "Enable reserving a non-cached memory area for drivers" 475 depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH) 476 help 477 This is useful for drivers that would otherwise require a lot of 478 explicit cache maintenance. For some drivers it's also impossible to 479 properly maintain the cache. For example if the regions that need to 480 be flushed are not a multiple of the cache-line size, *and* padding 481 cannot be allocated between the regions to align them (i.e. if the 482 HW requires a contiguous array of regions, and the size of each 483 region is not cache-aligned), then a flush of one region may result 484 in overwriting data that hardware has written to another region in 485 the same cache-line. This can happen for example in network drivers 486 where descriptors for buffers are typically smaller than the CPU 487 cache-line (e.g. 16 bytes vs. 32 or 64 bytes). 488 489config SYS_NONCACHED_MEMORY 490 hex "Size in bytes of the non-cached memory area" 491 depends on SYS_HAS_NONCACHED_MEMORY 492 default 0x100000 493 help 494 Size of non-cached memory area. This area of memory will be typically 495 located right below the malloc() area and mapped uncached in the MMU. 496 497source "arch/arc/Kconfig" 498source "arch/arm/Kconfig" 499source "arch/m68k/Kconfig" 500source "arch/microblaze/Kconfig" 501source "arch/mips/Kconfig" 502source "arch/nios2/Kconfig" 503source "arch/powerpc/Kconfig" 504source "arch/sandbox/Kconfig" 505source "arch/sh/Kconfig" 506source "arch/x86/Kconfig" 507source "arch/xtensa/Kconfig" 508source "arch/riscv/Kconfig" 509 510if ARM || M68K || PPC 511 512source "arch/Kconfig.nxp" 513 514endif 515 516source "board/keymile/Kconfig" 517 518if MIPS || MICROBLAZE 519 520choice 521 prompt "Endianness selection" 522 help 523 Some MIPS boards can be configured for either little or big endian 524 byte order. These modes require different U-Boot images. In general there 525 is one preferred byteorder for a particular system but some systems are 526 just as commonly used in the one or the other endianness. 527 528config SYS_BIG_ENDIAN 529 bool "Big endian" 530 depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE 531 532config SYS_LITTLE_ENDIAN 533 bool "Little endian" 534 depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE 535 536endchoice 537 538endif 539