1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 24 */ 25 26/* 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28 */ 29 30/* IntelVersion: 1.49 v3_3_14_3_BHSW1 */ 31 32#include "igb_api.h" 33 34static void e1000_stop_nvm(struct e1000_hw *hw); 35static void e1000_reload_nvm_generic(struct e1000_hw *hw); 36 37/* 38 * e1000_init_nvm_ops_generic - Initialize NVM function pointers 39 * @hw: pointer to the HW structure 40 * 41 * Setups up the function pointers to no-op functions 42 */ 43void 44e1000_init_nvm_ops_generic(struct e1000_hw *hw) 45{ 46 struct e1000_nvm_info *nvm = &hw->nvm; 47 DEBUGFUNC("e1000_init_nvm_ops_generic"); 48 49 /* Initialize function pointers */ 50 nvm->ops.init_params = e1000_null_ops_generic; 51 nvm->ops.acquire = e1000_null_ops_generic; 52 nvm->ops.read = e1000_null_read_nvm; 53 nvm->ops.release = e1000_null_nvm_generic; 54 nvm->ops.reload = e1000_reload_nvm_generic; 55 nvm->ops.update = e1000_null_ops_generic; 56 nvm->ops.valid_led_default = e1000_null_led_default; 57 nvm->ops.validate = e1000_null_ops_generic; 58 nvm->ops.write = e1000_null_write_nvm; 59} 60 61/* 62 * e1000_null_nvm_read - No-op function, return 0 63 * @hw: pointer to the HW structure 64 */ 65s32 66e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) 67{ 68 DEBUGFUNC("e1000_null_read_nvm"); 69 UNREFERENCED_4PARAMETER(hw, a, b, c); 70 return (E1000_SUCCESS); 71} 72 73/* 74 * e1000_null_nvm_generic - No-op function, return void 75 * @hw: pointer to the HW structure 76 */ 77void 78e1000_null_nvm_generic(struct e1000_hw *hw) 79{ 80 DEBUGFUNC("e1000_null_nvm_generic"); 81 UNREFERENCED_1PARAMETER(hw); 82} 83 84/* 85 * e1000_null_led_default - No-op function, return 0 86 * @hw: pointer to the HW structure 87 */ 88s32 89e1000_null_led_default(struct e1000_hw *hw, u16 *data) 90{ 91 DEBUGFUNC("e1000_null_led_default"); 92 UNREFERENCED_2PARAMETER(hw, data); 93 return (E1000_SUCCESS); 94} 95 96/* 97 * e1000_null_write_nvm - No-op function, return 0 98 * @hw: pointer to the HW structure 99 */ 100s32 101e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) 102{ 103 DEBUGFUNC("e1000_null_write_nvm"); 104 UNREFERENCED_4PARAMETER(hw, a, b, c); 105 return (E1000_SUCCESS); 106} 107 108/* 109 * e1000_raise_eec_clk - Raise EEPROM clock 110 * @hw: pointer to the HW structure 111 * @eecd: pointer to the EEPROM 112 * 113 * Enable/Raise the EEPROM clock bit. 114 */ 115static void 116e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 117{ 118 *eecd = *eecd | E1000_EECD_SK; 119 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 120 E1000_WRITE_FLUSH(hw); 121 usec_delay(hw->nvm.delay_usec); 122} 123 124/* 125 * e1000_lower_eec_clk - Lower EEPROM clock 126 * @hw: pointer to the HW structure 127 * @eecd: pointer to the EEPROM 128 * 129 * Clear/Lower the EEPROM clock bit. 130 */ 131static void 132e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 133{ 134 *eecd = *eecd & ~E1000_EECD_SK; 135 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 136 E1000_WRITE_FLUSH(hw); 137 usec_delay(hw->nvm.delay_usec); 138} 139 140/* 141 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 142 * @hw: pointer to the HW structure 143 * @data: data to send to the EEPROM 144 * @count: number of bits to shift out 145 * 146 * We need to shift 'count' bits out to the EEPROM. So, the value in the 147 * "data" parameter will be shifted out to the EEPROM one bit at a time. 148 * In order to do this, "data" must be broken down into bits. 149 */ 150static void 151e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 152{ 153 struct e1000_nvm_info *nvm = &hw->nvm; 154 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 155 u32 mask; 156 157 DEBUGFUNC("e1000_shift_out_eec_bits"); 158 159 mask = 0x01 << (count - 1); 160 if (nvm->type == e1000_nvm_eeprom_microwire) 161 eecd &= ~E1000_EECD_DO; 162 else if (nvm->type == e1000_nvm_eeprom_spi) 163 eecd |= E1000_EECD_DO; 164 165 do { 166 eecd &= ~E1000_EECD_DI; 167 168 if (data & mask) 169 eecd |= E1000_EECD_DI; 170 171 E1000_WRITE_REG(hw, E1000_EECD, eecd); 172 E1000_WRITE_FLUSH(hw); 173 174 usec_delay(nvm->delay_usec); 175 176 e1000_raise_eec_clk(hw, &eecd); 177 e1000_lower_eec_clk(hw, &eecd); 178 179 mask >>= 1; 180 } while (mask); 181 182 eecd &= ~E1000_EECD_DI; 183 E1000_WRITE_REG(hw, E1000_EECD, eecd); 184} 185 186/* 187 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 188 * @hw: pointer to the HW structure 189 * @count: number of bits to shift in 190 * 191 * In order to read a register from the EEPROM, we need to shift 'count' bits 192 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 193 * the EEPROM (setting the SK bit), and then reading the value of the data out 194 * "DO" bit. During this "shifting in" process the data in "DI" bit should 195 * always be clear. 196 */ 197static u16 198e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 199{ 200 u32 eecd; 201 u32 i; 202 u16 data; 203 204 DEBUGFUNC("e1000_shift_in_eec_bits"); 205 206 eecd = E1000_READ_REG(hw, E1000_EECD); 207 208 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 209 data = 0; 210 211 for (i = 0; i < count; i++) { 212 data <<= 1; 213 e1000_raise_eec_clk(hw, &eecd); 214 215 eecd = E1000_READ_REG(hw, E1000_EECD); 216 217 eecd &= ~E1000_EECD_DI; 218 if (eecd & E1000_EECD_DO) 219 data |= 1; 220 221 e1000_lower_eec_clk(hw, &eecd); 222 } 223 224 return (data); 225} 226 227/* 228 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion 229 * @hw: pointer to the HW structure 230 * @ee_reg: EEPROM flag for polling 231 * 232 * Polls the EEPROM status bit for either read or write completion based 233 * upon the value of 'ee_reg'. 234 */ 235s32 236e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 237{ 238 u32 attempts = 100000; 239 u32 i, reg = 0; 240 s32 ret_val = -E1000_ERR_NVM; 241 242 DEBUGFUNC("e1000_poll_eerd_eewr_done"); 243 244 for (i = 0; i < attempts; i++) { 245 if (ee_reg == E1000_NVM_POLL_READ) 246 reg = E1000_READ_REG(hw, E1000_EERD); 247 else 248 reg = E1000_READ_REG(hw, E1000_EEWR); 249 250 if (reg & E1000_NVM_RW_REG_DONE) { 251 ret_val = E1000_SUCCESS; 252 break; 253 } 254 255 usec_delay(5); 256 } 257 258 return (ret_val); 259} 260 261/* 262 * e1000_acquire_nvm_generic - Generic request for access to EEPROM 263 * @hw: pointer to the HW structure 264 * 265 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 266 * Return successful if access grant bit set, else clear the request for 267 * EEPROM access and return -E1000_ERR_NVM (-1). 268 */ 269s32 270e1000_acquire_nvm_generic(struct e1000_hw *hw) 271{ 272 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 273 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 274 s32 ret_val = E1000_SUCCESS; 275 276 DEBUGFUNC("e1000_acquire_nvm_generic"); 277 278 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); 279 eecd = E1000_READ_REG(hw, E1000_EECD); 280 281 while (timeout) { 282 if (eecd & E1000_EECD_GNT) 283 break; 284 usec_delay(5); 285 eecd = E1000_READ_REG(hw, E1000_EECD); 286 timeout--; 287 } 288 289 if (!timeout) { 290 eecd &= ~E1000_EECD_REQ; 291 E1000_WRITE_REG(hw, E1000_EECD, eecd); 292 DEBUGOUT("Could not acquire NVM grant\n"); 293 ret_val = -E1000_ERR_NVM; 294 } 295 296 return (ret_val); 297} 298 299/* 300 * e1000_standby_nvm - Return EEPROM to standby state 301 * @hw: pointer to the HW structure 302 * 303 * Return the EEPROM to a standby state. 304 */ 305static void 306e1000_standby_nvm(struct e1000_hw *hw) 307{ 308 struct e1000_nvm_info *nvm = &hw->nvm; 309 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 310 311 DEBUGFUNC("e1000_standby_nvm"); 312 313 if (nvm->type == e1000_nvm_eeprom_microwire) { 314 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 315 E1000_WRITE_REG(hw, E1000_EECD, eecd); 316 E1000_WRITE_FLUSH(hw); 317 usec_delay(nvm->delay_usec); 318 319 e1000_raise_eec_clk(hw, &eecd); 320 321 /* Select EEPROM */ 322 eecd |= E1000_EECD_CS; 323 E1000_WRITE_REG(hw, E1000_EECD, eecd); 324 E1000_WRITE_FLUSH(hw); 325 usec_delay(nvm->delay_usec); 326 327 e1000_lower_eec_clk(hw, &eecd); 328 } else if (nvm->type == e1000_nvm_eeprom_spi) { 329 /* Toggle CS to flush commands */ 330 eecd |= E1000_EECD_CS; 331 E1000_WRITE_REG(hw, E1000_EECD, eecd); 332 E1000_WRITE_FLUSH(hw); 333 usec_delay(nvm->delay_usec); 334 eecd &= ~E1000_EECD_CS; 335 E1000_WRITE_REG(hw, E1000_EECD, eecd); 336 E1000_WRITE_FLUSH(hw); 337 usec_delay(nvm->delay_usec); 338 } 339} 340 341/* 342 * e1000_stop_nvm - Terminate EEPROM command 343 * @hw: pointer to the HW structure 344 * 345 * Terminates the current command by inverting the EEPROM's chip select pin. 346 */ 347void 348e1000_stop_nvm(struct e1000_hw *hw) 349{ 350 u32 eecd; 351 352 DEBUGFUNC("e1000_stop_nvm"); 353 354 eecd = E1000_READ_REG(hw, E1000_EECD); 355 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 356 /* Pull CS high */ 357 eecd |= E1000_EECD_CS; 358 e1000_lower_eec_clk(hw, &eecd); 359 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { 360 /* CS on Microwire is active-high */ 361 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 362 E1000_WRITE_REG(hw, E1000_EECD, eecd); 363 e1000_raise_eec_clk(hw, &eecd); 364 e1000_lower_eec_clk(hw, &eecd); 365 } 366} 367 368/* 369 * e1000_release_nvm_generic - Release exclusive access to EEPROM 370 * @hw: pointer to the HW structure 371 * 372 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 373 */ 374void 375e1000_release_nvm_generic(struct e1000_hw *hw) 376{ 377 u32 eecd; 378 379 DEBUGFUNC("e1000_release_nvm_generic"); 380 381 e1000_stop_nvm(hw); 382 383 eecd = E1000_READ_REG(hw, E1000_EECD); 384 eecd &= ~E1000_EECD_REQ; 385 E1000_WRITE_REG(hw, E1000_EECD, eecd); 386} 387 388/* 389 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 390 * @hw: pointer to the HW structure 391 * 392 * Setups the EEPROM for reading and writing. 393 */ 394static s32 395e1000_ready_nvm_eeprom(struct e1000_hw *hw) 396{ 397 struct e1000_nvm_info *nvm = &hw->nvm; 398 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 399 s32 ret_val = E1000_SUCCESS; 400 u16 timeout = 0; 401 u8 spi_stat_reg; 402 403 DEBUGFUNC("e1000_ready_nvm_eeprom"); 404 405 if (nvm->type == e1000_nvm_eeprom_microwire) { 406 /* Clear SK and DI */ 407 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 408 E1000_WRITE_REG(hw, E1000_EECD, eecd); 409 /* Set CS */ 410 eecd |= E1000_EECD_CS; 411 E1000_WRITE_REG(hw, E1000_EECD, eecd); 412 } else if (nvm->type == e1000_nvm_eeprom_spi) { 413 /* Clear SK and CS */ 414 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 415 E1000_WRITE_REG(hw, E1000_EECD, eecd); 416 usec_delay(1); 417 timeout = NVM_MAX_RETRY_SPI; 418 419 /* 420 * Read "Status Register" repeatedly until the LSB is cleared. 421 * The EEPROM will signal that the command has been completed 422 * by clearing bit 0 of the internal status register. If it's 423 * not cleared within 'timeout', then error out. 424 */ 425 while (timeout) { 426 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 427 hw->nvm.opcode_bits); 428 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 429 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 430 break; 431 432 usec_delay(5); 433 e1000_standby_nvm(hw); 434 timeout--; 435 } 436 437 if (!timeout) { 438 DEBUGOUT("SPI NVM Status error\n"); 439 ret_val = -E1000_ERR_NVM; 440 goto out; 441 } 442 } 443 444out: 445 return (ret_val); 446} 447 448/* 449 * e1000_read_nvm_microwire - Reads EEPROM's using microwire 450 * @hw: pointer to the HW structure 451 * @offset: offset of word in the EEPROM to read 452 * @words: number of words to read 453 * @data: word read from the EEPROM 454 * 455 * Reads a 16 bit word from the EEPROM. 456 */ 457s32 458e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 459 u16 *data) 460{ 461 struct e1000_nvm_info *nvm = &hw->nvm; 462 u32 i = 0; 463 s32 ret_val; 464 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE; 465 466 DEBUGFUNC("e1000_read_nvm_microwire"); 467 468 /* 469 * A check for invalid values: offset too large, too many words, 470 * and not enough words. 471 */ 472 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 473 (words == 0)) { 474 DEBUGOUT("nvm parameter(s) out of bounds\n"); 475 ret_val = -E1000_ERR_NVM; 476 goto out; 477 } 478 479 ret_val = nvm->ops.acquire(hw); 480 if (ret_val) 481 goto out; 482 483 ret_val = e1000_ready_nvm_eeprom(hw); 484 if (ret_val) 485 goto release; 486 487 for (i = 0; i < words; i++) { 488 /* Send the READ command (opcode + addr) */ 489 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 490 e1000_shift_out_eec_bits(hw, (u16)(offset + i), 491 nvm->address_bits); 492 493 /* 494 * Read the data. For microwire, each word requires the 495 * overhead of setup and tear-down. 496 */ 497 data[i] = e1000_shift_in_eec_bits(hw, 16); 498 e1000_standby_nvm(hw); 499 } 500 501release: 502 nvm->ops.release(hw); 503 504out: 505 return (ret_val); 506} 507 508/* 509 * e1000_read_nvm_eerd - Reads EEPROM using EERD register 510 * @hw: pointer to the HW structure 511 * @offset: offset of word in the EEPROM to read 512 * @words: number of words to read 513 * @data: word read from the EEPROM 514 * 515 * Reads a 16 bit word from the EEPROM using the EERD register. 516 */ 517s32 518e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 519{ 520 struct e1000_nvm_info *nvm = &hw->nvm; 521 u32 i, eerd = 0; 522 s32 ret_val = E1000_SUCCESS; 523 524 DEBUGFUNC("e1000_read_nvm_eerd"); 525 526 /* 527 * A check for invalid values: offset too large, too many words, 528 * too many words for the offset, and not enough words. 529 */ 530 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 531 (words == 0)) { 532 DEBUGOUT("nvm parameter(s) out of bounds\n"); 533 ret_val = -E1000_ERR_NVM; 534 goto out; 535 } 536 537 for (i = 0; i < words; i++) { 538 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + 539 E1000_NVM_RW_REG_START; 540 541 E1000_WRITE_REG(hw, E1000_EERD, eerd); 542 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 543 if (ret_val) 544 break; 545 546 data[i] = (E1000_READ_REG(hw, E1000_EERD) >> 547 E1000_NVM_RW_REG_DATA); 548 } 549 550out: 551 return (ret_val); 552} 553 554/* 555 * e1000_write_nvm_spi - Write to EEPROM using SPI 556 * @hw: pointer to the HW structure 557 * @offset: offset within the EEPROM to be written to 558 * @words: number of words to write 559 * @data: 16 bit word(s) to be written to the EEPROM 560 * 561 * Writes data to EEPROM at offset using SPI interface. 562 * 563 * If e1000_update_nvm_checksum is not called after this function , the 564 * EEPROM will most likely contain an invalid checksum. 565 */ 566s32 567e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 568{ 569 struct e1000_nvm_info *nvm = &hw->nvm; 570 s32 ret_val; 571 u16 widx = 0; 572 573 DEBUGFUNC("e1000_write_nvm_spi"); 574 575 /* 576 * A check for invalid values: offset too large, too many words, 577 * and not enough words. 578 */ 579 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 580 (words == 0)) { 581 DEBUGOUT("nvm parameter(s) out of bounds\n"); 582 ret_val = -E1000_ERR_NVM; 583 goto out; 584 } 585 586 ret_val = nvm->ops.acquire(hw); 587 if (ret_val) 588 goto out; 589 590 while (widx < words) { 591 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 592 593 ret_val = e1000_ready_nvm_eeprom(hw); 594 if (ret_val) 595 goto release; 596 597 e1000_standby_nvm(hw); 598 599 /* Send the WRITE ENABLE command (8 bit opcode) */ 600 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 601 nvm->opcode_bits); 602 603 e1000_standby_nvm(hw); 604 605 /* 606 * Some SPI eeproms use the 8th address bit embedded in the 607 * opcode 608 */ 609 if ((nvm->address_bits == 8) && (offset >= 128)) 610 write_opcode |= NVM_A8_OPCODE_SPI; 611 612 /* Send the Write command (8-bit opcode + addr) */ 613 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 614 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 615 nvm->address_bits); 616 617 /* Loop to allow for up to whole page write of eeprom */ 618 while (widx < words) { 619 u16 word_out = data[widx]; 620 word_out = (word_out >> 8) | (word_out << 8); 621 e1000_shift_out_eec_bits(hw, word_out, 16); 622 widx++; 623 624 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 625 e1000_standby_nvm(hw); 626 break; 627 } 628 } 629 } 630 631 msec_delay(10); 632release: 633 nvm->ops.release(hw); 634 635out: 636 return (ret_val); 637} 638 639/* 640 * e1000_write_nvm_microwire - Writes EEPROM using microwire 641 * @hw: pointer to the HW structure 642 * @offset: offset within the EEPROM to be written to 643 * @words: number of words to write 644 * @data: 16 bit word(s) to be written to the EEPROM 645 * 646 * Writes data to EEPROM at offset using microwire interface. 647 * 648 * If e1000_update_nvm_checksum is not called after this function , the 649 * EEPROM will most likely contain an invalid checksum. 650 */ 651s32 652e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 653 u16 *data) 654{ 655 struct e1000_nvm_info *nvm = &hw->nvm; 656 s32 ret_val; 657 u32 eecd; 658 u16 words_written = 0; 659 u16 widx = 0; 660 661 DEBUGFUNC("e1000_write_nvm_microwire"); 662 663 /* 664 * A check for invalid values: offset too large, too many words, 665 * and not enough words. 666 */ 667 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 668 (words == 0)) { 669 DEBUGOUT("nvm parameter(s) out of bounds\n"); 670 ret_val = -E1000_ERR_NVM; 671 goto out; 672 } 673 674 ret_val = nvm->ops.acquire(hw); 675 if (ret_val) 676 goto out; 677 678 ret_val = e1000_ready_nvm_eeprom(hw); 679 if (ret_val) 680 goto release; 681 682 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE, 683 (u16)(nvm->opcode_bits + 2)); 684 685 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 686 687 e1000_standby_nvm(hw); 688 689 while (words_written < words) { 690 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE, 691 nvm->opcode_bits); 692 693 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written), 694 nvm->address_bits); 695 696 e1000_shift_out_eec_bits(hw, data[words_written], 16); 697 698 e1000_standby_nvm(hw); 699 700 for (widx = 0; widx < 200; widx++) { 701 eecd = E1000_READ_REG(hw, E1000_EECD); 702 if (eecd & E1000_EECD_DO) 703 break; 704 usec_delay(50); 705 } 706 707 if (widx == 200) { 708 DEBUGOUT("NVM Write did not complete\n"); 709 ret_val = -E1000_ERR_NVM; 710 goto release; 711 } 712 713 e1000_standby_nvm(hw); 714 715 words_written++; 716 } 717 718 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE, 719 (u16)(nvm->opcode_bits + 2)); 720 721 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 722 723release: 724 nvm->ops.release(hw); 725 726out: 727 return (ret_val); 728} 729 730/* 731 * e1000_read_pba_num_generic - Read device part number 732 * @hw: pointer to the HW structure 733 * @pba_num: pointer to device part number 734 * 735 * Reads the product board assembly (PBA) number from the EEPROM and stores 736 * the value in pba_num. 737 */ 738s32 739e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num) 740{ 741 s32 ret_val; 742 u16 nvm_data; 743 744 DEBUGFUNC("e1000_read_pba_num_generic"); 745 746 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 747 if (ret_val) { 748 DEBUGOUT("NVM Read Error\n"); 749 goto out; 750 } 751 *pba_num = (u32)(nvm_data << 16); 752 753 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); 754 if (ret_val) { 755 DEBUGOUT("NVM Read Error\n"); 756 goto out; 757 } 758 *pba_num |= nvm_data; 759 760out: 761 return (ret_val); 762} 763 764/* 765 * e1000_read_mac_addr_generic - Read device MAC address 766 * @hw: pointer to the HW structure 767 * 768 * Reads the device MAC address from the EEPROM and stores the value. 769 * Since devices with two ports use the same EEPROM, we increment the 770 * last bit in the MAC address for the second port. 771 */ 772s32 773e1000_read_mac_addr_generic(struct e1000_hw *hw) 774{ 775 u32 rar_high; 776 u32 rar_low; 777 u16 i; 778 779 rar_high = E1000_READ_REG(hw, E1000_RAH(0)); 780 rar_low = E1000_READ_REG(hw, E1000_RAL(0)); 781 782 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 783 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); 784 785 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 786 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); 787 788 for (i = 0; i < ETH_ADDR_LEN; i++) 789 hw->mac.addr[i] = hw->mac.perm_addr[i]; 790 791 return (E1000_SUCCESS); 792} 793 794/* 795 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum 796 * @hw: pointer to the HW structure 797 * 798 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 799 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 800 */ 801s32 802e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) 803{ 804 s32 ret_val = E1000_SUCCESS; 805 u16 checksum = 0; 806 u16 i, nvm_data; 807 808 DEBUGFUNC("e1000_validate_nvm_checksum_generic"); 809 810 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 811 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 812 if (ret_val) { 813 DEBUGOUT("NVM Read Error\n"); 814 goto out; 815 } 816 checksum += nvm_data; 817 } 818 819 if (checksum != (u16) NVM_SUM) { 820 DEBUGOUT("NVM Checksum Invalid\n"); 821 ret_val = -E1000_ERR_NVM; 822 goto out; 823 } 824 825out: 826 return (ret_val); 827} 828 829/* 830 * e1000_update_nvm_checksum_generic - Update EEPROM checksum 831 * @hw: pointer to the HW structure 832 * 833 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 834 * up to the checksum. Then calculates the EEPROM checksum and writes the 835 * value to the EEPROM. 836 */ 837s32 838e1000_update_nvm_checksum_generic(struct e1000_hw *hw) 839{ 840 s32 ret_val; 841 u16 checksum = 0; 842 u16 i, nvm_data; 843 844 DEBUGFUNC("e1000_update_nvm_checksum"); 845 846 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 847 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 848 if (ret_val) { 849 DEBUGOUT("NVM Read Error while updating checksum.\n"); 850 goto out; 851 } 852 checksum += nvm_data; 853 } 854 checksum = (u16) NVM_SUM - checksum; 855 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 856 if (ret_val) 857 DEBUGOUT("NVM Write Error while updating checksum.\n"); 858 859out: 860 return (ret_val); 861} 862 863/* 864 * e1000_reload_nvm_generic - Reloads EEPROM 865 * @hw: pointer to the HW structure 866 * 867 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 868 * extended control register. 869 */ 870void 871e1000_reload_nvm_generic(struct e1000_hw *hw) 872{ 873 u32 ctrl_ext; 874 875 DEBUGFUNC("e1000_reload_nvm_generic"); 876 877 usec_delay(10); 878 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 879 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 880 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 881 E1000_WRITE_FLUSH(hw); 882} 883