1/* 2 * BCM53XXX ARM/Cortext A9 boot code for standalone apps. 3 * 4 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id$ 19 */ 20 21#include <arminc.h> 22#include <sbhndarm.h> 23#include <hndrte_armtrap.h> 24#include <hndsoc.h> 25#include <sbchipc.h> 26#include <bcmdevs.h> 27#include <ddr_core.h> 28#include <pcieg2_core.h> 29#include <armca9_core.h> 30 31#ifdef _CFE_ 32 33#include <armmacros.h> 34#include "initdata.h" 35#include "bsp_config.h" 36#include "cfe_devfuncs.h" 37 38#define c_main cfe_main 39 40/* 41 * This is the size of the stack, rounded to KByte boundaries. 42 */ 43 44#ifndef CFG_STACK_SIZE 45#error "CFG_STACK_SIZE not defined" 46#else 47#define STACK_SIZE ((CFG_STACK_SIZE+1023) & ~1023) 48#endif 49 50#define envram_ofs 0x1000 51 52#else /* !_CFE_ */ 53 54#if defined(__thumb__) 55#define FUNC(x) THUMBLEAF(x) 56#else 57#define FUNC(x) LEAF(x) 58#endif 59 60/* Debug macro */ 61#ifdef TRACE 62#undef TRACE 63#endif 64#ifdef BCMDBG 65#define TRACE(x) \ 66 ldr r9,=(x); \ 67 ldr r10,=SI_ENUM_BASE; \ 68 str r9,[r10,#0x64] 69#else 70#define TRACE(x) 71#endif 72 73#define envram_ofs 0x400 74 75#if CFG_BIENDIAN 76#define CFE_EPTSEAL_REV 0x31454643 77#endif 78#define CFE_EPTSEAL 0x43464531 79#define cfe_command_restart 0 80 81#endif /* _CFE_ */ 82 83#ifdef CFG_SHMOO 84/* MMU table */ 85 .section section_mmu_table 86page_table: 87 .word 0x00004c06 88 .word 0x00104c06 89 .word 0x00204c06 90 .word 0x00304c06 91 .word 0x00404c06 92 .word 0x00504c06 93 .word 0x00604c06 94 .word 0x00704c06 95 .word 0x00804c06 96 .word 0x00904c06 97 .word 0x00a04c06 98 .word 0x00b04c06 99 .word 0x00c04c06 100 .word 0x00d04c06 101 .word 0x00e04c06 102 .word 0x00f04c06 103 .word 0x01004c06 @DDR_SHMOO_RELATED_CHANGE: make 16MB-32MB area as L1 cacheable write-back mode requested by shmoo memory test 104 .word 0x01104c06 105 .word 0x01204c06 106 .word 0x01304c06 107 .word 0x01404c06 108 .word 0x01504c06 109 .word 0x01604c06 110 .word 0x01704c06 111 .word 0x01804c06 112 .word 0x01904c06 113 .word 0x01a04c06 114 .word 0x01b04c06 115 .word 0x01c04c06 116 .word 0x01d04c06 117 .word 0x01e04c06 118 .word 0x01f04c06 119 .word 0x02004c06 @DDR_SHMOO_RELATED_CHANGE: make 32MB-128MB area as L1&L2 cacheable write-back mode requested by stress memory test 120 .word 0x02104c06 121 .word 0x02204c06 122 .word 0x02304c06 123 .word 0x02404c06 124 .word 0x02504c06 125 .word 0x02604c06 126 .word 0x02704c06 127 .word 0x02804c06 128 .word 0x02904c06 129 .word 0x02a04c06 130 .word 0x02b04c06 131 .word 0x02c04c06 132 .word 0x02d04c06 133 .word 0x02e04c06 134 .word 0x02f04c06 135 .word 0x03004c06 136 .word 0x03104c06 137 .word 0x03204c06 138 .word 0x03304c06 139 .word 0x03404c06 140 .word 0x03504c06 141 .word 0x03604c06 142 .word 0x03704c06 143 .word 0x03804c06 144 .word 0x03904c06 145 .word 0x03a04c06 146 .word 0x03b04c06 147 .word 0x03c04c06 148 .word 0x03d04c06 149 .word 0x03e04c06 150 .word 0x03f04c06 151 .word 0x04004c06 152 .word 0x04104c06 153 .word 0x04204c06 154 .word 0x04304c06 155 .word 0x04404c06 156 .word 0x04504c06 157 .word 0x04604c06 158 .word 0x04704c06 159 .word 0x04804c06 160 .word 0x04904c06 161 .word 0x04a04c06 162 .word 0x04b04c06 163 .word 0x04c04c06 164 .word 0x04d04c06 165 .word 0x04e04c06 166 .word 0x04f04c06 167 .word 0x05004c06 168 .word 0x05104c06 169 .word 0x05204c06 170 .word 0x05304c06 171 .word 0x05404c06 172 .word 0x05504c06 173 .word 0x05604c06 174 .word 0x05704c06 175 .word 0x05804c06 176 .word 0x05904c06 177 .word 0x05a04c06 178 .word 0x05b04c06 179 .word 0x05c04c06 180 .word 0x05d04c06 181 .word 0x05e04c06 182 .word 0x05f04c06 183 .word 0x06004c06 184 .word 0x06104c06 185 .word 0x06204c06 186 .word 0x06304c06 187 .word 0x06404c06 188 .word 0x06504c06 189 .word 0x06604c06 190 .word 0x06704c06 191 .word 0x06804c06 192 .word 0x06904c06 193 .word 0x06a04c06 194 .word 0x06b04c06 195 .word 0x06c04c06 196 .word 0x06d04c06 197 .word 0x06e04c06 198 .word 0x06f04c06 199 .word 0x07004c06 200 .word 0x07104c06 201 .word 0x07204c06 202 .word 0x07304c06 203 .word 0x07404c06 204 .word 0x07504c06 205 .word 0x07604c06 206 .word 0x07704c06 207 .word 0x07804c06 208 .word 0x07904c06 209 .word 0x07a04c06 210 .word 0x07b04c06 211 .word 0x07c04c06 212 .word 0x07d04c06 213 .word 0x07e04c06 214 .word 0x07f04c06 @ DDR_SHMOO_RELATED_CHANGE: end of L1&L2 cacheable write-back mode 215 .word 0x08002c02 216 .word 0x08102c02 217 .word 0x08202c02 218 .word 0x08302c02 219 .word 0x08402c02 220 .word 0x08502c02 221 .word 0x08602c02 222 .word 0x08702c02 223 .word 0x08802c02 224 .word 0x08902c02 225 .word 0x08a02c02 226 .word 0x08b02c02 227 .word 0x08c02c02 228 .word 0x08d02c02 229 .word 0x08e02c02 230 .word 0x08f02c02 231 .word 0x09002c02 232 .word 0x09102c02 233 .word 0x09202c02 234 .word 0x09302c02 235 .word 0x09402c02 236 .word 0x09502c02 237 .word 0x09602c02 238 .word 0x09702c02 239 .word 0x09802c02 240 .word 0x09902c02 241 .word 0x09a02c02 242 .word 0x09b02c02 243 .word 0x09c02c02 244 .word 0x09d02c02 245 .word 0x09e02c02 246 .word 0x09f02c02 247 .word 0x0a002c02 248 .word 0x0a102c02 249 .word 0x0a202c02 250 .word 0x0a302c02 251 .word 0x0a402c02 252 .word 0x0a502c02 253 .word 0x0a602c02 254 .word 0x0a702c02 255 .word 0x0a802c02 256 .word 0x0a902c02 257 .word 0x0aa02c02 258 .word 0x0ab02c02 259 .word 0x0ac02c02 260 .word 0x0ad02c02 261 .word 0x0ae02c02 262 .word 0x0af02c02 263 .word 0x0b002c02 264 .word 0x0b102c02 265 .word 0x0b202c02 266 .word 0x0b302c02 267 .word 0x0b402c02 268 .word 0x0b502c02 269 .word 0x0b602c02 270 .word 0x0b702c02 271 .word 0x0b802c02 272 .word 0x0b902c02 273 .word 0x0ba02c02 274 .word 0x0bb02c02 275 .word 0x0bc02c02 276 .word 0x0bd02c02 277 .word 0x0be02c02 278 .word 0x0bf02c02 279 .word 0x0c002c02 280 .word 0x0c102c02 281 .word 0x0c202c02 282 .word 0x0c302c02 283 .word 0x0c402c02 284 .word 0x0c502c02 285 .word 0x0c602c02 286 .word 0x0c702c02 287 .word 0x0c802c02 288 .word 0x0c902c02 289 .word 0x0ca02c02 290 .word 0x0cb02c02 291 .word 0x0cc02c02 292 .word 0x0cd02c02 293 .word 0x0ce02c02 294 .word 0x0cf02c02 295 .word 0x0d002c02 296 .word 0x0d102c02 297 .word 0x0d202c02 298 .word 0x0d302c02 299 .word 0x0d402c02 300 .word 0x0d502c02 301 .word 0x0d602c02 302 .word 0x0d702c02 303 .word 0x0d802c02 304 .word 0x0d902c02 305 .word 0x0da02c02 306 .word 0x0db02c02 307 .word 0x0dc02c02 308 .word 0x0dd02c02 309 .word 0x0de02c02 310 .word 0x0df02c02 311 .word 0x0e002c02 312 .word 0x0e102c02 313 .word 0x0e202c02 314 .word 0x0e302c02 315 .word 0x0e402c02 316 .word 0x0e502c02 317 .word 0x0e602c02 318 .word 0x0e702c02 319 .word 0x0e802c02 320 .word 0x0e902c02 321 .word 0x0ea02c02 322 .word 0x0eb02c02 323 .word 0x0ec02c02 324 .word 0x0ed02c02 325 .word 0x0ee02c02 326 .word 0x0ef02c02 327 .word 0x0f002c02 328 .word 0x0f102c02 329 .word 0x0f202c02 330 .word 0x0f302c02 331 .word 0x0f402c02 332 .word 0x0f502c02 333 .word 0x0f602c02 334 .word 0x0f702c02 335 .word 0x0f802c02 336 .word 0x0f902c02 337 .word 0x0fa02c02 338 .word 0x0fb02c02 339 .word 0x0fc02c02 340 .word 0x0fd02c02 341 .word 0x0fe02c02 342 .word 0x0ff02c02 343 .word 0x10002c02 344 .word 0x10102c02 345 .word 0x10202c02 346 .word 0x10302c02 347 .word 0x10402c02 348 .word 0x10502c02 349 .word 0x10602c02 350 .word 0x10702c02 351 .word 0x10802c02 352 .word 0x10902c02 353 .word 0x10a02c02 354 .word 0x10b02c02 355 .word 0x10c02c02 356 .word 0x10d02c02 357 .word 0x10e02c02 358 .word 0x10f02c02 359 .word 0x11002c02 360 .word 0x11102c02 361 .word 0x11202c02 362 .word 0x11302c02 363 .word 0x11402c02 364 .word 0x11502c02 365 .word 0x11602c02 366 .word 0x11702c02 367 .word 0x11802c02 368 .word 0x11902c02 369 .word 0x11a02c02 370 .word 0x11b02c02 371 .word 0x11c02c02 372 .word 0x11d02c02 373 .word 0x11e02c02 374 .word 0x11f02c02 375 .word 0x12002c02 376 .word 0x12102c02 377 .word 0x12202c02 378 .word 0x12302c02 379 .word 0x12402c02 380 .word 0x12502c02 381 .word 0x12602c02 382 .word 0x12702c02 383 .word 0x12802c02 384 .word 0x12902c02 385 .word 0x12a02c02 386 .word 0x12b02c02 387 .word 0x12c02c02 388 .word 0x12d02c02 389 .word 0x12e02c02 390 .word 0x12f02c02 391 .word 0x13002c02 392 .word 0x13102c02 393 .word 0x13202c02 394 .word 0x13302c02 395 .word 0x13402c02 396 .word 0x13502c02 397 .word 0x13602c02 398 .word 0x13702c02 399 .word 0x13802c02 400 .word 0x13902c02 401 .word 0x13a02c02 402 .word 0x13b02c02 403 .word 0x13c02c02 404 .word 0x13d02c02 405 .word 0x13e02c02 406 .word 0x13f02c02 407 .word 0x14002c02 408 .word 0x14102c02 409 .word 0x14202c02 410 .word 0x14302c02 411 .word 0x14402c02 412 .word 0x14502c02 413 .word 0x14602c02 414 .word 0x14702c02 415 .word 0x14802c02 416 .word 0x14902c02 417 .word 0x14a02c02 418 .word 0x14b02c02 419 .word 0x14c02c02 420 .word 0x14d02c02 421 .word 0x14e02c02 422 .word 0x14f02c02 423 .word 0x15002c02 424 .word 0x15102c02 425 .word 0x15202c02 426 .word 0x15302c02 427 .word 0x15402c02 428 .word 0x15502c02 429 .word 0x15602c02 430 .word 0x15702c02 431 .word 0x15802c02 432 .word 0x15902c02 433 .word 0x15a02c02 434 .word 0x15b02c02 435 .word 0x15c02c02 436 .word 0x15d02c02 437 .word 0x15e02c02 438 .word 0x15f02c02 439 .word 0x16002c02 440 .word 0x16102c02 441 .word 0x16202c02 442 .word 0x16302c02 443 .word 0x16402c02 444 .word 0x16502c02 445 .word 0x16602c02 446 .word 0x16702c02 447 .word 0x16802c02 448 .word 0x16902c02 449 .word 0x16a02c02 450 .word 0x16b02c02 451 .word 0x16c02c02 452 .word 0x16d02c02 453 .word 0x16e02c02 454 .word 0x16f02c02 455 .word 0x17002c02 456 .word 0x17102c02 457 .word 0x17202c02 458 .word 0x17302c02 459 .word 0x17402c02 460 .word 0x17502c02 461 .word 0x17602c02 462 .word 0x17702c02 463 .word 0x17802c02 464 .word 0x17902c02 465 .word 0x17a02c02 466 .word 0x17b02c02 467 .word 0x17c02c02 468 .word 0x17d02c02 469 .word 0x17e02c02 470 .word 0x17f02c02 471 .word 0x18002c02 472 .word 0x18102c02 473 .word 0x18202c02 474 .word 0x18302c02 475 .word 0x18402c02 476 .word 0x18502c02 477 .word 0x18602c02 478 .word 0x18702c02 479 .word 0x18802c02 480 .word 0x18902c02 481 .word 0x18a02c02 482 .word 0x18b02c02 483 .word 0x18c02c02 484 .word 0x18d02c02 485 .word 0x18e02c02 486 .word 0x18f02c02 487 .word 0x19002c02 488 .word 0x19102c02 489 .word 0x19202c02 490 .word 0x19302c02 491 .word 0x19402c02 492 .word 0x19502c02 493 .word 0x19602c02 494 .word 0x19702c02 495 .word 0x19802c02 496 .word 0x19902c02 497 .word 0x19a02c02 498 .word 0x19b02c02 499 .word 0x19c02c02 500 .word 0x19d02c02 501 .word 0x19e02c02 502 .word 0x19f02c02 503 .word 0x1a002c02 504 .word 0x1a102c02 505 .word 0x1a202c02 506 .word 0x1a302c02 507 .word 0x1a402c02 508 .word 0x1a502c02 509 .word 0x1a602c02 510 .word 0x1a702c02 511 .word 0x1a802c02 512 .word 0x1a902c02 513 .word 0x1aa02c02 514 .word 0x1ab02c02 515 .word 0x1ac02c02 516 .word 0x1ad02c02 517 .word 0x1ae02c02 518 .word 0x1af02c02 519 .word 0x1b002c02 520 .word 0x1b102c02 521 .word 0x1b202c02 522 .word 0x1b302c02 523 .word 0x1b402c02 524 .word 0x1b502c02 525 .word 0x1b602c02 526 .word 0x1b702c02 527 .word 0x1b802c02 528 .word 0x1b902c02 529 .word 0x1ba02c02 530 .word 0x1bb02c02 531 .word 0x1bc02c02 532 .word 0x1bd02c02 533 .word 0x1be02c02 534 .word 0x1bf02c02 535 .word 0x1c002c02 @ bcm95301x_svk_iproc_nand_config: make NAND flash code L1&L2 cachable 536 .word 0x1c102c02 537 .word 0x1c202c02 538 .word 0x1c302c02 539 .word 0x1c402c02 540 .word 0x1c502c02 541 .word 0x1c602c02 542 .word 0x1c702c02 543 .word 0x1c802c02 544 .word 0x1c902c02 545 .word 0x1ca02c02 546 .word 0x1cb02c02 547 .word 0x1cc02c02 548 .word 0x1cd02c02 549 .word 0x1ce02c02 550 .word 0x1cf02c02 551 .word 0x1d002c02 552 .word 0x1d102c02 553 .word 0x1d202c02 554 .word 0x1d302c02 555 .word 0x1d402c02 556 .word 0x1d502c02 557 .word 0x1d602c02 558 .word 0x1d702c02 559 .word 0x1d802c02 560 .word 0x1d902c02 561 .word 0x1da02c02 562 .word 0x1db02c02 563 .word 0x1dc02c02 564 .word 0x1dd02c02 565 .word 0x1de02c02 566 .word 0x1df02c02 567 .word 0x1e004c02 @DDR_SHMOO_RELATED_CHANGE: change 0x1e014ca2 to 0x1e016caa to make flash code L1&L2 cachable 568 .word 0x1e104c02 569 .word 0x1e204c02 570 .word 0x1e304c02 571 .word 0x1e404c02 572 .word 0x1e504c02 573 .word 0x1e604c02 574 .word 0x1e704c02 575 .word 0x1e804c0a 576 .word 0x1e904c0a 577 .word 0x1ea04c0a 578 .word 0x1eb04c0a 579 .word 0x1ec04c0a 580 .word 0x1ed04c0a 581 .word 0x1ee04c0a 582 .word 0x1ef04c0a 583 .word 0x1f004c0a 584 .word 0x1f104c0a 585 .word 0x1f204c0a 586 .word 0x1f304c0a 587 .word 0x1f404c0a 588 .word 0x1f504c0a 589 .word 0x1f604c0a 590 .word 0x1f704c0a 591 .word 0x1f804c0a 592 .word 0x1f904c0a 593 .word 0x1fa04c0a 594 .word 0x1fb04c0a 595 .word 0x1fc04c0a 596 .word 0x1fd04c0a 597 .word 0x1fe04c0a 598 .word 0x1ff04c0a 599 .word 0x20002c02 600 .word 0x20102c02 601 .word 0x20202c02 602 .word 0x20302c02 603 .word 0x20402c02 604 .word 0x20502c02 605 .word 0x20602c02 606 .word 0x20702c02 607 .word 0x20802c02 608 .word 0x20902c02 609 .word 0x20a02c02 610 .word 0x20b02c02 611 .word 0x20c02c02 612 .word 0x20d02c02 613 .word 0x20e02c02 614 .word 0x20f02c02 615 .word 0x21002c02 616 .word 0x21102c02 617 .word 0x21202c02 618 .word 0x21302c02 619 .word 0x21402c02 620 .word 0x21502c02 621 .word 0x21602c02 622 .word 0x21702c02 623 .word 0x21802c02 624 .word 0x21902c02 625 .word 0x21a02c02 626 .word 0x21b02c02 627 .word 0x21c02c02 628 .word 0x21d02c02 629 .word 0x21e02c02 630 .word 0x21f02c02 631 .word 0x22002c02 632 .word 0x22102c02 633 .word 0x22202c02 634 .word 0x22302c02 635 .word 0x22402c02 636 .word 0x22502c02 637 .word 0x22602c02 638 .word 0x22702c02 639 .word 0x22802c02 640 .word 0x22902c02 641 .word 0x22a02c02 642 .word 0x22b02c02 643 .word 0x22c02c02 644 .word 0x22d02c02 645 .word 0x22e02c02 646 .word 0x22f02c02 647 .word 0x23002c02 648 .word 0x23102c02 649 .word 0x23202c02 650 .word 0x23302c02 651 .word 0x23402c02 652 .word 0x23502c02 653 .word 0x23602c02 654 .word 0x23702c02 655 .word 0x23802c02 656 .word 0x23902c02 657 .word 0x23a02c02 658 .word 0x23b02c02 659 .word 0x23c02c02 660 .word 0x23d02c02 661 .word 0x23e02c02 662 .word 0x23f02c02 663 .word 0x24002c02 664 .word 0x24102c02 665 .word 0x24202c02 666 .word 0x24302c02 667 .word 0x24402c02 668 .word 0x24502c02 669 .word 0x24602c02 670 .word 0x24702c02 671 .word 0x24802c02 672 .word 0x24902c02 673 .word 0x24a02c02 674 .word 0x24b02c02 675 .word 0x24c02c02 676 .word 0x24d02c02 677 .word 0x24e02c02 678 .word 0x24f02c02 679 .word 0x25002c02 680 .word 0x25102c02 681 .word 0x25202c02 682 .word 0x25302c02 683 .word 0x25402c02 684 .word 0x25502c02 685 .word 0x25602c02 686 .word 0x25702c02 687 .word 0x25802c02 688 .word 0x25902c02 689 .word 0x25a02c02 690 .word 0x25b02c02 691 .word 0x25c02c02 692 .word 0x25d02c02 693 .word 0x25e02c02 694 .word 0x25f02c02 695 .word 0x26002c02 696 .word 0x26102c02 697 .word 0x26202c02 698 .word 0x26302c02 699 .word 0x26402c02 700 .word 0x26502c02 701 .word 0x26602c02 702 .word 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0xfc802c02 4128 .word 0xfc902c02 4129 .word 0xfca02c02 4130 .word 0xfcb02c02 4131 .word 0xfcc02c02 4132 .word 0xfcd02c02 4133 .word 0xfce02c02 4134 .word 0xfcf02c02 4135 .word 0xfd002c02 4136 .word 0xfd102c02 4137 .word 0xfd202c02 4138 .word 0xfd302c02 4139 .word 0xfd402c02 4140 .word 0xfd502c02 4141 .word 0xfd602c02 4142 .word 0xfd702c02 4143 .word 0xfd802c02 4144 .word 0xfd902c02 4145 .word 0xfda02c02 4146 .word 0xfdb02c02 4147 .word 0xfdc02c02 4148 .word 0xfdd02c02 4149 .word 0xfde02c02 4150 .word 0xfdf02c02 4151 .word 0xfe002c02 4152 .word 0xfe102c02 4153 .word 0xfe202c02 4154 .word 0xfe302c02 4155 .word 0xfe402c02 4156 .word 0xfe502c02 4157 .word 0xfe602c02 4158 .word 0xfe702c02 4159 .word 0xfe802c02 4160 .word 0xfe902c02 4161 .word 0xfea02c02 4162 .word 0xfeb02c02 4163 .word 0xfec02c02 4164 .word 0xfed02c02 4165 .word 0xfee02c02 4166 .word 0xfef02c02 4167 .word 0xff002c02 4168 .word 0xff102c02 4169 .word 0xff202c02 4170 .word 0xff302c02 4171 .word 0xff402c02 4172 .word 0xff502c02 4173 .word 0xff602c02 4174 .word 0xff702c02 4175 .word 0xff802c02 4176 .word 0xff902c02 4177 .word 0xffa02c02 4178 .word 0xffb02c02 4179 .word 0xffc02c02 4180 .word 0xffd02c02 4181 .word 0xffe02c02 4182 .word 0xfff02c02 4183#endif /* CFG_SHMOO */ 4184 4185/* Entry point */ 4186 .section .text.startup 4187 4188 .globl startup 4189startup: 4190 b tr_rst /* 0 - reset */ 4191 ldr pc,_tr_und /* 4 - undefined instruction */ 4192 ldr pc,_tr_swi /* 8 - software interrupt */ 4193 ldr pc,_tr_iab /* 0xc - prefetch abort */ 4194 ldr pc,_tr_dab /* 0x10 - data abort */ 4195 ldr pc,_tr_bad /* 0x14 - reserved */ 4196 ldr pc,_tr_irq /* 0x18 - external interrupt */ 4197 ldr pc,_tr_fiq /* 0x1c - fast interrupt */ 4198 4199_tr_und: 4200 .word tr_und 4201_tr_swi: 4202 .word tr_swi 4203_tr_iab: 4204 .word tr_iab 4205_tr_dab: 4206 .word tr_dab 4207_tr_bad: 4208 .word tr_bad 4209_tr_irq: 4210 .word tr_irq 4211_tr_fiq: 4212 .word tr_fiq 4213_pad: 4214 .word 0x12345678 /* now 16*4=64 */ 4215 4216 .org (BISZ_OFFSET-4) 4217_ddrclk: 4218 .word 0x0 4219 /* Record the size of the binary */ 4220 .org BISZ_OFFSET 4221 4222 .word BISZ_MAGIC 4223 .word text_start 4224 .word text_end 4225 .word data_start 4226 .word data_end 4227 .word bss_start 4228 .word bss_end 4229 .word _end 4230 4231 .balign envram_ofs 4232 /* Embedded NVRAM */ 4233 .global embedded_nvram 4234embedded_nvram: 4235 .fill 0x400,4,~0x48534C46 /* 'FLSH' */ 4236 .long 0x4c5a4d41 /* LZMA NVRAM Supported */ 4237 4238#ifdef _CFE_ 4239#if CFG_EMBEDDED_PIC 4240#define RUNTIME_RELOC_START __runtime_reloc_start 4241#define RUNTIME_RELOC_STOP __runtime_reloc_stop 4242#else 4243#define RUNTIME_RELOC_START 0 4244#define RUNTIME_RELOC_STOP 0 4245#endif 4246 4247#include "segtable.h" 4248 4249 .globl segment_table 4250segment_table: 4251 .word text_end /* [ 0] End of text (R_SEG_ETEXT) */ 4252 .word data_start /* [ 1] Beginning of data (R_SEG_FDATA) */ 4253 .word data_end /* [ 2] End of data (R_SEG_EDATA) */ 4254 .word _end /* [ 3] End of BSS (R_SEG_END) */ 4255 .word text_start /* [ 4] Beginning of text (R_SEG_FTEXT) */ 4256 .word bss_start /* [ 5] Beginning of BSS (R_SEG_FBSS) */ 4257 .word 0 /* [ 6] Global Pointer (R_SEG_GP) */ 4258 .word RUNTIME_RELOC_START /* [ 7] Beginning of reloc entries */ 4259 .word RUNTIME_RELOC_STOP /* [ 8] End of reloc entries */ 4260 .word 0 /* [ 9] R_SEG_APIENTRY */ 4261#endif /* __CFE_ */ 4262 4263/************************************************************************* 4264 * 4265 * Startup Code (reset vector) 4266 * 4267 * do important init only if we don't start from memory! 4268 * setup Memory and board specific bits prior to relocation. 4269 * relocate armboot to ram 4270 * setup stack 4271 * 4272 *************************************************************************/ 4273 4274/* 4275 * the actual reset code 4276 */ 4277tr_rst: 4278 mrs r0,cpsr 4279 mov r1,#(PS_MM) 4280 bic r0,r0,r1 4281 /* Switch to system mode and make sure interrupts are disabled */ 4282 mov r1,#(PS_I | PS_F | PS_SYS) 4283 orr r0,r0,r1 4284 msr cpsr,r0 4285initcpu: 4286 mov r0,#0 4287 4288 /* Initialize cp15 registers */ 4289 mcr p15,0,r0,c5,c0,0 /* DFSR */ 4290 mcr p15,0,r0,c5,c0,1 /* IFSR */ 4291 mcr p15,0,r0,c6,c0,0 /* DFAR */ 4292 mcr p15,0,r0,c6,c0,1 /* WFSR */ 4293 4294 /* Initialize system control register */ 4295 mrc p15,0,r1,c1,c0,0 4296 bic r1,r1,#0x7 /* Clear C, A, M bits */ 4297 bic r1,r1,#(0x1 << 12) /* Clear I bit */ 4298 orr r1,r1,#0x2000 /* Set V bit: high vectors (0xffff0000) */ 4299 orr r1,r1,#0x2 /* Set A bit: enable strict alignment */ 4300 mcr p15,0,r1,c1,c0,0 4301 4302 mcr p15,0,r0,c8,c7,0 /* Invalidate TLB */ 4303 mcr p15,0,r0,c7,c5,0 /* Invalidate icache */ 4304 mcr p15,0,r0,c7,c5,6 /* Invalidate BTAC */ 4305 mcr p15,0,r0,c7,c10,4 /* DSB */ 4306 mcr p15,0,r0,c7,c5,4 /* ISB */ 4307 4308 /* Identify current CPU */ 4309 mrc p15,0,r0,c0,c0,5 4310 and r0,r0,#0xf /* retrieve cpu core id */ 4311 cmp r0,#0 /* cpu core 0? */ 4312 beq check_startaddr 4313 4314 /* Changed the jump address for core 1 */ 4315 ldr r0,=0xffff002c /* This address contains a wfe instruction */ 4316 ldr r1,=0xffff0000 /* SKU ROM starting address */ 4317 str r0, [r1, #0x400] 4318 4319 ldr pc,=0xffff002c /* Go back to SKU ROM, waiting kernel SMP */ 4320 4321check_startaddr: 4322 adrl r0,startup /* r0: source start address */ 4323 ldr r1,=startup /* r1: target address */ 4324 cmp r0,r1 4325 beq szmem 4326 4327 /* Wake up core 1 */ 4328 mov r0,#0 4329 mcr p15,0,r0,c7,c10,4 4330 sev 4331 4332enable_cache: 4333 /* Enable I cache */ 4334 mrc p15,0,r1,c1,c0,0 4335 orr r1,r1,#0x1800 /* Enable I$ and branch prediction */ 4336 mcr p15,0,r1,c1,c0,0 4337 4338#ifdef CFG_SHMOO 4339 /* Invalidate data cache */ 4340 bl cpu_inv_dcache_all 4341 4342 /* Enable D cache */ 4343 mcr p15,0,r0,c7,c10,4 /* DSB */ 4344 mrc p15,0,r1,c1,c0,0 4345 orr r1,r1,#0x4 4346 mcr p15,0,r1,c1,c0,0 4347 mcr p15,0,r0,c7,c5,4 /* ISB */ 4348 4349 /* Invalidate TLB */ 4350 mcr p15,0,r0,c8,c7,0 4351 4352scu_enable: 4353 ldr r1,=IHOST_SCU_INVALIDATE 4354 mov r2,#0xff 4355 str r2,[r1] 4356 ldr r1,=IHOST_SCU_CONTROL 4357 ldr r2,[r1] 4358 orr r2,r2,#0x1 4359 str r2,[r1] 4360mmu_init: 4361 ldr r1,=startup 4362 ldr r2,=page_table 4363 sub r2,r2,r1 4364 adrl r1,startup 4365 add r1,r1,r2 4366 4367 /* Configure translation table base (TTB) control register cp15,c2 4368 * to a value of all zeros, indicates we are using TTB register 0 4369 */ 4370 mov r0,#0 4371 mcr p15,0,r0,c2,c0,2 4372 /* Load page table address to cp15 */ 4373 mcr p15,0,r1,c2,c0,0 4374 /* Set the access control to client */ 4375 ldr r1,=0xffffffff 4376 mcr p15,0,r1,c3,c0,0 4377 /* Enable MMU */ 4378 mrc p15,0,r1,c1,c0,0 4379 orr r1,r1,#0x1 4380 mcr p15,0,r1,c1,c0,0 4381 mcr p15,0,r0,c7,c5,4 /* ISB */ 4382 4383l2cc_init: 4384 ldr r1,=SI_ENUM_BASE 4385 ldr r2,=CC_CHIPID 4386 ldr r2,[r1,r2] 4387 ldr r1,=CID_ID_MASK 4388 and r2,r2,r1 4389 ldr r1,=0xcf12 /* NS Ax/Bx */ 4390 cmp r2,r1 4391 beq l2cc_256k 4392 ldr r1,=0xcf26 /* NS 47094 */ 4393 cmp r2,r1 4394 beq l2cc_256k 4395 ldr r1,=0xcf19 4396 cmp r2,r1 4397 bge l2cc_512k 4398l2cc_256k: 4399 ldr r1,=0x0a130000 4400 ldr r4,=0x111 4401 b l2cc_inv 4402l2cc_512k: 4403 ldr r1,=0x0a150000 4404 ldr r4,=0x131 4405l2cc_inv: 4406 ldr r2,=IHOST_L2C_CACHE_ID 4407 ldr r3,[r2,#0x104] 4408 bic r3,r3,#0x000f0000 4409 orr r3,r3,r1 4410 str r3,[r2,#0x104] 4411 ldr r1,=0x0 4412 str r1,[r2,#0x108] 4413 str r4,[r2,#0x10c] 4414 ldr r1,=0xffff 4415 str r1,[r2,#0x77c] 4416test_inv_way: 4417 ldr r1,[r2,#0x77c] 4418 cmp r1,r0 4419 bne test_inv_way 4420 4421 ldr r1,=0x1ff 4422 str r1,[r2,#0x220] /* int_clear */ 4423 mov r1,#0x1 4424 str r1,[r2,#0x100] /* control */ 4425 mcr p15,0,r0,c7,c10,4 /* DSB */ 4426 mcr p15,0,r0,c7,c5,4 /* ISB */ 4427 4428l2cc_lockdown: 4429 ldr r1,=0xc0000000 4430 ldr r2,=0xc0020000 /* 128KB */ 4431 ldr r4,=0xa5a5a5a5 4432 ldr r5,=0xa5a5a5a5 4433 ldr r6,=0xa5a5a5a5 4434 ldr r7,=0xa5a5a5a5 4435 ldr r8,=0xa5a5a5a5 4436 ldr r9,=0xa5a5a5a5 4437 ldr r10,=0xa5a5a5a5 4438 ldr r11,=0xa5a5a5a5 4439 /* Enable lockdown by line */ 4440 mov r3,#0x01 4441 ldr r0,=IHOST_L2C_CACHE_ID 4442 str r3,[r0,#0x950] 44431: 4444 stmia r1!,{r4-r11} 4445 ldr r3,=0x10 4446cdelay1: 4447 sub r3,r3,#1 4448 cmp r3,#0 4449 bne cdelay1 4450 cmp r1,r2 4451 bne 1b 4452 4453 /* Disable lockdown by line */ 4454 mov r3,#0 4455 ldr r0,=IHOST_L2C_CACHE_ID 4456 str r3,[r0,#0x950] 4457l2cc_init_done: 4458#endif /* CFG_SHMOO */ 4459 4460 /* BCM4708 WAR for PCIE2 */ 4461 ldr r0,=0x1a000000 4462 ldr r1,=0x0 4463 str r1,[r0] 4464 ldr r0,=0x18130e04 4465 ldr r1,=0x0 4466 str r1,[r0] 4467 ldr r0,=0x18130e00 4468 ldr r1,=0x1 4469 str r1,[r0] 4470 4471init_pcie: 4472 ldr r0,=SI_ENUM_BASE /* r0: core regs SI base address */ 4473 ldr r1,=CC_EROMPTR 4474 ldr r1,[r0,r1] /* r1: erom pointer */ 44751: ldr r2,[r1] /* r2: erom entry */ 4476 ldr r3,=(ER_TAG | ER_VALID) 4477 and r3,r3,r2 4478 cmp r3,#(ER_END | ER_VALID) /* Is this the END marker? */ 4479 beq no_pcie /* Yes: done and did not find pcie */ 4480 4481 cmp r3,#(ER_CI | ER_VALID) 4482 beq 2f 4483 4484 add r1,r1,#4 /* Next erom entry */ 4485 b 1b 4486 4487no_pcie: 4488 b find_bootdev 4489 4490 /* Found a CIA */ 44912: add r1,r1,#8 /* Skip both CIA & CIB */ 4492 ldr r3,=CIA_CID_MASK 4493 and r3,r3,r2 4494 ldr r4,=(NS_PCIEG2_CORE_ID << CIA_CID_SHIFT) 4495 cmp r3,r4 4496 bne 1b 4497 4498 /* Found pcie, get regs and wrapper and save them */ 4499 bl ai_get_slave 4500 mov r8,r0 4501 bl ai_get_wrapper 4502 mov r9,r0 4503 4504 /* Initialize memory controller and size memory */ 4505 mov r0,r8 4506 mov r1,r9 4507 bl pcie_init 4508 bl pcie_phy_init 4509 4510find_bootdev: 4511 ldr r0,=SI_ENUM_BASE /* r0: core regs SI base address */ 4512 ldr r1,=CC_EROMPTR 4513 ldr r1,[r0,r1] /* r1: erom pointer */ 45141: ldr r2,[r1] /* r2: erom entry */ 4515 ldr r3,=(ER_TAG | ER_VALID) 4516 and r3,r3,r2 4517 cmp r3,#(ER_END | ER_VALID) /* Is this the END marker? */ 4518 beq no_socrom_core /* Yes: done and did not find rom core */ 4519 4520 cmp r3,#(ER_CI | ER_VALID) 4521 beq 2f 4522 4523 add r1,r1,#4 /* Next erom entry */ 4524 b 1b 4525 4526no_socrom_core: 4527 b init_ddr 4528 4529 /* Found a CIA */ 45302: add r1,r1,#8 /* Skip both CIA & CIB */ 4531 ldr r3,=CIA_CID_MASK 4532 and r3,r3,r2 4533 ldr r4,=(NS_ROM_CORE_ID << CIA_CID_SHIFT) 4534 cmp r3,r4 4535 bne 1b 4536 4537 /* Found socrom, get regs and wrapper and save them */ 4538 bl ai_get_wrapper 4539 ldr r1,[r0,#AI_IOSTATUS] 4540 ldr r2,=SISF_NS_BOOTDEV_MASK 4541 and r1,r1,r2 4542 mov r7,r1 4543 ldr r0,=SISF_NS_BOOTDEV_OFFLOAD 4544 cmp r1,r0 4545 bne init_ddr 4546 4547offload_mode: 4548 ldr r4,=0x1 4549 ldr r5,=0xffff042c 4550 str r4,[r5] 4551 ldr r4,=0x0 4552 ldr r5,=0xffff0430 4553wait_for_host: 4554 ldr r6,[r5] 4555 cmp r6,r4 4556 beq wait_for_host 4557 bx r6 4558 4559/* 4560 * Find ddr core 4561 */ 4562init_ddr: 4563#ifdef CFG_SHMOO 4564 /* Copy to cache */ 4565copy2cache: 4566 adrl r0,startup /* r0: source start address */ 4567 ldr r1,=startup /* r1: target address */ 4568 cmp r0,r1 4569 beq l2c_clear_bss 4570 ldr r3,_bss_start_ofs 4571 add r2,r0,r3 /* r2: source end address */ 4572l2c_copy_loop: 4573 ldmia r0!,{r9-r10} /* copy from source address [r0] */ 4574 stmia r1!,{r9-r10} /* copy to target address [r1] */ 4575 cmp r0,r2 /* until source end address [r2] */ 4576 blo l2c_copy_loop 4577 4578 /* Clear BSS */ 4579l2c_clear_bss: 4580 ldr r0,_bss_start_ofs 4581 ldr r1,_bss_end_ofs 4582 ldr r4,=startup 4583 add r0,r0,r4 4584 add r1,r1,r4 4585 mov r2,#0x00000000 4586 /* empty bss section checking */ 4587 cmp r0,r1 4588 beq enable_arm_cyclecount 4589 4590l2c_clbss_l: 4591 str r2,[r0] 4592 add r0,r0,#4 4593 cmp r0,r1 4594 bne l2c_clbss_l 4595 4596/* Cycle Count */ 4597enable_arm_cyclecount: 4598 mrc p15,0,r1,c9,c12,0 4599 ldr r2,=1 4600 orr r1,r1,r2 4601 mcr p15,0,r1,c9,c12,0 /* Set enable bit in PMNC */ 4602 ldr r1,=0x80000000 4603 mcr p15,0,r1,c9,c12,1 4604 4605 /* setup stack pointer */ 4606 ldr r0,=0xc0000000 4607 ldr r1,=0x20000 /* 128KB */ 4608 add r0,r0,r1 4609 sub r0,r0,#8 4610 mov sp,r0 4611 bic sp,sp,#7 4612 ldr r0,_c_ddr_init_ofs 4613 ldr r1,=startup 4614 add lr,r1,r0 4615 ldr r0,_c_ddr_init_done_ofs 4616 adrl r1,startup 4617 add r0,r1,r0 4618 mov pc,lr 4619c_ddr_init_done: 4620#else /* CFG_SHMOO */ 4621 ldr r0,=SI_ENUM_BASE /* r0: core regs SI base address */ 4622 ldr r1,=CC_EROMPTR 4623 ldr r1,[r0,r1] /* r1: erom pointer */ 46241: ldr r2,[r1] /* r2: erom entry */ 4625 ldr r3,=(ER_TAG | ER_VALID) 4626 and r3,r3,r2 4627 cmp r3,#(ER_END | ER_VALID) /* Is this the END marker? */ 4628 beq panic /* Yes: done and did not find ddr */ 4629 4630 cmp r3,#(ER_CI | ER_VALID) 4631 beq 2f 4632 4633 add r1,r1,#4 /* Next erom entry */ 4634 b 1b 4635 4636panic: b . 4637 4638 /* Found a CIA */ 46392: add r1,r1,#8 /* Skip both CIA & CIB */ 4640 ldr r3,=CIA_CID_MASK 4641 and r3,r3,r2 4642 ldr r4,=(NS_DDR23_CORE_ID << CIA_CID_SHIFT) 4643 cmp r3,r4 4644 bne 1b 4645 4646 /* Found ddr, get regs and wrapper and save them */ 4647 bl ai_get_slave 4648 mov r8,r0 4649 bl ai_get_wrapper 4650 mov r9,r0 4651 4652 /* Initialize memory controller and size memory */ 4653 mov r0,r8 4654 mov r1,r9 4655 mov r2,r7 /* boot_dev */ 4656 4657 bl ddr_init 4658#endif /* CFG_SHMOO */ 4659 4660szmem: 4661 ldr r3,=0x80000000 4662 ldr r2,=0xaa55beef 4663 ldr r1,=0x00000000 4664 str r1,[r3,#0x3c] 4665 ldr r0,=(1 << 20) 4666 ldr r5,=(1 << 30) 46671: 4668 ldr r4,=0x80000000 4669 add r4,r4,r0 4670 str r2,[r4,#0x3c] 4671 ldr r1,[r4,#0x3c] /* Read back to ensure completion */ 4672 ldr r1,[r3,#0x3c] 4673 cmp r1,r2 4674 beq 2f 4675 4676 lsl r0,r0,#1 4677 cmp r0,r5 4678 bne 1b 4679 4680 /* Didn't find an alias, must be 128MB */ 46812: 4682 mov r8,r0 /* r8: the memory size in bytes */ 4683 4684/* Do CRU configure after DDR initied */ 4685#if !defined(CFG_ROMBOOT) 4686set_cru_policy7: 4687 ldr r0,=IHOST_PROC_CLK_WR_ACCESS 4688 ldr r1,=0xa5a501 4689 str r1,[r0] 4690 4691 ldr r3,=SI_ENUM_BASE 4692 ldr r4,=CC_CHIPID 4693 ldr r4,[r3,r4] 4694 ldr r3,=CID_PKG_MASK 4695 and r4,r4,r3 4696 lsr r3,r4,#CID_PKG_SHIFT 4697 4698 cmp r3,#0 4699 beq cpu_1g 4700 ldr r1,=0x1004001 /* 800MHz */ 4701 b set_clocks 4702 4703cpu_1g: 4704 ldr r1,=0x1005001 /* 1GHz */ 4705 b set_clocks 4706 4707set_clocks: 4708 ldr r0,=IHOST_PROC_CLK_PLLARMA 4709 str r1,[r0] 4710 ldr r2,=0x0 4711 4712 ldr r4,=0x100000 4713poll_plllock: 4714 cmp r4,r2 4715 beq poll_plllock_done 4716 sub r4,r4,#1 4717 ldr r1,[r0] 4718 and r3,r1,#(1 << IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK) 4719 cmp r3,r2 4720 beq poll_plllock 4721poll_plllock_done: 4722 orr r1,r1,#(1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB) 4723 str r1,[r0] 4724 ldr r0,=IHOST_PROC_CLK_POLICY_FREQ 4725 ldr r1,=0x87070707 4726 str r1,[r0] 4727 ldr r0,=IHOST_PROC_CLK_CORE0_CLKGATE 4728 ldr r1,=0x00010303 4729 str r1,[r0] 4730 ldr r0,=IHOST_PROC_CLK_CORE1_CLKGATE 4731 ldr r2,=0x00000303 4732 str r2,[r0] 4733 ldr r0,=IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 4734 str r1,[r0] 4735 ldr r0,=IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 4736 str r1,[r0] 4737 ldr r0,=IHOST_PROC_CLK_APB0_CLKGATE 4738 str r1,[r0] 4739 4740 ldr r0,=IHOST_PROC_CLK_POLICY_CTL 4741 ldr r2,=(1 << IHOST_PROC_CLK_POLICY_CTL__GO) 4742 ldr r3,=(1 << IHOST_PROC_CLK_POLICY_CTL__GO_AC) 4743 orr r3,r3,r2 4744 str r3,[r0] 4745 ldr r3,=0x0 4746 ldr r4,=0x100000 4747poll_ccu: 4748 cmp r4,r3 4749 beq poll_ccu_done 4750 sub r4,r4,#1 4751 ldr r1,[r0] 4752 and r1,r1,r2 4753 cmp r1,r3 4754 bne poll_ccu 4755poll_ccu_done: 4756#endif /* !defined(CFG_ROMBOOT) */ 4757 4758#ifndef CFG_SHMOO 4759 /* Copy to RAM */ 4760copy2ram: 4761 adrl r0,startup /* r0: source start address */ 4762 ldr r1,=startup /* r1: target address */ 4763 cmp r0,r1 4764 beq clear_bss 4765 ldr r3,_bss_start_ofs 4766 add r2,r0,r3 /* r2: source end address */ 4767copy_loop: 4768 ldmia r0!,{r9-r10} /* copy from source address [r0] */ 4769 stmia r1!,{r9-r10} /* copy to target address [r1] */ 4770 cmp r0,r2 /* until source end address [r2] */ 4771 blo copy_loop 4772 4773 /* Clear BSS */ 4774clear_bss: 4775 ldr r0,_bss_start_ofs 4776 ldr r1,_bss_end_ofs 4777 ldr r4,=startup 4778 add r0,r0,r4 4779 add r1,r1,r4 4780 mov r2,#0x00000000 4781 /* empty bss section checking */ 4782 cmp r0,r1 4783 beq enable_arm_cyclecount 4784 4785clbss_l: 4786 str r2,[r0] 4787 add r0,r0,#4 4788 cmp r0,r1 4789 bne clbss_l 4790 4791/* Cycle Count */ 4792enable_arm_cyclecount: 4793 mrc p15,0,r1,c9,c12,0 4794 ldr r2,=1 4795 orr r1,r1,r2 4796 mcr p15,0,r1,c9,c12,0 /* Set enable bit in PMNC */ 4797 ldr r1,=0x80000000 4798 mcr p15,0,r1,c9,c12,1 4799#endif /* !CFG_SHMOO */ 4800/* Set stackpointer in internal RAM to call c_main */ 4801call_c_main: 4802 /* Save memory size in bytes */ 4803 mov r0,r8 4804 cmp r0,#(128<<20) 4805 ble 1f 4806 mov r0,#(128<<20) 48071: 4808 ldr r1,=_memsize 4809 str r0,[r1] 4810 4811#ifdef _CFE_ 4812 _LSR_ r8,r8,#10 /* memory size in Kbytes */ 4813 ldr r1,=mem_totalsize 4814 str r8,[r1] 4815 4816 /* not relocating, no offset */ 4817 ldr r0,=0 4818 ldr r1,=mem_datareloc 4819 str r0,[r1] 4820 ldr r1,=mem_textreloc 4821 str r0,[r1] 4822 4823 ldr r0,_text_start_ofs 4824 add r0,r0,r4 4825 ldr r1,=mem_bottomofmem 4826 str r0,[r1] 4827 4828 ldr r0,__end_ofs 4829 add r0,r0,r4 4830 ldr r1,=mem_heapstart 4831 str r0,[r1] 4832 4833 add r0,#(CFG_HEAP_SIZE*1024) 4834 add r0,#STACK_SIZE 4835 ldr r1,=mem_topofmem 4836 str r0,[r1] 4837 4838 ldr r0,_text_start_ofs 4839 add r0,r0,r4 4840 ldr r2,_text_end_ofs 4841 add r2,r2,r4 4842 sub r2,r2,r0 4843 ldr r1,=mem_textsize 4844 str r2,[r1] 4845 ldr r1,=mem_textbase 4846 str r0,[r1] 4847 4848 ldr r0,=0x00000000 4849 ldr r1,=cpu_prid 4850 str r0,[r1] 4851 4852 /* Set the segment_table */ 4853 /* text_end */ 4854 ldr r0,_text_end_ofs 4855 add r0,r0,r4 4856 ldr r1,=segment_table 4857 str r0,[r1] 4858 4859 /* data_start */ 4860 ldr r0,_data_start_ofs 4861 add r0,r0,r4 4862 add r1,r1,#4 4863 str r0,[r1] 4864 4865 /* data_end */ 4866 ldr r0,_data_end_ofs 4867 add r0,r0,r4 4868 add r1,r1,#4 4869 str r0,[r1] 4870 4871 /* _end */ 4872 ldr r0,__end_ofs 4873 add r0,r0,r4 4874 add r1,r1,#4 4875 str r0,[r1] 4876 4877 /* text_start */ 4878 ldr r0,_text_start_ofs 4879 add r0,r0,r4 4880 add r1,r1,#4 4881 str r0,[r1] 4882 4883 /* bss_start */ 4884 ldr r0,_bss_start_ofs 4885 add r0,r0,r4 4886 add r1,r1,#4 4887 str r0,[r1] 4888 4889 /* _gp (0) */ 4890 mov r0,#0 4891 add r1,r1,#4 4892 str r0,[r1] 4893 4894 /* RUNTIME_RELOC_START (0) */ 4895 mov r0,#0 4896 add r1,r1,#4 4897 str r0,[r1] 4898 4899 /* RUNTIME_RELOC_STOP (0) */ 4900 mov r0,#0 4901 add r1,r1,#4 4902 str r0,[r1] 4903 4904 /* cpu_apientry (0) */ 4905 mov r0,#0 4906 add r1,r1,#4 4907 str r0,[r1] 4908 4909 ldr r1,=mem_topofmem 4910#else /* !_CFE_ */ 4911 ldr r1,=_memsize 4912#endif /* _CFE_ */ 4913 4914 ldr r0,[r1] 4915 sub r0,r0,#8 4916 mov sp,r0 4917 bic sp,sp,#7 /* 8-byte alignment for ABI compliance */ 4918 4919 ldr r0,_c_main_ofs 4920 ldr r1,=startup 4921 add lr, r0, r1 4922 /* setup parameters for c_main */ 4923#ifdef _CFE_ 4924 /* CFE: clear argument a & b in cfe_main */ 4925 ldr r0,=0x00000000 4926 ldr r1,=0x00000000 4927#else 4928 /* CFEZ: set return addr to argment ra */ 4929 ldr r0,_theend_ofs 4930 add r0,r0,r2 4931#endif 4932 /* jump to it ... */ 4933 mov pc,lr 4934 4935/* In case c_main returns */ 4936theend: 4937 TRACE(0x424feedd) 4938 wfe 4939 b theend 4940 4941 4942/* 4943 * These are defined in the board-specific linker script. 4944 */ 4945 4946#ifdef _CFE_ 4947.globl _text_start_ofs 4948_text_start_ofs: 4949 .word text_start - startup 4950 4951.globl _text_end_ofs 4952_text_end_ofs: 4953 .word text_end - startup 4954 4955.globl _data_start_ofs 4956_data_start_ofs: 4957 .word data_start - startup 4958 4959.globl _data_end_ofs 4960_data_end_ofs: 4961 .word data_end - startup 4962 4963.globl __end_ofs 4964__end_ofs: 4965 .word _end - startup 4966#endif /* _CFE_ */ 4967 4968.globl _bss_start_ofs 4969_bss_start_ofs: 4970 .word bss_start - startup 4971 4972.globl _bss_end_ofs 4973_bss_end_ofs: 4974 .word bss_end - startup 4975 4976#ifdef CFG_SHMOO 4977_c_ddr_init_ofs: 4978 .word c_ddr_init - startup 4979 4980_c_ddr_init_done_ofs: 4981 .word c_ddr_init_done - startup 4982#endif /* CFG_SHMOO */ 4983 4984_c_main_ofs: 4985 .word c_main - startup 4986 4987_theend_ofs: 4988 .word theend - startup 4989 4990/* Init PCIE mappings */ 4991FUNC(pcie_init) 4992 ldr r5,=REG_BAR2_CONFIG_F0 4993 str r5,[r0,#PAXB_INDR_ADDR] 4994 ldr r3,[r0,#PAXB_INDR_DATA] 4995 and r3,r3,#0xfffffff0 4996 orr r3,r3,#0xc 4997 str r3,[r0,#PAXB_INDR_DATA] 4998 4999 ldr r3,[r0,#PAXB_IARR_1_LOWER] 5000 and r3,r3,#0xffffff00 5001 orr r3,r3,#0x80 5002 str r3,[r0,#PAXB_IARR_1_LOWER] 5003 ldr r3,=0x40000000 5004 str r3,[r0,#PAXB_IARR_1_UPPER] 5005 5006 ldr r3,=0x00000001 5007 str r3,[r0,#PAXB_FUNC0_IMAP1] 5008 bx lr 5009END(pcie_init) 5010 5011/* 5012 * Find the first slave address for a core in the AI EROM 5013 * Input: 5014 * r1 - pointer to EROM after CIB 5015 * Output: 5016 * r0 - slave address 5017 * Changed: 5018 * r0, r1, r2 5019 */ 5020FUNC(ai_get_slave) 50211: ldr r0,[r1] 5022 ldr r2,=(ER_TAG | ER_VALID) 5023 add r1,r1,#4 /* Next erom entry */ 5024 and r2,r2,r0 5025 cmp r2,#(ER_ADD | ER_VALID) 5026 bne 1b 5027 50282: ldr r2,=AD_ADDR_MASK 5029 and r0,r0,r2 5030 bx lr 5031END(ai_get_slave) 5032 5033 5034/* 5035 * Find the first wrapper address for a core in the AI EROM 5036 * Input: 5037 * r1 - pointer to EROM after first slave ADD 5038 * Output: 5039 * r0 - wrapper address 5040 * Changed: 5041 * r0, r1, r2, r3 5042 */ 5043FUNC(ai_get_wrapper) 50441: ldr r0,[r1] 5045 ldr r2,=(ER_TAG | ER_VALID) 5046 add r1,r1,#4 /* Next erom entry */ 5047 and r2,r2,r0 5048 cmp r2,#(ER_ADD | ER_VALID) 5049 bne 1b 5050 5051 /* An address descriptor, is it a wrapper? */ 5052 ldr r2,=AD_ST_SWRAP /* We test just for the SWRAP bit set, */ 5053 tst r0,r2 /* that gets both Master and Slave */ 5054 beq 1b /* wrappers. */ 5055 5056 /* It is, isolate address and return */ 5057 ldr r2,=AD_ADDR_MASK 5058 and r0,r0,r2 5059 bx lr 5060END(ai_get_wrapper) 5061 5062 5063/* Interrupt handlers */ 5064/* Note: hndrte_arm.c for EXT_CBALL expects each trap handler to be 16 bytes */ 5065LEAF(__traps) 5066 5067/* Undefined instruction exception handler */ 5068tr_und: 5069 srsdb sp!, #PS_SYS /* use system mode stack */ 5070 cps #PS_SYS 5071 5072 /* now cr4 is in system mode */ 5073 /* lr has the value before the exception, push it to stack */ 5074 push {r0} /* hold the place for r15 */ 5075 push {lr} 5076 sub sp,sp,#24 /* skip r8-r13 now */ 5077 push {r0-r7} /* save r0-r7 to the stack */ 5078 eor r0,r0,r0 5079 add r0,r0,#TR_UND 5080 b trap 5081 5082/* Software interrupt exception handler */ 5083tr_swi: 5084 srsdb sp!, #PS_SYS /* use system mode stack */ 5085 cps #PS_SYS 5086 5087 push {r0} /* hold the place for r15 */ 5088 push {lr} 5089 sub sp,sp,#24 /* skip r8-r13 now */ 5090 push {r0-r7} 5091 eor r0,r0,r0 5092 add r0,r0,#TR_SWI 5093 b trap 5094 5095/* Prefetch abort exception handler */ 5096tr_iab: 5097 /* adjust lr to the address of abort insturction fetch */ 5098 mov sp,lr 5099 sub sp,sp,#4 5100 mov lr,sp 5101 srsdb sp!, #PS_SYS /* use system mode stack */ 5102 cps #PS_SYS 5103 5104 push {r0} /* hold the place for r15 */ 5105 push {lr} 5106 sub sp,sp,#24 /* skip r8-r13 now */ 5107 push {r0-r7} 5108 eor r0,r0,r0 5109 add r0,r0,#TR_IAB 5110 b trap 5111 5112/* Data abort exception handler */ 5113tr_dab: 5114 /* adjust lr to the address of aborted data fetch */ 5115 mov sp,lr 5116 sub sp,sp,#8 5117 mov lr,sp 5118 srsdb sp!, #PS_SYS /* use system mode stack */ 5119 cps #PS_SYS 5120 5121 push {r0} /* hold the place for r15 */ 5122 push {lr} 5123 sub sp,sp,#24 /* skip r8-r13 now */ 5124 push {r0-r7} 5125 eor r0,r0,r0 5126 add r0,r0,#TR_DAB 5127 b trap 5128 5129tr_bad: /* reserved */ 5130 mov sp,lr 5131 sub sp,sp,#4 5132 mov lr,sp 5133 srsdb sp!, #PS_SYS /* use system mode stack */ 5134 cps #PS_SYS 5135 5136 push {r0} /* hold the place for r15 */ 5137 push {lr} 5138 sub sp,sp,#24 /* skip r8-r13 now */ 5139 push {r0-r7} 5140 eor r0,r0,r0 5141 add r0,r0,#TR_BAD 5142 b trap 5143 5144/* Interrupt handler */ 5145tr_irq: 5146 /* subtract the offset */ 5147 mov sp,lr 5148 sub sp,sp,#4 5149 mov lr,sp 5150 srsdb sp!, #PS_SYS /* use system mode stack */ 5151 cps #PS_SYS 5152 5153 push {r0} /* hold the place for r15 */ 5154 push {lr} 5155 sub sp,sp,#24 /* skip r8-r13 now */ 5156 push {r0-r7} 5157 eor r0,r0,r0 5158 add r0,r0,#TR_IRQ 5159 b trap 5160 5161 5162/* Fast interrupt handler */ 5163tr_fiq: 5164 mov sp,lr 5165 sub sp,sp,#4 5166 mov lr,sp 5167 srsdb sp!, #PS_SYS /* use system mode stack */ 5168 cps #PS_SYS 5169 5170 push {r0} /* hold the place for r15 */ 5171 push {lr} 5172 sub sp,sp,#24 /* skip r8-r13 now */ 5173 push {r0-r7} 5174 eor r0,r0,r0 5175 add r0,r0,#TR_FIQ 5176 b trap 5177 5178/* Generic exception handler */ 5179trap: 5180 /* 5181 * construt the trap structure in system mode stack 5182 */ 5183 /* save trap type, epc, cpsr and spsr */ 5184 mov r4, sp /* sp is now at r0 */ 5185 add r4,r4,#64 5186 ldmia r4!, {r1,r3} /* r1<-epc, r3<-spsr */ 5187 mrs r2, cpsr 5188 push {r0,r1,r2,r3} /* trap type(r0), epc(r1), cpsr,spsr */ 5189 5190 /* fix the value of pc in trap structure */ 5191 sub r4,r4,#12 5192 str r1,[r4] /* save the value or epc as r15 into the stack */ 5193 5194 /* save r8 - r13 */ 5195 mov r7,sp /* sp is at the being of the trap structure now */ 5196 add r7,r7,#TRAP_T_SIZE + 8 /* sp value before the exception */ 5197 mov r6,r12 5198 mov r5,r11 5199 mov r4,r10 5200 mov r3,r9 5201 mov r2,r8 5202 add sp,sp,#72 /* move sp to r14 */ 5203 push {r2-r7} /* save r8-r13 to stack */ 5204 5205 sub sp,sp,#48 /* move sp back to the top of trap structure */ 5206 5207 /* If trap_hook is null, go to the end */ 5208 ldr r4,=trap_hook 5209 ldr r4,[r4] 5210 cmp r4,#0 52111: beq 1b 5212 /* else call (*trap_hook)(trap_t) */ 5213 mov r0,sp 5214 blx r4 5215 5216/* Restore the state from the trap_t */ 5217rfe: 5218 /* pop r8-r14 */ 5219 add sp,sp,#48 5220 pop {r0-r6} /* r8 - r14 */ 5221 mov r8,r0 5222 mov r9,r1 5223 mov r10,r2 5224 mov r11,r3 5225 mov r12,r4 5226 mov lr,r6 /* restore lr */ 5227 5228 sub sp,sp,#60 /* move sp to point to r0 */ 5229 pop {r0-r7} 5230 5231 /* move sp to point to epc and spsr saved by srs */ 5232 add sp,sp,#32 5233 5234 /* Restore cpsr, sp and return */ 5235 rfeia sp! /* done! */ 5236END(__traps) 5237 5238FUNC(_getticks) 5239 mrc p15,0,r0,c9,c13,0 5240 bx lr 5241END(_getticks) 5242 5243/* Flush the whole D-cache */ 5244cpu_flush_dcache_all: 5245 mrc p15, 1, r0, c0, c0, 1 @ read clidr 5246 ands r3, r0, #0x7000000 @ extract loc from clidr 5247 mov r3, r3, lsr #23 @ left align loc bit field 5248 beq finished @ if loc is 0, then no need to clean 5249 mov r10, #0 @ start clean at cache level 0 5250loop1: 5251 add r2, r10, r10, lsr #1 @ work out 3x current cache level 5252 mov r1, r0, lsr r2 @ extract cache type bits from clidr 5253 and r1, r1, #7 @ mask of the bits for current cache only 5254 cmp r1, #2 @ see what cache we have at this level 5255 blt skip @ skip if no cache, or just i-cache 5256 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 5257 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, 5258 @ with armv7 this is 'isb', 5259 @ but we compile with armv5 5260 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 5261 and r2, r1, #7 @ extract the length of the cache lines 5262 add r2, r2, #4 @ add 4 (line length offset) 5263 ldr r4, =0x3ff 5264 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 5265 clz r5, r4 @ find bit position of way size increment 5266 ldr r7, =0x7fff 5267 ands r7, r7, r1, lsr #13 @ extract max number of the index size 5268loop2: 5269 mov r9, r4 @ create working copy of max way size 5270loop3: 5271 orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 5272 orr r11, r11, r7, lsl r2 @ factor index number into r11 5273 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 5274 subs r9, r9, #1 @ decrement the way 5275 bge loop3 5276 subs r7, r7, #1 @ decrement the index 5277 bge loop2 5278skip: 5279 add r10, r10, #2 @ increment cache number 5280 cmp r3, r10 5281 bgt loop1 5282finished: 5283 mov r10, #0 @ swith back to cache level 0 5284 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 5285 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, 5286 @ with armv7 this is 'isb', 5287 @ but we compile with armv5 5288 mov pc, lr 5289 5290FUNC(cpu_flush_cache_all) 5291 stmfd sp!, {r0-r7, r9-r11, lr} 5292 bl cpu_flush_dcache_all 5293 mov r0, #0 5294 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 5295 ldmfd sp!, {r0-r7, r9-r11, lr} 5296 mov pc, lr 5297END(cpu_flush_cache_all) 5298 5299/* Invalidate the whole D-cache */ 5300cpu_inv_dcache_all: 5301 mrc p15, 1, r0, c0, c0, 1 @ read clidr 5302 ands r3, r0, #0x7000000 @ extract loc from clidr 5303 mov r3, r3, lsr #23 @ left align loc bit field 5304 beq invfinished @ if loc is 0, then no need to clean 5305 mov r10, #0 @ start clean at cache level 0 5306invloop1: 5307 add r2, r10, r10, lsr #1 @ work out 3x current cache level 5308 mov r1, r0, lsr r2 @ extract cache type bits from clidr 5309 and r1, r1, #7 @ mask of the bits for current cache only 5310 cmp r1, #2 @ see what cache we have at this level 5311 blt invskip @ skip if no cache, or just i-cache 5312 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 5313 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, 5314 @ with armv7 this is 'isb', 5315 @ but we compile with armv5 5316 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 5317 and r2, r1, #7 @ extract the length of the cache lines 5318 add r2, r2, #4 @ add 4 (line length offset) 5319 ldr r4, =0x3ff 5320 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 5321 clz r5, r4 @ find bit position of way size increment 5322 ldr r7, =0x7fff 5323 ands r7, r7, r1, lsr #13 @ extract max number of the index size 5324invloop2: 5325 mov r9, r4 @ create working copy of max way size 5326invloop3: 5327 orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 5328 orr r11, r11, r7, lsl r2 @ factor index number into r11 5329 mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way 5330 subs r9, r9, #1 @ decrement the way 5331 bge invloop3 5332 subs r7, r7, #1 @ decrement the index 5333 bge invloop2 5334invskip: 5335 add r10, r10, #2 @ increment cache number 5336 cmp r3, r10 5337 bgt invloop1 5338invfinished: 5339 mov r10, #0 @ swith back to cache level 0 5340 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 5341 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, 5342 @ with armv7 this is 'isb', 5343 @ but we compile with armv5 5344 mov pc, lr 5345 5346FUNC(cpu_inv_cache_all) 5347 stmfd sp!, {r0-r7, r9-r11, lr} 5348 bl cpu_inv_dcache_all 5349 mov r0, #0 5350 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 5351 ldmfd sp!, {r0-r7, r9-r11, lr} 5352 mov pc, lr 5353END(cpu_inv_cache_all) 5354 5355/* Dummy function just for link happy */ 5356FUNC(raise) 5357 5358 mov r0, #0 5359 mov pc, lr 5360 5361END(raise) 5362 5363FUNC(__aeabi_unwind_cpp_pr0) 5364 5365 mov pc, lr 5366 5367END(__aeabi_unwind_cpp_pr0) 5368 5369/* 5370 * Common code/data start here... 5371 */ 5372#ifdef CONFIG_XIP 5373 .data 5374#endif 5375 5376 DW(_memsize, 0) 5377 5378/* C trap handler */ 5379 DW(trap_hook, 0) 5380 5381#ifdef CONFIG_XIP 5382 .text 5383#endif 5384 5385#ifdef _CFE_ 5386 5387/* 5388 * Setup the trap handler. 5389 */ 5390FUNC(hndrte_set_trap) 5391 5392 ldr r2,=trap_hook 5393 ldr r1,[r2] 5394 str r0,[r2] 5395 mov r0,r1 5396 bx lr 5397 5398END(hndrte_set_trap) 5399 5400/* 5401 * Turn remap off and then jump to an given address 5402 */ 5403FUNC(arm_jumpto) 5404 5405 bx r0 5406 5407END(arm_jumpto) 5408 5409/* ********************************************************************* 5410 * CFE_FLUSHCACHE 5411 * 5412 * Perform certain cache operations 5413 * 5414 * Input parameters: 5415 * a0 - flags (CFE_CACHE_xxx flags, or zero for a default) 5416 * a1,a2 - start/end of range for "range invalidate" operations 5417 * (not used otherwise) 5418 * 5419 * Return value: 5420 * nothing 5421 ********************************************************************* */ 5422 5423FUNC(_cfe_flushcache) 5424 5425#ifndef CFG_UNCACHED 5426 mov ip,lr /* save lr across calls */ 5427 bl cpu_flush_cache_all 5428 mov lr,ip /* restore lr */ 5429#endif 5430 5431 mov pc, lr 5432 5433 5434END(_cfe_flushcache) 5435 5436# 5437# arguments: r0=start, r1=size 5438# 5439FUNC(_cfe_flushcache_rang) 5440 5441 mrc p15, 1, r3, c0, c0, 0 @ read CSIDR 5442 and r3, r3, #7 @ cache line size encoding 5443 mov r2, #16 @ size offset 5444 mov r2, r2, lsl r3 @ actual cache line size 5445 5446 sub r3, r2, #1 5447 bic r0, r0, r3 54481: 5449 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 5450 add r0, r0, r2 5451 cmp r0, r1 5452 blo 1b 5453# dsb 5454 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, 5455 @ with armv7 this is 'isb', 5456 @ but we compile with armv5 5457 mov pc, lr 5458 5459END(_cfe_flushcache_rang) 5460 5461/* ********************************************************************* 5462 * CFE_LAUNCH 5463 * 5464 * Start the user program. The program is passed a handle 5465 * that must be passed back when calling the firmware. 5466 * 5467 * Parameters passed to the called program are as follows: 5468 * 5469 * a0 - CFE handle 5470 * a1 - entry vector 5471 * a2 - reserved, will be 0 5472 * a3 - entrypoint signature. 5473 * 5474 * Input parameters: 5475 * a0 - entry vector 5476 * 5477 * Return value: 5478 * does not return 5479 ********************************************************************* */ 5480 5481FUNC(cfe_launch) 5482 5483 sub sp,sp,#8 5484 push {r0} 5485 5486 /* 5487 * Mask all interrupts. 5488 */ 5489 5490 mrs r0,cpsr 5491 ldr r1,=(PS_I | PS_F) 5492 orr r0,r0,r1 5493 msr cpsr,r0 5494 5495 /* 5496 * Flush the D-Cache, since the program we loaded is "data". 5497 * Invalidate the I-Cache, so that addresses in the program 5498 * region will miss and need to be filled from the data we 5499 * just flushed above. 5500 */ 5501 5502 bl _cfe_flushcache 5503 5504 /* 5505 * Disable the D-Cache, MMU and I-Cache bit 5506 */ 5507 5508 mrc p15,0,r0,c1,c0,0 @ read SCTLR 5509 bic r0,r0,#4 @ disable D-Cache 5510 bic r0,r0,#1 @ disable MMU 5511 bic r0,r0,#1000 @ disable I-Cache 5512 mcr p15,0,r0,c1,c0,0 5513 5514 /* 5515 * Set things up for launching the program. Pass the 5516 * handle in A0 - apps need to remember that and pass it 5517 * back. 5518 */ 5519 b RunProgram 5520 5521END(cfe_launch) 5522 5523/* 5524 * This is a nice place to set a breakpoint. 5525 */ 5526FUNC(RunProgram) 5527 5528 LOADREL(r2,=segment_table) 5529 ldr r2,[r2,#R_SEG_APIENTRY] /* A2 = code entry */ 5530 5531#if CFG_EMBEDDED_PIC 5532 ldr r1,mem_textreloc /* relocate table entry */ 5533 add r2,r2,r1 5534#endif 5535 5536 mov r4,r0 5537 mov r1,#0 /* A1 = 0 */ 5538 mov r0,#0 /* A0 = handle */ 5539 ldr r3,=CFE_EPTSEAL /* A3 = entrypoint signature */ 5540 pop {r4} /* entry point */ 5541 5542 /* Check if the MERGE_FRAG function should execute or not, 5543 * according to the information within structure cfe_frag_info_t. 5544 * _frag_info_sz is the size of structure cfe_frag_info_t. 5545 * Structure cfe_frag_info_t is stored right before MERGE_FRAG function, and 5546 * MERGE_FRAG function is stored right before entry point. 5547 * Note: {r0-r4} must be preserved 5548 */ 5549 ldr r7, =_frag_merge_func_len 5550 ldr r6, [r7] 5551 ldr r8, =_frag_info_sz 5552 ldr r7, [r8] 5553 add r6, r6, r7 5554 sub r5, r4, r6 5555 ldr r6, [r5] 5556 cmp r6, #0 5557 beq do_run 5558 mov pc, r6 /* Go to _merge_func */ 5559do_run: 5560 mov pc, r4 /* go for it. */ 5561END(RunProgram) 5562 5563 5564 .globl _frag_merge_func 5565_frag_merge_func: 5566 .word _merge_func 5567 5568 .globl _frag_merge_func_len 5569_frag_merge_func_len: 5570 .word _merge_func_end - _merge_func 5571 5572 .globl _frag_info_sz 5573_frag_info_sz: 5574 .word 0 5575 5576/* This merge_func will relocate at address which is stored at MERGE_FRAG. 5577 * It will reference the value which is stored at MERGE_FRAG. 5578 * There are the merge_func pointer, des_addr, src_addr and length. 5579 * r4 is the entry point, r0-r3 are the parameters for the image. 5580 * r5 is the address of MERGE_FRAG 5581 */ 5582FUNC(_merge_func) 5583 ldmia r5, {r9-r12} 55841: 5585 ldmia r11!, {r7-r8} @ copy 8 bytes from the memory at r11 address 5586 stmia r10!, {r7-r8} @ store 8 bytes to the memory at r10 address 5587 @ r12 is the length, each loop copy 8 bytes 5588 subs r12, r12, #8 @ adjust the length 5589 bgt 1b 5590 5591 mov pc, r4 @ jump to the entry point 5592_merge_func_end: 5593END(_merge_func) 5594 5595/* ********************************************************************* 5596 * BOARD_SETLEDS(x) 5597 * 5598 * Set LEDs for boot-time progress indication. Not used if 5599 * the board does not have progress LEDs. This routine 5600 * must not call any other routines, since it may be invoked 5601 * either from KSEG0 or KSEG1 and it may be invoked 5602 * whether or not the icache is operational. 5603 * 5604 * Input parameters: 5605 * a0 - LED value (8 bits per character, 4 characters) 5606 * 5607 * Return value: 5608 * nothing 5609 ********************************************************************* */ 5610FUNC(board_setleds) 5611 5612 mov pc, lr @ back to my caller 5613 5614END(board_setleds) 5615 5616/* ********************************************************************* 5617 * CFE_LEDS 5618 * 5619 * Set the on-board LEDs. 5620 * 5621 * Input parameters: 5622 * a0 - LEDs 5623 * 5624 * Return value: 5625 * nothing 5626 ********************************************************************* */ 5627FUNC(cfe_leds) 5628 5629 /* jump to BSP routine */ 5630 //bl board_setleds 5631 5632 /* return */ 5633 mov pc, lr 5634 5635END(cfe_leds) 5636 5637/* ********************************************************************* 5638 * _GETSEGTBL() 5639 * 5640 * Return the address of the segment table. We use this 5641 * to display the startup messages. 5642 * 5643 * You can't just address the table from C because it lives 5644 * in the text segment. 5645 * 5646 * Input parameters: 5647 * nothing 5648 * 5649 * Return value: 5650 * address of table 5651 ********************************************************************* */ 5652 5653FUNC(_getsegtbl) 5654 5655 mov ip, lr /* persevere link reg across call */ 5656 LOADREL(r0,=segment_table) 5657 mov lr, ip /* restore link */ 5658 mov pc, lr /* back to my caller */ 5659 5660END(_getsegtbl) 5661 5662/* ********************************************************************* 5663 * _SETCONTEXT() 5664 * 5665 * Set the CONTEXT register. 5666 * 5667 * Input parameters: 5668 * a0 - context 5669 * 5670 * Return value: 5671 * nothing 5672 ********************************************************************* */ 5673 5674FUNC(_setcontext) 5675 5676 mov pc,lr 5677 5678END(_setcontext) 5679 5680/* ********************************************************************* 5681 * CFE_WARMSTART 5682 * 5683 * Restart the command interpreter 5684 * 5685 * Input parameters: 5686 * A0 - command status 5687 * nothing (GP has already been set up for us) 5688 * 5689 * Return value: 5690 * nothing 5691 ********************************************************************* */ 5692 5693FUNC(cfe_warmstart) 5694 5695 mov pc,lr 5696 5697END(cfe_warmstart) 5698 5699#endif /* _CFE_ */ 5700