/*
 * BCM53XXX ARM/Cortext A9 boot code for standalone apps.
 *
 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved.
 * 
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 * $Id$
 */

#include <arminc.h>
#include <sbhndarm.h>
#include <hndrte_armtrap.h>
#include <hndsoc.h>
#include <sbchipc.h>
#include <bcmdevs.h>
#include <ddr_core.h>
#include <pcieg2_core.h>
#include <armca9_core.h>

#ifdef _CFE_

#include <armmacros.h>
#include "initdata.h"
#include "bsp_config.h"
#include "cfe_devfuncs.h"

#define c_main	cfe_main

/*
 * This is the size of the stack, rounded to KByte boundaries.
 */

#ifndef CFG_STACK_SIZE
#error "CFG_STACK_SIZE not defined"
#else
#define STACK_SIZE	((CFG_STACK_SIZE+1023) & ~1023)
#endif

#define envram_ofs	0x1000

#else /* !_CFE_ */

#if defined(__thumb__)
#define FUNC(x)	THUMBLEAF(x)
#else
#define FUNC(x)	LEAF(x)
#endif

/* Debug macro */
#ifdef TRACE
#undef TRACE
#endif
#ifdef BCMDBG
#define TRACE(x) \
	ldr	r9,=(x); \
	ldr     r10,=SI_ENUM_BASE; \
	str	r9,[r10,#0x64]
#else
#define TRACE(x)
#endif

#define envram_ofs	0x400

#if CFG_BIENDIAN
#define CFE_EPTSEAL_REV 0x31454643
#endif
#define CFE_EPTSEAL 0x43464531
#define cfe_command_restart 0

#endif /* _CFE_ */

#ifdef CFG_SHMOO
/* MMU table */
	.section section_mmu_table
page_table:
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	.word	0x00d04c06
	.word	0x00e04c06
	.word	0x00f04c06
	.word	0x01004c06 @DDR_SHMOO_RELATED_CHANGE: make 16MB-32MB area as L1 cacheable write-back mode requested by shmoo memory test
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	.word	0x01e04c06
	.word	0x01f04c06 
	.word	0x02004c06 @DDR_SHMOO_RELATED_CHANGE: make 32MB-128MB area as L1&L2 cacheable write-back mode requested by stress memory test
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	.word	0x07b04c06
	.word	0x07c04c06
	.word	0x07d04c06
	.word	0x07e04c06
	.word	0x07f04c06 @ DDR_SHMOO_RELATED_CHANGE: end of L1&L2 cacheable write-back mode
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	.word	0x1be02c02
	.word	0x1bf02c02
	.word	0x1c002c02   @ bcm95301x_svk_iproc_nand_config: make NAND flash code L1&L2 cachable
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	.word	0x1e004c02  @DDR_SHMOO_RELATED_CHANGE: change 0x1e014ca2 to 0x1e016caa to make flash code L1&L2 cachable   
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	.word	0xefe02c02
	.word	0xeff02c02
	.word	0xf0002c02
	.word	0xf0102c02
	.word	0xf0202c02
	.word	0xf0302c02
	.word	0xf0402c02
	.word	0xf0502c02
	.word	0xf0602c02
	.word	0xf0702c02
	.word	0xf0802c02
	.word	0xf0902c02
	.word	0xf0a02c02
	.word	0xf0b02c02
	.word	0xf0c02c02
	.word	0xf0d02c02
	.word	0xf0e02c02
	.word	0xf0f02c02
	.word	0xf1002c02
	.word	0xf1102c02
	.word	0xf1202c02
	.word	0xf1302c02
	.word	0xf1402c02
	.word	0xf1502c02
	.word	0xf1602c02
	.word	0xf1702c02
	.word	0xf1802c02
	.word	0xf1902c02
	.word	0xf1a02c02
	.word	0xf1b02c02
	.word	0xf1c02c02
	.word	0xf1d02c02
	.word	0xf1e02c02
	.word	0xf1f02c02
	.word	0xf2002c02
	.word	0xf2102c02
	.word	0xf2202c02
	.word	0xf2302c02
	.word	0xf2402c02
	.word	0xf2502c02
	.word	0xf2602c02
	.word	0xf2702c02
	.word	0xf2802c02
	.word	0xf2902c02
	.word	0xf2a02c02
	.word	0xf2b02c02
	.word	0xf2c02c02
	.word	0xf2d02c02
	.word	0xf2e02c02
	.word	0xf2f02c02
	.word	0xf3002c02
	.word	0xf3102c02
	.word	0xf3202c02
	.word	0xf3302c02
	.word	0xf3402c02
	.word	0xf3502c02
	.word	0xf3602c02
	.word	0xf3702c02
	.word	0xf3802c02
	.word	0xf3902c02
	.word	0xf3a02c02
	.word	0xf3b02c02
	.word	0xf3c02c02
	.word	0xf3d02c02
	.word	0xf3e02c02
	.word	0xf3f02c02
	.word	0xf4002c02
	.word	0xf4102c02
	.word	0xf4202c02
	.word	0xf4302c02
	.word	0xf4402c02
	.word	0xf4502c02
	.word	0xf4602c02
	.word	0xf4702c02
	.word	0xf4802c02
	.word	0xf4902c02
	.word	0xf4a02c02
	.word	0xf4b02c02
	.word	0xf4c02c02
	.word	0xf4d02c02
	.word	0xf4e02c02
	.word	0xf4f02c02
	.word	0xf5002c02
	.word	0xf5102c02
	.word	0xf5202c02
	.word	0xf5302c02
	.word	0xf5402c02
	.word	0xf5502c02
	.word	0xf5602c02
	.word	0xf5702c02
	.word	0xf5802c02
	.word	0xf5902c02
	.word	0xf5a02c02
	.word	0xf5b02c02
	.word	0xf5c02c02
	.word	0xf5d02c02
	.word	0xf5e02c02
	.word	0xf5f02c02
	.word	0xf6002c02
	.word	0xf6102c02
	.word	0xf6202c02
	.word	0xf6302c02
	.word	0xf6402c02
	.word	0xf6502c02
	.word	0xf6602c02
	.word	0xf6702c02
	.word	0xf6802c02
	.word	0xf6902c02
	.word	0xf6a02c02
	.word	0xf6b02c02
	.word	0xf6c02c02
	.word	0xf6d02c02
	.word	0xf6e02c02
	.word	0xf6f02c02
	.word	0xf7002c02
	.word	0xf7102c02
	.word	0xf7202c02
	.word	0xf7302c02
	.word	0xf7402c02
	.word	0xf7502c02
	.word	0xf7602c02
	.word	0xf7702c02
	.word	0xf7802c02
	.word	0xf7902c02
	.word	0xf7a02c02
	.word	0xf7b02c02
	.word	0xf7c02c02
	.word	0xf7d02c02
	.word	0xf7e02c02
	.word	0xf7f02c02
	.word	0xf8002c02
	.word	0xf8102c02
	.word	0xf8202c02
	.word	0xf8302c02
	.word	0xf8402c02
	.word	0xf8502c02
	.word	0xf8602c02
	.word	0xf8702c02
	.word	0xf8802c02
	.word	0xf8902c02
	.word	0xf8a02c02
	.word	0xf8b02c02
	.word	0xf8c02c02
	.word	0xf8d02c02
	.word	0xf8e02c02
	.word	0xf8f02c02
	.word	0xf9002c02
	.word	0xf9102c02
	.word	0xf9202c02
	.word	0xf9302c02
	.word	0xf9402c02
	.word	0xf9502c02
	.word	0xf9602c02
	.word	0xf9702c02
	.word	0xf9802c02
	.word	0xf9902c02
	.word	0xf9a02c02
	.word	0xf9b02c02
	.word	0xf9c02c02
	.word	0xf9d02c02
	.word	0xf9e02c02
	.word	0xf9f02c02
	.word	0xfa002c02
	.word	0xfa102c02
	.word	0xfa202c02
	.word	0xfa302c02
	.word	0xfa402c02
	.word	0xfa502c02
	.word	0xfa602c02
	.word	0xfa702c02
	.word	0xfa802c02
	.word	0xfa902c02
	.word	0xfaa02c02
	.word	0xfab02c02
	.word	0xfac02c02
	.word	0xfad02c02
	.word	0xfae02c02
	.word	0xfaf02c02
	.word	0xfb002c02
	.word	0xfb102c02
	.word	0xfb202c02
	.word	0xfb302c02
	.word	0xfb402c02
	.word	0xfb502c02
	.word	0xfb602c02
	.word	0xfb702c02
	.word	0xfb802c02
	.word	0xfb902c02
	.word	0xfba02c02
	.word	0xfbb02c02
	.word	0xfbc02c02
	.word	0xfbd02c02
	.word	0xfbe02c02
	.word	0xfbf02c02
	.word	0xfc002c02
	.word	0xfc102c02
	.word	0xfc202c02
	.word	0xfc302c02
	.word	0xfc402c02
	.word	0xfc502c02
	.word	0xfc602c02
	.word	0xfc702c02
	.word	0xfc802c02
	.word	0xfc902c02
	.word	0xfca02c02
	.word	0xfcb02c02
	.word	0xfcc02c02
	.word	0xfcd02c02
	.word	0xfce02c02
	.word	0xfcf02c02
	.word	0xfd002c02
	.word	0xfd102c02
	.word	0xfd202c02
	.word	0xfd302c02
	.word	0xfd402c02
	.word	0xfd502c02
	.word	0xfd602c02
	.word	0xfd702c02
	.word	0xfd802c02
	.word	0xfd902c02
	.word	0xfda02c02
	.word	0xfdb02c02
	.word	0xfdc02c02
	.word	0xfdd02c02
	.word	0xfde02c02
	.word	0xfdf02c02
	.word	0xfe002c02
	.word	0xfe102c02
	.word	0xfe202c02
	.word	0xfe302c02
	.word	0xfe402c02
	.word	0xfe502c02
	.word	0xfe602c02
	.word	0xfe702c02
	.word	0xfe802c02
	.word	0xfe902c02
	.word	0xfea02c02
	.word	0xfeb02c02
	.word	0xfec02c02
	.word	0xfed02c02
	.word	0xfee02c02
	.word	0xfef02c02
	.word	0xff002c02
	.word	0xff102c02
	.word	0xff202c02
	.word	0xff302c02
	.word	0xff402c02
	.word	0xff502c02
	.word	0xff602c02
	.word	0xff702c02
	.word	0xff802c02
	.word	0xff902c02
	.word	0xffa02c02
	.word	0xffb02c02
	.word	0xffc02c02
	.word	0xffd02c02
	.word	0xffe02c02
	.word	0xfff02c02
#endif /* CFG_SHMOO */

/* Entry point */
	.section .text.startup

	.globl startup
startup:
	b	tr_rst	/* 0 - reset */
	ldr	pc,_tr_und	/* 4 - undefined instruction */
	ldr	pc,_tr_swi	/* 8 - software interrupt */
	ldr	pc,_tr_iab	/* 0xc - prefetch abort */
	ldr	pc,_tr_dab	/* 0x10 - data abort */
	ldr	pc,_tr_bad	/* 0x14 - reserved */
	ldr	pc,_tr_irq	/* 0x18 - external interrupt */
	ldr	pc,_tr_fiq	/* 0x1c - fast interrupt */

_tr_und:
	.word tr_und
_tr_swi:
	.word tr_swi
_tr_iab:
	.word tr_iab
_tr_dab:
	.word tr_dab
_tr_bad:
	.word tr_bad
_tr_irq:
	.word tr_irq
_tr_fiq:
	.word tr_fiq
_pad:
	.word 0x12345678 /* now 16*4=64 */

	.org	(BISZ_OFFSET-4)
_ddrclk:
	.word	0x0
	/* Record the size of the binary */
	.org	BISZ_OFFSET

	.word	BISZ_MAGIC
	.word	text_start
	.word	text_end
	.word	data_start
	.word	data_end
	.word	bss_start
	.word	bss_end
	.word	_end

	.balign envram_ofs
	/* Embedded NVRAM */
	.global	embedded_nvram
embedded_nvram:
	.fill	0x400,4,~0x48534C46	/* 'FLSH' */
        .long   0x4c5a4d41              /* LZMA NVRAM Supported */

#ifdef _CFE_
#if CFG_EMBEDDED_PIC
#define RUNTIME_RELOC_START	__runtime_reloc_start
#define RUNTIME_RELOC_STOP	__runtime_reloc_stop
#else
#define RUNTIME_RELOC_START	0
#define RUNTIME_RELOC_STOP	0
#endif

#include "segtable.h"

	.globl segment_table
segment_table:
	.word	text_end			/* [  0] End of text (R_SEG_ETEXT) */
	.word	data_start			/* [  1] Beginning of data (R_SEG_FDATA) */
	.word	data_end			/* [  2] End of data (R_SEG_EDATA) */
	.word	_end				/* [  3] End of BSS (R_SEG_END) */
	.word	text_start			/* [  4] Beginning of text (R_SEG_FTEXT) */
	.word	bss_start			/* [  5] Beginning of BSS (R_SEG_FBSS) */
	.word	0					/* [  6] Global Pointer (R_SEG_GP) */
	.word	RUNTIME_RELOC_START	/* [  7] Beginning of reloc entries */
	.word	RUNTIME_RELOC_STOP	/* [  8] End of reloc entries */
	.word	0					/* [  9] R_SEG_APIENTRY */
#endif /* __CFE_ */

/*************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************/

/*
 * the actual reset code
 */
tr_rst:
	mrs	r0,cpsr
	mov	r1,#(PS_MM)
	bic	r0,r0,r1
	/* Switch to system mode and make sure interrupts are disabled */
	mov 	r1,#(PS_I | PS_F | PS_SYS)
	orr	r0,r0,r1
	msr	cpsr,r0
initcpu:
	mov	r0,#0

	/* Initialize cp15 registers */
	mcr	p15,0,r0,c5,c0,0		/* DFSR */
	mcr	p15,0,r0,c5,c0,1		/* IFSR */
	mcr	p15,0,r0,c6,c0,0		/* DFAR */
	mcr	p15,0,r0,c6,c0,1		/* WFSR */

	/* Initialize system control register */
	mrc	p15,0,r1,c1,c0,0
	bic	r1,r1,#0x7			/* Clear C, A, M bits */
	bic	r1,r1,#(0x1 << 12)		/* Clear I bit */
	orr	r1,r1,#0x2000			/* Set V bit: high vectors (0xffff0000) */
	orr	r1,r1,#0x2			/* Set A bit: enable strict alignment */
	mcr	p15,0,r1,c1,c0,0

	mcr	p15,0,r0,c8,c7,0		/* Invalidate TLB */
	mcr	p15,0,r0,c7,c5,0		/* Invalidate icache */
	mcr	p15,0,r0,c7,c5,6		/* Invalidate BTAC */
	mcr	p15,0,r0,c7,c10,4		/* DSB */
	mcr	p15,0,r0,c7,c5,4		/* ISB */

	/* Identify current CPU */
	mrc	p15,0,r0,c0,c0,5
	and	r0,r0,#0xf			/* retrieve cpu core id */
	cmp	r0,#0				/* cpu core 0? */
	beq	check_startaddr

	/* Changed the jump address for core 1 */
	ldr	r0,=0xffff002c			/* This address contains a wfe instruction */
	ldr	r1,=0xffff0000			/* SKU ROM starting address */
	str	r0, [r1, #0x400]

	ldr	pc,=0xffff002c			/* Go back to SKU ROM, waiting kernel SMP */

check_startaddr:
	adrl	r0,startup		/* r0: source start address */
	ldr	r1,=startup		/* r1: target address */
	cmp	r0,r1
	beq	szmem

	/* Wake up core 1 */
	mov	r0,#0
	mcr 	p15,0,r0,c7,c10,4
	sev	

enable_cache:
	/* Enable I cache */
	mrc	p15,0,r1,c1,c0,0
	orr	r1,r1,#0x1800			/* Enable I$ and branch prediction */
	mcr	p15,0,r1,c1,c0,0
	
#ifdef CFG_SHMOO
	/* Invalidate data cache */
	bl	cpu_inv_dcache_all

	/* Enable D cache */
	mcr	p15,0,r0,c7,c10,4		/* DSB */
	mrc	p15,0,r1,c1,c0,0
	orr	r1,r1,#0x4
	mcr	p15,0,r1,c1,c0,0
	mcr	p15,0,r0,c7,c5,4		/* ISB */

	/* Invalidate TLB */
	mcr	p15,0,r0,c8,c7,0

scu_enable:
	ldr	r1,=IHOST_SCU_INVALIDATE
	mov	r2,#0xff
	str	r2,[r1]
	ldr	r1,=IHOST_SCU_CONTROL
	ldr	r2,[r1]
	orr	r2,r2,#0x1
	str	r2,[r1]
mmu_init:
	ldr	r1,=startup
	ldr	r2,=page_table
	sub	r2,r2,r1
	adrl	r1,startup
	add	r1,r1,r2

	/* Configure translation table base (TTB) control register cp15,c2
	 * to a value of all zeros, indicates we are using TTB register 0
	 */
	mov	r0,#0
	mcr	p15,0,r0,c2,c0,2
	/* Load page table address to cp15 */
	mcr	p15,0,r1,c2,c0,0
	/* Set the access control to client */
	ldr	r1,=0xffffffff
	mcr	p15,0,r1,c3,c0,0
	/* Enable MMU */
	mrc	p15,0,r1,c1,c0,0
	orr	r1,r1,#0x1
	mcr	p15,0,r1,c1,c0,0
	mcr	p15,0,r0,c7,c5,4		/* ISB */

l2cc_init:
	ldr	r1,=SI_ENUM_BASE
	ldr	r2,=CC_CHIPID
	ldr	r2,[r1,r2]
	ldr	r1,=CID_ID_MASK
	and	r2,r2,r1
	ldr	r1,=0xcf12	/* NS Ax/Bx */
	cmp	r2,r1
	beq	l2cc_256k
	ldr	r1,=0xcf26	/* NS 47094 */
	cmp	r2,r1
	beq	l2cc_256k
	ldr	r1,=0xcf19
	cmp	r2,r1
	bge	l2cc_512k
l2cc_256k:
	ldr	r1,=0x0a130000
	ldr	r4,=0x111
	b	l2cc_inv
l2cc_512k:
	ldr	r1,=0x0a150000
	ldr	r4,=0x131
l2cc_inv:
	ldr	r2,=IHOST_L2C_CACHE_ID
	ldr	r3,[r2,#0x104]
	bic	r3,r3,#0x000f0000
	orr	r3,r3,r1
	str	r3,[r2,#0x104]
	ldr	r1,=0x0
	str	r1,[r2,#0x108]
	str	r4,[r2,#0x10c]
	ldr	r1,=0xffff
	str	r1,[r2,#0x77c]
test_inv_way:
	ldr	r1,[r2,#0x77c]
	cmp	r1,r0
	bne	test_inv_way

	ldr	r1,=0x1ff
	str	r1,[r2,#0x220]			/* int_clear */
	mov	r1,#0x1
	str	r1,[r2,#0x100]			/* control */
	mcr	p15,0,r0,c7,c10,4		/* DSB */
	mcr	p15,0,r0,c7,c5,4		/* ISB */

l2cc_lockdown:
	ldr	r1,=0xc0000000
	ldr	r2,=0xc0020000			/* 128KB */
	ldr	r4,=0xa5a5a5a5
	ldr	r5,=0xa5a5a5a5
	ldr	r6,=0xa5a5a5a5
	ldr	r7,=0xa5a5a5a5
	ldr	r8,=0xa5a5a5a5
	ldr	r9,=0xa5a5a5a5
	ldr	r10,=0xa5a5a5a5
	ldr	r11,=0xa5a5a5a5
	/* Enable lockdown by line */
	mov	r3,#0x01
	ldr	r0,=IHOST_L2C_CACHE_ID
	str	r3,[r0,#0x950]
1:
	stmia	r1!,{r4-r11}
	ldr	r3,=0x10
cdelay1:
	sub	r3,r3,#1
	cmp	r3,#0
	bne	cdelay1
	cmp	r1,r2
	bne	1b

	/* Disable lockdown by line */
	mov	r3,#0
	ldr	r0,=IHOST_L2C_CACHE_ID
	str	r3,[r0,#0x950]		
l2cc_init_done:
#endif /* CFG_SHMOO */

	/* BCM4708 WAR for PCIE2 */
	ldr	r0,=0x1a000000
	ldr	r1,=0x0
	str	r1,[r0]
	ldr	r0,=0x18130e04
	ldr	r1,=0x0
	str	r1,[r0]
	ldr	r0,=0x18130e00
	ldr	r1,=0x1
	str	r1,[r0]
	
init_pcie:
	ldr	r0,=SI_ENUM_BASE		/* r0:	core regs SI base address */
	ldr	r1,=CC_EROMPTR
	ldr	r1,[r0,r1]			/* r1:	erom pointer */
1:	ldr	r2,[r1]				/* r2:	erom entry */
	ldr	r3,=(ER_TAG | ER_VALID)
	and	r3,r3,r2
	cmp	r3,#(ER_END | ER_VALID)		/* Is this the END marker? */
	beq	no_pcie				/* Yes: done and did not find pcie */

	cmp	r3,#(ER_CI | ER_VALID)
	beq	2f

	add	r1,r1,#4			/* Next erom entry */
	b	1b

no_pcie:
	b	find_bootdev
	
	/* Found a CIA */
2:	add	r1,r1,#8			/* Skip both CIA & CIB */
	ldr	r3,=CIA_CID_MASK
	and	r3,r3,r2
	ldr	r4,=(NS_PCIEG2_CORE_ID << CIA_CID_SHIFT)
	cmp	r3,r4
	bne	1b

	/* Found pcie, get regs and wrapper and save them */
	bl	ai_get_slave
	mov	r8,r0
	bl	ai_get_wrapper
	mov	r9,r0
	
	/* Initialize memory controller and size memory */
	mov	r0,r8
	mov	r1,r9
	bl	pcie_init
	bl	pcie_phy_init

find_bootdev:
	ldr	r0,=SI_ENUM_BASE		/* r0:	core regs SI base address */
	ldr	r1,=CC_EROMPTR
	ldr	r1,[r0,r1]			/* r1:	erom pointer */
1:	ldr	r2,[r1]				/* r2:	erom entry */
	ldr	r3,=(ER_TAG | ER_VALID)
	and	r3,r3,r2
	cmp	r3,#(ER_END | ER_VALID)		/* Is this the END marker? */
	beq	no_socrom_core			/* Yes: done and did not find rom core */

	cmp	r3,#(ER_CI | ER_VALID)
	beq	2f

	add	r1,r1,#4			/* Next erom entry */
	b	1b

no_socrom_core:
	b	init_ddr
	
	/* Found a CIA */
2:	add	r1,r1,#8			/* Skip both CIA & CIB */
	ldr	r3,=CIA_CID_MASK
	and	r3,r3,r2
	ldr	r4,=(NS_ROM_CORE_ID << CIA_CID_SHIFT)
	cmp	r3,r4
	bne	1b
	
	/* Found socrom, get regs and wrapper and save them */
	bl	ai_get_wrapper
	ldr	r1,[r0,#AI_IOSTATUS]
	ldr	r2,=SISF_NS_BOOTDEV_MASK
	and	r1,r1,r2
	mov	r7,r1
	ldr	r0,=SISF_NS_BOOTDEV_OFFLOAD
	cmp	r1,r0
	bne	init_ddr

offload_mode:
	ldr	r4,=0x1
	ldr	r5,=0xffff042c
	str	r4,[r5]
	ldr	r4,=0x0
	ldr	r5,=0xffff0430
wait_for_host:
	ldr	r6,[r5]
	cmp	r6,r4
	beq	wait_for_host
	bx	r6	

/*
 * Find ddr core
 */
init_ddr:
#ifdef CFG_SHMOO
	/* Copy to cache */
copy2cache:
	adrl	r0,startup		/* r0: source start address */
	ldr	r1,=startup		/* r1: target address */
	cmp	r0,r1
	beq	l2c_clear_bss
	ldr	r3,_bss_start_ofs
	add	r2,r0,r3		/* r2: source end address */
l2c_copy_loop:
	ldmia	r0!,{r9-r10}		/* copy from source address [r0] */
	stmia	r1!,{r9-r10}		/* copy to   target address [r1] */
	cmp	r0,r2			/* until source end address [r2] */
	blo	l2c_copy_loop

	/* Clear BSS */
l2c_clear_bss:
	ldr	r0,_bss_start_ofs
	ldr	r1,_bss_end_ofs
	ldr	r4,=startup
	add	r0,r0,r4
	add	r1,r1,r4
	mov	r2,#0x00000000
	/* empty bss section checking */
	cmp	r0,r1
	beq	enable_arm_cyclecount

l2c_clbss_l:
	str	r2,[r0]
	add	r0,r0,#4
	cmp	r0,r1
	bne	l2c_clbss_l

/* Cycle Count */
enable_arm_cyclecount:
	mrc	p15,0,r1,c9,c12,0
	ldr	r2,=1
	orr	r1,r1,r2
	mcr	p15,0,r1,c9,c12,0	/* Set enable bit in PMNC */
	ldr	r1,=0x80000000
	mcr	p15,0,r1,c9,c12,1

	/* setup stack pointer */
	ldr	r0,=0xc0000000
	ldr	r1,=0x20000			/* 128KB */
	add	r0,r0,r1
	sub	r0,r0,#8
	mov	sp,r0
	bic	sp,sp,#7
	ldr	r0,_c_ddr_init_ofs
	ldr	r1,=startup
	add	lr,r1,r0
	ldr	r0,_c_ddr_init_done_ofs
	adrl	r1,startup
	add	r0,r1,r0
	mov	pc,lr
c_ddr_init_done:
#else	/* CFG_SHMOO */
	ldr	r0,=SI_ENUM_BASE		/* r0:	core regs SI base address */
	ldr	r1,=CC_EROMPTR
	ldr	r1,[r0,r1]			/* r1:	erom pointer */
1:	ldr	r2,[r1]				/* r2:	erom entry */
	ldr	r3,=(ER_TAG | ER_VALID)
	and	r3,r3,r2
	cmp	r3,#(ER_END | ER_VALID)		/* Is this the END marker? */
	beq	panic				/* Yes: done and did not find ddr */

	cmp	r3,#(ER_CI | ER_VALID)
	beq	2f

	add	r1,r1,#4			/* Next erom entry */
	b	1b

panic:	b	.
	
	/* Found a CIA */
2:	add	r1,r1,#8			/* Skip both CIA & CIB */
	ldr	r3,=CIA_CID_MASK
	and	r3,r3,r2
	ldr	r4,=(NS_DDR23_CORE_ID << CIA_CID_SHIFT)
	cmp	r3,r4
	bne	1b

	/* Found ddr, get regs and wrapper and save them */
	bl	ai_get_slave
	mov	r8,r0
	bl	ai_get_wrapper
	mov	r9,r0
	
	/* Initialize memory controller and size memory */
	mov	r0,r8
	mov	r1,r9
	mov	r2,r7			/* boot_dev */

	bl	ddr_init
#endif  /* CFG_SHMOO */

szmem:
	ldr	r3,=0x80000000
	ldr	r2,=0xaa55beef
	ldr	r1,=0x00000000
	str	r1,[r3,#0x3c]
	ldr	r0,=(1 << 20)
	ldr	r5,=(1 << 30)
1:
	ldr	r4,=0x80000000
	add	r4,r4,r0
	str	r2,[r4,#0x3c]
	ldr	r1,[r4,#0x3c]			/* Read back to ensure completion */
	ldr	r1,[r3,#0x3c]
	cmp	r1,r2
	beq	2f

	lsl	r0,r0,#1
	cmp	r0,r5
	bne	1b

	/* Didn't find an alias, must be 128MB */
2:
	mov	r8,r0			/* r8: the memory size in bytes */

/* Do CRU configure after DDR initied */
#if !defined(CFG_ROMBOOT)
set_cru_policy7:
	ldr	r0,=IHOST_PROC_CLK_WR_ACCESS
	ldr	r1,=0xa5a501
	str	r1,[r0]
	
	ldr	r3,=SI_ENUM_BASE
	ldr	r4,=CC_CHIPID
	ldr	r4,[r3,r4]
	ldr	r3,=CID_PKG_MASK
	and	r4,r4,r3
	lsr	r3,r4,#CID_PKG_SHIFT

	cmp	r3,#0
	beq	cpu_1g
	ldr	r1,=0x1004001		/* 800MHz */
	b	set_clocks
	
cpu_1g:
	ldr	r1,=0x1005001		/* 1GHz */ 
	b	set_clocks

set_clocks:	
	ldr	r0,=IHOST_PROC_CLK_PLLARMA
	str	r1,[r0]
	ldr	r2,=0x0
	
	ldr	r4,=0x100000
poll_plllock:
	cmp	r4,r2
	beq	poll_plllock_done
	sub	r4,r4,#1
	ldr	r1,[r0]
	and	r3,r1,#(1 << IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK)
	cmp	r3,r2
	beq	poll_plllock
poll_plllock_done:
	orr	r1,r1,#(1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB)
	str	r1,[r0]
	ldr	r0,=IHOST_PROC_CLK_POLICY_FREQ
	ldr	r1,=0x87070707
	str	r1,[r0]
	ldr	r0,=IHOST_PROC_CLK_CORE0_CLKGATE
	ldr	r1,=0x00010303
	str	r1,[r0]
	ldr	r0,=IHOST_PROC_CLK_CORE1_CLKGATE
	ldr	r2,=0x00000303
	str	r2,[r0]
	ldr	r0,=IHOST_PROC_CLK_ARM_SWITCH_CLKGATE
	str	r1,[r0]
	ldr	r0,=IHOST_PROC_CLK_ARM_PERIPH_CLKGATE
	str	r1,[r0]
	ldr	r0,=IHOST_PROC_CLK_APB0_CLKGATE
	str	r1,[r0]

	ldr	r0,=IHOST_PROC_CLK_POLICY_CTL
	ldr	r2,=(1 << IHOST_PROC_CLK_POLICY_CTL__GO)
	ldr	r3,=(1 << IHOST_PROC_CLK_POLICY_CTL__GO_AC)
	orr	r3,r3,r2
	str	r3,[r0]
	ldr	r3,=0x0
	ldr	r4,=0x100000
poll_ccu:
	cmp	r4,r3
	beq	poll_ccu_done
	sub	r4,r4,#1
	ldr	r1,[r0]
	and	r1,r1,r2
	cmp	r1,r3
	bne	poll_ccu
poll_ccu_done:
#endif /* !defined(CFG_ROMBOOT) */

#ifndef CFG_SHMOO
        /* Copy to RAM */
copy2ram:
	adrl	r0,startup		/* r0: source start address */
	ldr	r1,=startup		/* r1: target address */
	cmp	r0,r1
	beq	clear_bss
	ldr	r3,_bss_start_ofs
	add	r2,r0,r3		/* r2: source end address */
copy_loop:
	ldmia	r0!,{r9-r10}		/* copy from source address [r0] */
	stmia	r1!,{r9-r10}		/* copy to   target address [r1] */
	cmp	r0,r2			/* until source end address [r2] */
	blo	copy_loop

	/* Clear BSS */
clear_bss:
	ldr	r0,_bss_start_ofs
	ldr	r1,_bss_end_ofs
	ldr	r4,=startup
	add	r0,r0,r4
	add	r1,r1,r4
	mov	r2,#0x00000000
	/* empty bss section checking */
	cmp	r0,r1
	beq	enable_arm_cyclecount

clbss_l:
	str	r2,[r0]
	add	r0,r0,#4
	cmp	r0,r1
	bne	clbss_l

/* Cycle Count */
enable_arm_cyclecount:
	mrc	p15,0,r1,c9,c12,0
	ldr	r2,=1
	orr	r1,r1,r2
	mcr	p15,0,r1,c9,c12,0	/* Set enable bit in PMNC */
	ldr	r1,=0x80000000
	mcr	p15,0,r1,c9,c12,1
#endif /* !CFG_SHMOO */
/* Set stackpointer in internal RAM to call c_main */
call_c_main:
	/* Save memory size in bytes */
	mov	r0,r8
	cmp	r0,#(128<<20)
	ble	1f
	mov	r0,#(128<<20)
1:
	ldr	r1,=_memsize
	str r0,[r1]

#ifdef _CFE_
	_LSR_ r8,r8,#10			/* memory size in Kbytes */
	ldr	r1,=mem_totalsize
	str	r8,[r1]

	/* not relocating, no offset */
	ldr	r0,=0
	ldr	r1,=mem_datareloc
	str	r0,[r1]
	ldr	r1,=mem_textreloc
	str	r0,[r1]

	ldr r0,_text_start_ofs
	add	r0,r0,r4
	ldr	r1,=mem_bottomofmem
	str	r0,[r1]

	ldr	r0,__end_ofs
	add	r0,r0,r4
	ldr	r1,=mem_heapstart
	str	r0,[r1]

	add	r0,#(CFG_HEAP_SIZE*1024)
	add	r0,#STACK_SIZE
	ldr	r1,=mem_topofmem
	str	r0,[r1]

	ldr	r0,_text_start_ofs
	add	r0,r0,r4
	ldr	r2,_text_end_ofs
	add	r2,r2,r4
	sub	r2,r2,r0
	ldr	r1,=mem_textsize
	str	r2,[r1]
	ldr	r1,=mem_textbase
	str	r0,[r1]

	ldr	r0,=0x00000000
	ldr	r1,=cpu_prid
	str	r0,[r1]

	/* Set the segment_table */
	/* text_end */
	ldr	r0,_text_end_ofs
	add	r0,r0,r4
	ldr	r1,=segment_table
	str	r0,[r1]

	/* data_start */
	ldr	r0,_data_start_ofs
	add	r0,r0,r4
	add	r1,r1,#4
	str	r0,[r1]

	/* data_end */
	ldr	r0,_data_end_ofs
	add	r0,r0,r4
	add	r1,r1,#4
	str	r0,[r1]

	/* _end */
	ldr	r0,__end_ofs
	add	r0,r0,r4
	add	r1,r1,#4
	str	r0,[r1]

	/* text_start */
	ldr	r0,_text_start_ofs
	add	r0,r0,r4
	add	r1,r1,#4
	str	r0,[r1]

	/* bss_start */
	ldr	r0,_bss_start_ofs
	add	r0,r0,r4
	add	r1,r1,#4
	str	r0,[r1]

	/* _gp (0) */
	mov	r0,#0
	add	r1,r1,#4
	str	r0,[r1]

	/* RUNTIME_RELOC_START (0) */
	mov	r0,#0
	add	r1,r1,#4
	str	r0,[r1]

	/* RUNTIME_RELOC_STOP (0) */
	mov	r0,#0
	add	r1,r1,#4
	str	r0,[r1]

	/* cpu_apientry (0) */
	mov	r0,#0
	add	r1,r1,#4
	str	r0,[r1]

	ldr	r1,=mem_topofmem
#else /* !_CFE_ */
	ldr	r1,=_memsize
#endif /* _CFE_ */

	ldr	r0,[r1]
	sub	r0,r0,#8
	mov	sp,r0
	bic	sp,sp,#7		/* 8-byte alignment for ABI compliance */

	ldr	r0,_c_main_ofs
	ldr	r1,=startup
	add	lr, r0, r1
	/* setup parameters for c_main */
#ifdef _CFE_
	/* CFE: clear argument a & b in cfe_main */
	ldr	r0,=0x00000000
	ldr	r1,=0x00000000
#else
	/* CFEZ: set return addr to argment ra */
	ldr	r0,_theend_ofs
	add	r0,r0,r2
#endif
	/* jump to it ... */
	mov	pc,lr

/* In case c_main returns */
theend:
	TRACE(0x424feedd)
	wfe
	b	theend


/*
 * These are defined in the board-specific linker script.
 */

#ifdef _CFE_
.globl _text_start_ofs
_text_start_ofs:
	.word text_start - startup

.globl _text_end_ofs
_text_end_ofs:
	.word text_end - startup

.globl _data_start_ofs
_data_start_ofs:
	.word data_start - startup

.globl _data_end_ofs
_data_end_ofs:
	.word data_end - startup

.globl __end_ofs
__end_ofs:
	.word _end - startup
#endif /* _CFE_ */

.globl _bss_start_ofs
_bss_start_ofs:
	.word bss_start - startup

.globl _bss_end_ofs
_bss_end_ofs:
	.word bss_end - startup

#ifdef CFG_SHMOO
_c_ddr_init_ofs:
	.word c_ddr_init - startup

_c_ddr_init_done_ofs:
	.word c_ddr_init_done - startup
#endif /* CFG_SHMOO */

_c_main_ofs:
	.word c_main - startup

_theend_ofs:
	.word theend - startup

/* Init PCIE mappings */
FUNC(pcie_init)
	ldr	r5,=REG_BAR2_CONFIG_F0
	str	r5,[r0,#PAXB_INDR_ADDR]
	ldr	r3,[r0,#PAXB_INDR_DATA]
	and	r3,r3,#0xfffffff0
	orr	r3,r3,#0xc
	str	r3,[r0,#PAXB_INDR_DATA]

	ldr	r3,[r0,#PAXB_IARR_1_LOWER]
	and	r3,r3,#0xffffff00
	orr	r3,r3,#0x80
	str	r3,[r0,#PAXB_IARR_1_LOWER]
	ldr	r3,=0x40000000
	str	r3,[r0,#PAXB_IARR_1_UPPER]
	
	ldr	r3,=0x00000001
	str	r3,[r0,#PAXB_FUNC0_IMAP1]
	bx	lr
END(pcie_init)

/*
 * Find the first slave address for a core in the AI EROM
 * Input:
 *	r1 - pointer to EROM after CIB
 * Output:
 *	r0 - slave address
 * Changed:
 *	r0, r1, r2
 */
FUNC(ai_get_slave)
1:	ldr	r0,[r1]
	ldr	r2,=(ER_TAG | ER_VALID)
	add	r1,r1,#4			/* Next erom entry */
	and	r2,r2,r0
	cmp	r2,#(ER_ADD | ER_VALID)
	bne	1b

2:	ldr	r2,=AD_ADDR_MASK
	and	r0,r0,r2
	bx	lr
END(ai_get_slave)


/*
 * Find the first wrapper address for a core in the AI EROM
 * Input:
 *	r1 - pointer to EROM after first slave ADD
 * Output:
 *	r0 - wrapper address
 * Changed:
 *	r0, r1, r2, r3
 */
FUNC(ai_get_wrapper)
1:	ldr	r0,[r1]
	ldr	r2,=(ER_TAG | ER_VALID)
	add	r1,r1,#4			/* Next erom entry */
	and	r2,r2,r0
	cmp	r2,#(ER_ADD | ER_VALID)
	bne	1b

	/* An address descriptor, is it a wrapper? */
	ldr	r2,=AD_ST_SWRAP			/* We test just for the SWRAP bit set, */
	tst	r0,r2				/*  that gets both Master and Slave */
	beq	1b				/*  wrappers. */

	/* It is, isolate address and return */
	ldr	r2,=AD_ADDR_MASK
	and	r0,r0,r2
	bx	lr
END(ai_get_wrapper)


/* Interrupt handlers */
/* Note: hndrte_arm.c for EXT_CBALL expects each trap handler to be 16 bytes */
LEAF(__traps)

/* Undefined instruction exception handler */
tr_und:
	srsdb	sp!, #PS_SYS	/* use system mode stack */
	cps	#PS_SYS		

	/* now cr4 is in system mode */
	/* lr has the value before the exception, push it to stack */
	push 	{r0}	/* hold the place for r15 */
	push	{lr}
	sub	sp,sp,#24	/* skip r8-r13 now */
	push 	{r0-r7}	/* save r0-r7 to the stack */
	eor	r0,r0,r0
	add	r0,r0,#TR_UND
	b	trap

/* Software interrupt exception handler */
tr_swi:
	srsdb	sp!, #PS_SYS	/* use system mode stack */
	cps	#PS_SYS

	push 	{r0}	/* hold the place for r15 */
	push	{lr}
	sub	sp,sp,#24	/* skip r8-r13 now */
	push 	{r0-r7}
	eor	r0,r0,r0
	add	r0,r0,#TR_SWI
	b	trap

/* Prefetch abort exception handler */
tr_iab:
	/* adjust lr to the address of abort insturction fetch */
	mov 	sp,lr
	sub	sp,sp,#4
	mov 	lr,sp
	srsdb	sp!, #PS_SYS	/* use system mode stack */
	cps	#PS_SYS

	push 	{r0}	/* hold the place for r15 */
	push	{lr}
	sub	sp,sp,#24	/* skip r8-r13 now */
	push 	{r0-r7}
	eor	r0,r0,r0
	add	r0,r0,#TR_IAB
	b	trap

/* Data abort exception handler */
tr_dab:
	/* adjust lr to the address of aborted data fetch */
	mov 	sp,lr
	sub	sp,sp,#8
	mov 	lr,sp
	srsdb	sp!, #PS_SYS	/* use system mode stack */
	cps	#PS_SYS	

	push 	{r0}	/* hold the place for r15 */
	push	{lr}
	sub	sp,sp,#24	/* skip r8-r13 now */
	push 	{r0-r7}
	eor	r0,r0,r0
	add	r0,r0,#TR_DAB
	b	trap

tr_bad: /* reserved */
	mov 	sp,lr
	sub	sp,sp,#4
	mov 	lr,sp
	srsdb	sp!, #PS_SYS	/* use system mode stack */
	cps	#PS_SYS

	push 	{r0}	/* hold the place for r15 */
	push	{lr}
	sub	sp,sp,#24	/* skip r8-r13 now */
	push 	{r0-r7}
	eor	r0,r0,r0
	add	r0,r0,#TR_BAD
	b	trap

/* Interrupt handler */
tr_irq:
	/* subtract the offset */
	mov 	sp,lr
	sub	sp,sp,#4
	mov 	lr,sp
	srsdb	sp!, #PS_SYS	/* use system mode stack */
	cps	#PS_SYS

	push 	{r0}	/* hold the place for r15 */
	push	{lr}
	sub	sp,sp,#24	/* skip r8-r13 now */
	push 	{r0-r7}
	eor	r0,r0,r0
	add	r0,r0,#TR_IRQ
	b	trap


/* Fast interrupt handler */
tr_fiq:
	mov 	sp,lr
	sub	sp,sp,#4
	mov 	lr,sp
	srsdb	sp!, #PS_SYS	/* use system mode stack */
	cps	#PS_SYS

	push 	{r0}	/* hold the place for r15 */
	push	{lr}
	sub	sp,sp,#24	/* skip r8-r13 now */
	push 	{r0-r7}
	eor	r0,r0,r0
	add	r0,r0,#TR_FIQ
	b	trap

/* Generic exception handler */
trap:
	/*
	 * construt the trap structure in system mode stack 
	*/
	/* save trap type, epc, cpsr and spsr */
	mov 	r4, sp	/* sp is now at r0 */
	add	r4,r4,#64
	ldmia	r4!, {r1,r3} /* r1<-epc, r3<-spsr */
	mrs	r2, cpsr
	push	{r0,r1,r2,r3}	/* trap type(r0), epc(r1), cpsr,spsr */

	/* fix the value of pc in trap structure */
	sub	r4,r4,#12
	str	r1,[r4]	/* save the value or epc as r15 into the stack */ 
	
	/* save r8 - r13 */
	mov 	r7,sp	/* sp is at the being of the trap structure now */
	add	r7,r7,#TRAP_T_SIZE + 8	/* sp value before the exception */
	mov 	r6,r12
	mov	r5,r11
	mov	r4,r10
	mov	r3,r9
	mov	r2,r8
	add	sp,sp,#72 /* move sp to r14 */
	push	{r2-r7}	/* save r8-r13 to stack */		

	sub	sp,sp,#48 /* move sp back to the top of trap structure */	

	/* If trap_hook is null, go to the end */
	ldr	r4,=trap_hook
	ldr	r4,[r4]
	cmp	r4,#0
1:	beq	1b
	/* else call (*trap_hook)(trap_t) */
	mov	r0,sp
	blx	r4

/* Restore the state from the trap_t */
rfe:	
	/* pop r8-r14 */
	add	sp,sp,#48
	pop	{r0-r6} /* r8 - r14 */
	mov	r8,r0
	mov	r9,r1
	mov	r10,r2
	mov	r11,r3
	mov	r12,r4
	mov	lr,r6	/* restore lr */

	sub	sp,sp,#60 /* move sp to point to r0 */
	pop	{r0-r7}

	/* move sp to point to epc and spsr saved by srs */
	add	sp,sp,#32

	/* Restore cpsr, sp and return */
	rfeia	sp!	/* done! */
END(__traps)

FUNC(_getticks)
	mrc	p15,0,r0,c9,c13,0
	bx	lr
END(_getticks)

/* Flush the whole D-cache */
cpu_flush_dcache_all:
	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
	ands	r3, r0, #0x7000000		@ extract loc from clidr
	mov	r3, r3, lsr #23			@ left align loc bit field
	beq	finished			@ if loc is 0, then no need to clean
	mov	r10, #0				@ start clean at cache level 0
loop1:
	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
	and	r1, r1, #7			@ mask of the bits for current cache only
	cmp	r1, #2				@ see what cache we have at this level
	blt	skip				@ skip if no cache, or just i-cache
	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
						@ with armv7 this is 'isb',
						@ but we compile with armv5
	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
	and	r2, r1, #7			@ extract the length of the cache lines
	add	r2, r2, #4			@ add 4 (line length offset)
	ldr	r4, =0x3ff
	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
	clz	r5, r4				@ find bit position of way size increment
	ldr	r7, =0x7fff
	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
loop2:
	mov	r9, r4				@ create working copy of max way size
loop3:
	orr	r11, r10, r9, lsl r5		@ factor way and cache number into r11
	orr	r11, r11, r7, lsl r2		@ factor index number into r11
	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
	subs	r9, r9, #1			@ decrement the way
	bge	loop3
	subs	r7, r7, #1			@ decrement the index
	bge	loop2
skip:
	add	r10, r10, #2			@ increment cache number
	cmp	r3, r10
	bgt	loop1
finished:
	mov	r10, #0				@ swith back to cache level 0
	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
						@ with armv7 this is 'isb',
						@ but we compile with armv5
	mov	pc, lr

FUNC(cpu_flush_cache_all)
	stmfd	sp!, {r0-r7, r9-r11, lr}
	bl	cpu_flush_dcache_all
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
	ldmfd	sp!, {r0-r7, r9-r11, lr}
	mov	pc, lr
END(cpu_flush_cache_all)

/* Invalidate the whole D-cache */
cpu_inv_dcache_all:
	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
	ands	r3, r0, #0x7000000		@ extract loc from clidr
	mov	r3, r3, lsr #23			@ left align loc bit field
	beq	invfinished			@ if loc is 0, then no need to clean
	mov	r10, #0				@ start clean at cache level 0
invloop1:
	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
	and	r1, r1, #7			@ mask of the bits for current cache only
	cmp	r1, #2				@ see what cache we have at this level
	blt	invskip				@ skip if no cache, or just i-cache
	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
						@ with armv7 this is 'isb',
						@ but we compile with armv5
	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
	and	r2, r1, #7			@ extract the length of the cache lines
	add	r2, r2, #4			@ add 4 (line length offset)
	ldr	r4, =0x3ff
	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
	clz	r5, r4				@ find bit position of way size increment
	ldr	r7, =0x7fff
	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
invloop2:
	mov	r9, r4				@ create working copy of max way size
invloop3:
	orr	r11, r10, r9, lsl r5		@ factor way and cache number into r11
	orr	r11, r11, r7, lsl r2		@ factor index number into r11
	mcr	p15, 0, r11, c7, c6, 2		@ invalidate by set/way
	subs	r9, r9, #1			@ decrement the way
	bge	invloop3
	subs	r7, r7, #1			@ decrement the index
	bge	invloop2
invskip:
	add	r10, r10, #2			@ increment cache number
	cmp	r3, r10
	bgt	invloop1
invfinished:
	mov	r10, #0				@ swith back to cache level 0
	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
						@ with armv7 this is 'isb',
						@ but we compile with armv5
	mov	pc, lr

FUNC(cpu_inv_cache_all)
	stmfd	sp!, {r0-r7, r9-r11, lr}
	bl	cpu_inv_dcache_all
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
	ldmfd	sp!, {r0-r7, r9-r11, lr}
	mov	pc, lr
END(cpu_inv_cache_all)

/* Dummy function just for link happy */
FUNC(raise)

	mov	r0, #0
	mov pc, lr

END(raise)

FUNC(__aeabi_unwind_cpp_pr0)

	mov pc, lr

END(__aeabi_unwind_cpp_pr0)

/*
 * Common code/data start here...
 */
#ifdef CONFIG_XIP
	.data
#endif

	DW(_memsize, 0)

/* C trap handler */
	DW(trap_hook, 0)

#ifdef	CONFIG_XIP
	.text
#endif

#ifdef _CFE_

/*
 * Setup the trap handler.
 */
FUNC(hndrte_set_trap)

	ldr	r2,=trap_hook
	ldr	r1,[r2]
	str	r0,[r2]
	mov	r0,r1
	bx	lr

END(hndrte_set_trap)

/*
 * Turn remap off and then jump to an given address
 */
FUNC(arm_jumpto)

	bx	r0

END(arm_jumpto)

/*  *********************************************************************
    *  CFE_FLUSHCACHE
    *
    *  Perform certain cache operations
    *
    *  Input parameters:
    *  	   a0 - flags (CFE_CACHE_xxx flags, or zero for a default)
    *      a1,a2 - start/end of range for "range invalidate" operations
    *      (not used otherwise)
    *
    *  Return value:
    *  	   nothing
    ********************************************************************* */

FUNC(_cfe_flushcache)

#ifndef CFG_UNCACHED
	mov	ip,lr			/* save lr across calls */
	bl	cpu_flush_cache_all
	mov	lr,ip			/* restore lr */
#endif

	mov pc, lr
	

END(_cfe_flushcache)

#
# arguments: r0=start, r1=size
#
FUNC(_cfe_flushcache_rang)

	mrc	p15, 1, r3, c0, c0, 0	@ read CSIDR
	and	r3, r3, #7				@ cache line size encoding
	mov	r2, #16					@ size offset
	mov	r2, r2, lsl r3			@ actual cache line size

	sub	r3, r2, #1
	bic	r0, r0, r3
1:
	mcr	p15, 0, r0, c7, c10, 1		@ clean D / U line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
#	dsb
	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
						@ with armv7 this is 'isb',
						@ but we compile with armv5
	mov	pc, lr

END(_cfe_flushcache_rang)

/*  *********************************************************************
    *  CFE_LAUNCH
    *
    *  Start the user program.  The program is passed a handle
    *  that must be passed back when calling the firmware.
    *
    *  Parameters passed to the called program are as follows:
    *
    *      a0 - CFE handle
    *      a1 - entry vector
    *      a2 - reserved, will be 0
    *      a3 - entrypoint signature.
    *
    *  Input parameters:
    *  	   a0 - entry vector
    *
    *  Return value:
    *  	   does not return
    ********************************************************************* */

FUNC(cfe_launch)

	sub  sp,sp,#8
	push {r0}

	/*
	 * Mask all interrupts.
	 */

	mrs	r0,cpsr
	ldr	r1,=(PS_I | PS_F)
	orr	r0,r0,r1
	msr	cpsr,r0

	/*
	 * Flush the D-Cache, since the program we loaded is "data".
	 * Invalidate the I-Cache, so that addresses in the program
	 * region will miss and need to be filled from the data we
	 * just flushed above.
	 */

	bl _cfe_flushcache

	/*
	 * Disable the D-Cache, MMU and I-Cache bit
	 */

	mrc	p15,0,r0,c1,c0,0	@ read SCTLR
	bic	r0,r0,#4			@ disable D-Cache
	bic	r0,r0,#1			@ disable MMU
	bic	r0,r0,#1000			@ disable I-Cache
	mcr	p15,0,r0,c1,c0,0

	/*
	 * Set things up for launching the program.  Pass the
	 * handle in A0 - apps need to remember that and pass it
	 * back.
	 */
	b RunProgram

END(cfe_launch)

/*
 * This is a nice place to set a breakpoint.
 */
FUNC(RunProgram)

	LOADREL(r2,=segment_table)
	ldr r2,[r2,#R_SEG_APIENTRY]	/* A2 = code entry */

#if CFG_EMBEDDED_PIC
	ldr r1,mem_textreloc	/* relocate table entry */
	add r2,r2,r1
#endif

	mov r4,r0
	mov r1,#0		/* A1 = 0 */
	mov r0,#0		/* A0 = handle */
	ldr r3,=CFE_EPTSEAL  /* A3 = entrypoint signature */
	pop {r4}		/* entry point */

	/* Check if the MERGE_FRAG function should execute or not,
	 * according to the information within structure cfe_frag_info_t.
	 * _frag_info_sz is the size of structure cfe_frag_info_t.
	 * Structure cfe_frag_info_t is stored right before MERGE_FRAG function, and
	 * MERGE_FRAG function is stored right before entry point.
	 * Note: {r0-r4} must be preserved
	 */
	ldr r7, =_frag_merge_func_len
	ldr r6, [r7]
	ldr r8, =_frag_info_sz
	ldr r7, [r8]
	add r6, r6, r7
	sub r5, r4, r6
	ldr r6, [r5]
	cmp r6, #0
	beq do_run
	mov pc, r6	/* Go to _merge_func */
do_run:
	mov pc, r4		/* go for it. */
END(RunProgram)


	.globl _frag_merge_func
_frag_merge_func:
	.word _merge_func

	.globl _frag_merge_func_len
_frag_merge_func_len:
	.word _merge_func_end - _merge_func

       .globl _frag_info_sz
_frag_info_sz:
	.word   0

/* This merge_func will relocate at address which is stored at MERGE_FRAG.
 * It will reference the value which is stored at MERGE_FRAG.
 * There are the merge_func pointer, des_addr, src_addr and length.
 * r4 is the entry point, r0-r3 are the parameters for the image.
 * r5 is the address of MERGE_FRAG
 */
FUNC(_merge_func)
	ldmia	r5, {r9-r12}
1:
	ldmia	r11!, {r7-r8}			@ copy 8 bytes from the memory at r11 address
	stmia	r10!, {r7-r8}			@ store 8 bytes to the memory at r10 address
						@ r12 is the length, each loop copy 8 bytes
	subs	r12, r12, #8			@ adjust the length
	bgt	1b

	mov	pc, r4				@ jump to the entry point
_merge_func_end:
END(_merge_func)

/*  *********************************************************************
    *  BOARD_SETLEDS(x)
    *
    *  Set LEDs for boot-time progress indication.  Not used if
    *  the board does not have progress LEDs.  This routine
    *  must not call any other routines, since it may be invoked
    *  either from KSEG0 or KSEG1 and it may be invoked
    *  whether or not the icache is operational.
    *
    *  Input parameters:
    *  	   a0 - LED value (8 bits per character, 4 characters)
    *
    *  Return value:
    *  	   nothing
    ********************************************************************* */
FUNC(board_setleds)

	mov	pc, lr			@ back to my caller

END(board_setleds)

/*  *********************************************************************
    *  CFE_LEDS
    *
    *  Set the on-board LEDs.
    *
    *  Input parameters:
    *  	   a0 - LEDs
    *
    *  Return value:
    *  	   nothing
    ********************************************************************* */
FUNC(cfe_leds)

	/* jump to BSP routine */
	//bl	board_setleds

	/* return */
	mov	pc, lr

END(cfe_leds)

/*  *********************************************************************
    *  _GETSEGTBL()
    *
    *  Return the address of the segment table.  We use this
    *  to display the startup messages.
    *
    *  You can't just address the table from C because it lives
    *  in the text segment.
    *
    *  Input parameters:
    *  	   nothing
    *
    *  Return value:
    *      address of table
    ********************************************************************* */

FUNC(_getsegtbl)

	mov	ip, lr		/* persevere link reg across call */
	LOADREL(r0,=segment_table)
	mov	lr, ip		/* restore link */
	mov pc, lr		/* back to my caller */

END(_getsegtbl)

/*  *********************************************************************
    *  _SETCONTEXT()
    *
    *  Set the CONTEXT register.
    *
    *  Input parameters:
    *  	   a0 - context
    *
    *  Return value:
    *  	   nothing
    ********************************************************************* */

FUNC(_setcontext)

	mov	pc,lr

END(_setcontext)

/*  *********************************************************************
    *  CFE_WARMSTART
    *
    *  Restart the command interpreter
    *
    *  Input parameters:
    *      A0 - command status
    *  	   nothing (GP has already been set up for us)
    *
    *  Return value:
    *  	   nothing
    ********************************************************************* */

FUNC(cfe_warmstart)

	mov	pc,lr

END(cfe_warmstart)

#endif /* _CFE_ */
