1/* $NetBSD: gicv3_its.h,v 1.8 2021/10/31 16:23:47 skrll Exp $ */
2
3/*-
4 * Copyright (c) 2018 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jared McNeill <jmcneill@invisible.ca>.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _ARM_CORTEX_GICV3_ITS_H
33#define _ARM_CORTEX_GICV3_ITS_H
34
35#include <dev/pci/pcivar.h>
36
37#include <arm/pci/pci_msi_machdep.h>
38#include <arm/cortex/gic_reg.h>
39#include <arm/cortex/gicv3.h>
40
41struct gicv3_its_device {
42	uint32_t		dev_id;
43	u_int			dev_size;
44	struct gicv3_dma	dev_itt;
45
46	LIST_ENTRY(gicv3_its_device) dev_list;
47};
48
49struct gicv3_its {
50	bus_space_tag_t		its_bst;
51	bus_space_handle_t	its_bsh;
52	bus_dma_tag_t		its_dmat;
53	uint32_t		its_id;
54	uint64_t		its_base;
55	uint64_t		*its_rdbase;
56	bool			*its_cpuonline;
57
58	struct gicv3_softc	*its_gic;
59	struct gicv3_lpi_callback its_cb;
60
61	struct pic_softc	*its_pic;
62	struct pci_attach_args	**its_pa;
63	struct cpu_info		**its_targets;
64	uint32_t		*its_devid;
65
66	LIST_HEAD(, gicv3_its_device) its_devices;
67
68	struct gicv3_dma	its_cmd;		/* Command queue */
69	struct gicv3_dma	its_tab[8];		/* ITS tables */
70
71	struct arm_pci_msi	its_msi;
72
73	kmutex_t		*its_lock;
74};
75
76int	gicv3_its_init(struct gicv3_softc *, bus_space_handle_t, uint64_t, uint32_t);
77
78#endif /* !_ARM_CORTEX_GICV3_ITS_H */
79