1[ 2 { 3 "BriefDescription": "C10 residency percent per package", 4 "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", 5 "MetricGroup": "Power", 6 "MetricName": "C10_Pkg_Residency", 7 "ScaleUnit": "100%" 8 }, 9 { 10 "BriefDescription": "C1 residency percent per core", 11 "MetricExpr": "cstate_core@c1\\-residency@ / TSC", 12 "MetricGroup": "Power", 13 "MetricName": "C1_Core_Residency", 14 "ScaleUnit": "100%" 15 }, 16 { 17 "BriefDescription": "C2 residency percent per package", 18 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", 19 "MetricGroup": "Power", 20 "MetricName": "C2_Pkg_Residency", 21 "ScaleUnit": "100%" 22 }, 23 { 24 "BriefDescription": "C3 residency percent per package", 25 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", 26 "MetricGroup": "Power", 27 "MetricName": "C3_Pkg_Residency", 28 "ScaleUnit": "100%" 29 }, 30 { 31 "BriefDescription": "C6 residency percent per core", 32 "MetricExpr": "cstate_core@c6\\-residency@ / TSC", 33 "MetricGroup": "Power", 34 "MetricName": "C6_Core_Residency", 35 "ScaleUnit": "100%" 36 }, 37 { 38 "BriefDescription": "C6 residency percent per package", 39 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", 40 "MetricGroup": "Power", 41 "MetricName": "C6_Pkg_Residency", 42 "ScaleUnit": "100%" 43 }, 44 { 45 "BriefDescription": "C7 residency percent per core", 46 "MetricExpr": "cstate_core@c7\\-residency@ / TSC", 47 "MetricGroup": "Power", 48 "MetricName": "C7_Core_Residency", 49 "ScaleUnit": "100%" 50 }, 51 { 52 "BriefDescription": "C7 residency percent per package", 53 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", 54 "MetricGroup": "Power", 55 "MetricName": "C7_Pkg_Residency", 56 "ScaleUnit": "100%" 57 }, 58 { 59 "BriefDescription": "C8 residency percent per package", 60 "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", 61 "MetricGroup": "Power", 62 "MetricName": "C8_Pkg_Residency", 63 "ScaleUnit": "100%" 64 }, 65 { 66 "BriefDescription": "C9 residency percent per package", 67 "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", 68 "MetricGroup": "Power", 69 "MetricName": "C9_Pkg_Residency", 70 "ScaleUnit": "100%" 71 }, 72 { 73 "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", 74 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", 75 "MetricGroup": "smi", 76 "MetricName": "smi_cycles", 77 "MetricThreshold": "smi_cycles > 0.1", 78 "ScaleUnit": "100%" 79 }, 80 { 81 "BriefDescription": "Number of SMI interrupts.", 82 "MetricExpr": "msr@smi@", 83 "MetricGroup": "smi", 84 "MetricName": "smi_num", 85 "ScaleUnit": "1SMI#" 86 }, 87 { 88 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.", 89 "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / tma_info_core_slots", 90 "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", 91 "MetricName": "tma_alloc_restriction", 92 "MetricThreshold": "tma_alloc_restriction > 0.1", 93 "ScaleUnit": "100%" 94 }, 95 { 96 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", 97 "DefaultMetricgroupName": "TopdownL1", 98 "MetricExpr": "TOPDOWN_BE_BOUND.ALL / tma_info_core_slots", 99 "MetricGroup": "Default;TopdownL1;tma_L1_group", 100 "MetricName": "tma_backend_bound", 101 "MetricThreshold": "tma_backend_bound > 0.1", 102 "MetricgroupNoGroup": "TopdownL1;Default", 103 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.", 104 "ScaleUnit": "100%" 105 }, 106 { 107 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", 108 "DefaultMetricgroupName": "TopdownL1", 109 "MetricExpr": "tma_backend_bound", 110 "MetricGroup": "Default;TopdownL1;tma_L1_group", 111 "MetricName": "tma_backend_bound_aux", 112 "MetricThreshold": "tma_backend_bound_aux > 0.2", 113 "MetricgroupNoGroup": "TopdownL1;Default", 114 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation.", 115 "ScaleUnit": "100%" 116 }, 117 { 118 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear", 119 "DefaultMetricgroupName": "TopdownL1", 120 "MetricExpr": "(tma_info_core_slots - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / tma_info_core_slots", 121 "MetricGroup": "Default;TopdownL1;tma_L1_group", 122 "MetricName": "tma_bad_speculation", 123 "MetricThreshold": "tma_bad_speculation > 0.15", 124 "MetricgroupNoGroup": "TopdownL1;Default", 125 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", 126 "ScaleUnit": "100%" 127 }, 128 { 129 "BriefDescription": "Counts the number of uops that are not from the microsequencer.", 130 "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / tma_info_core_slots", 131 "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", 132 "MetricName": "tma_base", 133 "MetricThreshold": "tma_base > 0.6", 134 "MetricgroupNoGroup": "TopdownL2", 135 "ScaleUnit": "100%" 136 }, 137 { 138 "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend", 139 "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / tma_info_core_slots", 140 "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", 141 "MetricName": "tma_branch_detect", 142 "MetricThreshold": "tma_branch_detect > 0.05", 143 "PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", 144 "ScaleUnit": "100%" 145 }, 146 { 147 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts.", 148 "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / tma_info_core_slots", 149 "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", 150 "MetricName": "tma_branch_mispredicts", 151 "MetricThreshold": "tma_branch_mispredicts > 0.05", 152 "MetricgroupNoGroup": "TopdownL2", 153 "ScaleUnit": "100%" 154 }, 155 { 156 "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", 157 "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / tma_info_core_slots", 158 "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", 159 "MetricName": "tma_branch_resteer", 160 "MetricThreshold": "tma_branch_resteer > 0.05", 161 "ScaleUnit": "100%" 162 }, 163 { 164 "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", 165 "MetricExpr": "TOPDOWN_FE_BOUND.CISC / tma_info_core_slots", 166 "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", 167 "MetricName": "tma_cisc", 168 "MetricThreshold": "tma_cisc > 0.05", 169 "ScaleUnit": "100%" 170 }, 171 { 172 "BriefDescription": "Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls.", 173 "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", 174 "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", 175 "MetricName": "tma_core_bound", 176 "MetricThreshold": "tma_core_bound > 0.1", 177 "MetricgroupNoGroup": "TopdownL2", 178 "ScaleUnit": "100%" 179 }, 180 { 181 "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", 182 "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / tma_info_core_slots", 183 "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", 184 "MetricName": "tma_decode", 185 "MetricThreshold": "tma_decode > 0.05", 186 "ScaleUnit": "100%" 187 }, 188 { 189 "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory disambiguation.", 190 "MetricExpr": "tma_nuke * (MACHINE_CLEARS.DISAMBIGUATION / MACHINE_CLEARS.SLOW)", 191 "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", 192 "MetricName": "tma_disambiguation", 193 "MetricThreshold": "tma_disambiguation > 0.02", 194 "ScaleUnit": "100%" 195 }, 196 { 197 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", 198 "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks, 0) * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD", 199 "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", 200 "MetricName": "tma_dram_bound", 201 "MetricThreshold": "tma_dram_bound > 0.1", 202 "ScaleUnit": "100%" 203 }, 204 { 205 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear classified as a fast nuke due to memory ordering, memory disambiguation and memory renaming.", 206 "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / tma_info_core_slots", 207 "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", 208 "MetricName": "tma_fast_nuke", 209 "MetricThreshold": "tma_fast_nuke > 0.05", 210 "ScaleUnit": "100%" 211 }, 212 { 213 "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", 214 "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / tma_info_core_slots", 215 "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", 216 "MetricName": "tma_fetch_bandwidth", 217 "MetricThreshold": "tma_fetch_bandwidth > 0.1", 218 "MetricgroupNoGroup": "TopdownL2", 219 "ScaleUnit": "100%" 220 }, 221 { 222 "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", 223 "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / tma_info_core_slots", 224 "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", 225 "MetricName": "tma_fetch_latency", 226 "MetricThreshold": "tma_fetch_latency > 0.15", 227 "MetricgroupNoGroup": "TopdownL2", 228 "ScaleUnit": "100%" 229 }, 230 { 231 "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to FP assists.", 232 "MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEARS.SLOW)", 233 "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", 234 "MetricName": "tma_fp_assist", 235 "MetricThreshold": "tma_fp_assist > 0.02", 236 "ScaleUnit": "100%" 237 }, 238 { 239 "BriefDescription": "Counts the number of floating point divide operations per uop.", 240 "MetricExpr": "UOPS_RETIRED.FPDIV / tma_info_core_slots", 241 "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", 242 "MetricName": "tma_fpdiv_uops", 243 "MetricThreshold": "tma_fpdiv_uops > 0.2", 244 "ScaleUnit": "100%" 245 }, 246 { 247 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", 248 "DefaultMetricgroupName": "TopdownL1", 249 "MetricExpr": "TOPDOWN_FE_BOUND.ALL / tma_info_core_slots", 250 "MetricGroup": "Default;TopdownL1;tma_L1_group", 251 "MetricName": "tma_frontend_bound", 252 "MetricThreshold": "tma_frontend_bound > 0.2", 253 "MetricgroupNoGroup": "TopdownL1;Default", 254 "ScaleUnit": "100%" 255 }, 256 { 257 "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", 258 "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / tma_info_core_slots", 259 "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", 260 "MetricName": "tma_icache_misses", 261 "MetricThreshold": "tma_icache_misses > 0.05", 262 "ScaleUnit": "100%" 263 }, 264 { 265 "BriefDescription": "", 266 "MetricExpr": "CPU_CLK_UNHALTED.CORE", 267 "MetricName": "tma_info_core_clks" 268 }, 269 { 270 "BriefDescription": "", 271 "MetricExpr": "CPU_CLK_UNHALTED.CORE_P", 272 "MetricName": "tma_info_core_clks_p" 273 }, 274 { 275 "BriefDescription": "Cycles Per Instruction", 276 "MetricExpr": "tma_info_core_clks / INST_RETIRED.ANY", 277 "MetricName": "tma_info_core_cpi" 278 }, 279 { 280 "BriefDescription": "Instructions Per Cycle", 281 "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", 282 "MetricName": "tma_info_core_ipc" 283 }, 284 { 285 "BriefDescription": "", 286 "MetricExpr": "5 * tma_info_core_clks", 287 "MetricName": "tma_info_core_slots" 288 }, 289 { 290 "BriefDescription": "Uops Per Instruction", 291 "MetricExpr": "UOPS_RETIRED.ALL / INST_RETIRED.ANY", 292 "MetricName": "tma_info_core_upi" 293 }, 294 { 295 "BriefDescription": "Percent of instruction miss cost that hit in DRAM", 296 "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH", 297 "MetricName": "tma_info_frontend_inst_miss_cost_dramhit_percent" 298 }, 299 { 300 "BriefDescription": "Percent of instruction miss cost that hit in the L2", 301 "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH", 302 "MetricName": "tma_info_frontend_inst_miss_cost_l2hit_percent" 303 }, 304 { 305 "BriefDescription": "Percent of instruction miss cost that hit in the L3", 306 "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH", 307 "MetricName": "tma_info_frontend_inst_miss_cost_l3hit_percent" 308 }, 309 { 310 "BriefDescription": "Ratio of all branches which mispredict", 311 "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES", 312 "MetricName": "tma_info_inst_mix_branch_mispredict_ratio" 313 }, 314 { 315 "BriefDescription": "Ratio between Mispredicted branches and unknown branches", 316 "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY", 317 "MetricName": "tma_info_inst_mix_branch_mispredict_to_unknown_branch_ratio" 318 }, 319 { 320 "BriefDescription": "Percentage of all uops which are FPDiv uops", 321 "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL", 322 "MetricName": "tma_info_inst_mix_fpdiv_uop_ratio" 323 }, 324 { 325 "BriefDescription": "Percentage of all uops which are IDiv uops", 326 "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL", 327 "MetricName": "tma_info_inst_mix_idiv_uop_ratio" 328 }, 329 { 330 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", 331 "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", 332 "MetricName": "tma_info_inst_mix_ipbranch" 333 }, 334 { 335 "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)", 336 "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL", 337 "MetricName": "tma_info_inst_mix_ipcall" 338 }, 339 { 340 "BriefDescription": "Instructions per Far Branch", 341 "MetricExpr": "INST_RETIRED.ANY / (BR_INST_RETIRED.FAR_BRANCH / 2)", 342 "MetricName": "tma_info_inst_mix_ipfarbranch" 343 }, 344 { 345 "BriefDescription": "Instructions per Load", 346 "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", 347 "MetricName": "tma_info_inst_mix_ipload" 348 }, 349 { 350 "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken", 351 "MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN)", 352 "MetricName": "tma_info_inst_mix_ipmisp_cond_ntaken" 353 }, 354 { 355 "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was taken", 356 "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", 357 "MetricName": "tma_info_inst_mix_ipmisp_cond_taken" 358 }, 359 { 360 "BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction", 361 "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", 362 "MetricName": "tma_info_inst_mix_ipmisp_indirect" 363 }, 364 { 365 "BriefDescription": "Instructions per retired return Branch Misprediction", 366 "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN", 367 "MetricName": "tma_info_inst_mix_ipmisp_ret" 368 }, 369 { 370 "BriefDescription": "Instructions per retired Branch Misprediction", 371 "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", 372 "MetricName": "tma_info_inst_mix_ipmispredict" 373 }, 374 { 375 "BriefDescription": "Instructions per Store", 376 "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", 377 "MetricName": "tma_info_inst_mix_ipstore" 378 }, 379 { 380 "BriefDescription": "Percentage of all uops which are ucode ops", 381 "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL", 382 "MetricName": "tma_info_inst_mix_microcode_uop_ratio" 383 }, 384 { 385 "BriefDescription": "Percentage of all uops which are x87 uops", 386 "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL", 387 "MetricName": "tma_info_inst_mix_x87_uop_ratio" 388 }, 389 { 390 "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block", 391 "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS", 392 "MetricName": "tma_info_l1_bound_address_alias_blocks" 393 }, 394 { 395 "BriefDescription": "Percentage of total non-speculative loads that are splits", 396 "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS", 397 "MetricName": "tma_info_l1_bound_load_splits" 398 }, 399 { 400 "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block", 401 "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS", 402 "MetricName": "tma_info_l1_bound_store_fwd_blocks" 403 }, 404 { 405 "BriefDescription": "Cycle cost per DRAM hit", 406 "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETIRED.DRAM_HIT", 407 "MetricName": "tma_info_memory_cycles_per_demand_load_dram_hit" 408 }, 409 { 410 "BriefDescription": "Cycle cost per L2 hit", 411 "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRED.L2_HIT", 412 "MetricName": "tma_info_memory_cycles_per_demand_load_l2_hit" 413 }, 414 { 415 "BriefDescription": "Cycle cost per LLC hit", 416 "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIRED.L3_HIT", 417 "MetricName": "tma_info_memory_cycles_per_demand_load_l3_hit" 418 }, 419 { 420 "BriefDescription": "load ops retired per 1000 instruction", 421 "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", 422 "MetricName": "tma_info_memory_memloadpki" 423 }, 424 { 425 "BriefDescription": "Average CPU Utilization", 426 "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", 427 "MetricName": "tma_info_system_cpu_utilization" 428 }, 429 { 430 "BriefDescription": "Fraction of cycles spent in Kernel mode", 431 "MetricExpr": "cpu@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE", 432 "MetricGroup": "Summary", 433 "MetricName": "tma_info_system_kernel_utilization" 434 }, 435 { 436 "BriefDescription": "Average Frequency Utilization relative nominal frequency", 437 "MetricExpr": "tma_info_core_clks / CPU_CLK_UNHALTED.REF_TSC", 438 "MetricGroup": "Power", 439 "MetricName": "tma_info_system_turbo_utilization" 440 }, 441 { 442 "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", 443 "MetricExpr": "TOPDOWN_FE_BOUND.ITLB / tma_info_core_slots", 444 "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", 445 "MetricName": "tma_itlb_misses", 446 "MetricThreshold": "tma_itlb_misses > 0.05", 447 "ScaleUnit": "100%" 448 }, 449 { 450 "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block.", 451 "MetricExpr": "LD_HEAD.L1_BOUND_AT_RET / tma_info_core_clks", 452 "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", 453 "MetricName": "tma_l1_bound", 454 "MetricThreshold": "tma_l1_bound > 0.1", 455 "ScaleUnit": "100%" 456 }, 457 { 458 "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.", 459 "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks, 0) * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD", 460 "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", 461 "MetricName": "tma_l2_bound", 462 "MetricThreshold": "tma_l2_bound > 0.1", 463 "ScaleUnit": "100%" 464 }, 465 { 466 "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", 467 "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks, 0) * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD", 468 "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", 469 "MetricName": "tma_l3_bound", 470 "MetricThreshold": "tma_l3_bound > 0.1", 471 "ScaleUnit": "100%" 472 }, 473 { 474 "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to load buffer full", 475 "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.LD_BUF / MEM_SCHEDULER_BLOCK.ALL", 476 "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", 477 "MetricName": "tma_ld_buffer", 478 "MetricThreshold": "tma_ld_buffer > 0.05", 479 "ScaleUnit": "100%" 480 }, 481 { 482 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", 483 "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / tma_info_core_slots", 484 "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", 485 "MetricName": "tma_machine_clears", 486 "MetricThreshold": "tma_machine_clears > 0.05", 487 "MetricgroupNoGroup": "TopdownL2", 488 "ScaleUnit": "100%" 489 }, 490 { 491 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", 492 "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / tma_info_core_slots", 493 "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", 494 "MetricName": "tma_mem_scheduler", 495 "MetricThreshold": "tma_mem_scheduler > 0.1", 496 "ScaleUnit": "100%" 497 }, 498 { 499 "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads.", 500 "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_info_core_clks + tma_store_bound)", 501 "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", 502 "MetricName": "tma_memory_bound", 503 "MetricThreshold": "tma_memory_bound > 0.2", 504 "MetricgroupNoGroup": "TopdownL2", 505 "ScaleUnit": "100%" 506 }, 507 { 508 "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory ordering.", 509 "MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.SLOW)", 510 "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", 511 "MetricName": "tma_memory_ordering", 512 "MetricThreshold": "tma_memory_ordering > 0.02", 513 "ScaleUnit": "100%" 514 }, 515 { 516 "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)", 517 "MetricExpr": "UOPS_RETIRED.MS / tma_info_core_slots", 518 "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", 519 "MetricName": "tma_ms_uops", 520 "MetricThreshold": "tma_ms_uops > 0.05", 521 "MetricgroupNoGroup": "TopdownL2", 522 "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", 523 "ScaleUnit": "100%" 524 }, 525 { 526 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", 527 "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / tma_info_core_slots", 528 "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", 529 "MetricName": "tma_non_mem_scheduler", 530 "MetricThreshold": "tma_non_mem_scheduler > 0.1", 531 "ScaleUnit": "100%" 532 }, 533 { 534 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear (slow nuke).", 535 "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / tma_info_core_slots", 536 "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", 537 "MetricName": "tma_nuke", 538 "MetricThreshold": "tma_nuke > 0.05", 539 "ScaleUnit": "100%" 540 }, 541 { 542 "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", 543 "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / tma_info_core_slots", 544 "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", 545 "MetricName": "tma_other_fb", 546 "MetricThreshold": "tma_other_fb > 0.05", 547 "ScaleUnit": "100%" 548 }, 549 { 550 "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a number of other load blocks.", 551 "MetricExpr": "LD_HEAD.OTHER_AT_RET / tma_info_core_clks", 552 "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", 553 "MetricName": "tma_other_l1", 554 "MetricThreshold": "tma_other_l1 > 0.05", 555 "ScaleUnit": "100%" 556 }, 557 { 558 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer.", 559 "MetricExpr": "max(0, tma_memory_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", 560 "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", 561 "MetricName": "tma_other_load_store", 562 "MetricThreshold": "tma_other_load_store > 0.1", 563 "ScaleUnit": "100%" 564 }, 565 { 566 "BriefDescription": "Counts the number of uops retired excluding ms and fp div uops.", 567 "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV) / tma_info_core_slots", 568 "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", 569 "MetricName": "tma_other_ret", 570 "MetricThreshold": "tma_other_ret > 0.3", 571 "ScaleUnit": "100%" 572 }, 573 { 574 "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to page faults.", 575 "MetricExpr": "tma_nuke * (MACHINE_CLEARS.PAGE_FAULT / MACHINE_CLEARS.SLOW)", 576 "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", 577 "MetricName": "tma_page_fault", 578 "MetricThreshold": "tma_page_fault > 0.02", 579 "ScaleUnit": "100%" 580 }, 581 { 582 "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", 583 "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / tma_info_core_slots", 584 "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", 585 "MetricName": "tma_predecode", 586 "MetricThreshold": "tma_predecode > 0.05", 587 "ScaleUnit": "100%" 588 }, 589 { 590 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", 591 "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / tma_info_core_slots", 592 "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", 593 "MetricName": "tma_register", 594 "MetricThreshold": "tma_register > 0.1", 595 "ScaleUnit": "100%" 596 }, 597 { 598 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", 599 "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / tma_info_core_slots", 600 "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", 601 "MetricName": "tma_reorder_buffer", 602 "MetricThreshold": "tma_reorder_buffer > 0.1", 603 "ScaleUnit": "100%" 604 }, 605 { 606 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", 607 "MetricExpr": "tma_backend_bound", 608 "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group", 609 "MetricName": "tma_resource_bound", 610 "MetricThreshold": "tma_resource_bound > 0.2", 611 "MetricgroupNoGroup": "TopdownL2", 612 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count.", 613 "ScaleUnit": "100%" 614 }, 615 { 616 "BriefDescription": "Counts the number of issue slots that result in retirement slots.", 617 "DefaultMetricgroupName": "TopdownL1", 618 "MetricExpr": "TOPDOWN_RETIRING.ALL / tma_info_core_slots", 619 "MetricGroup": "Default;TopdownL1;tma_L1_group", 620 "MetricName": "tma_retiring", 621 "MetricThreshold": "tma_retiring > 0.75", 622 "MetricgroupNoGroup": "TopdownL1;Default", 623 "ScaleUnit": "100%" 624 }, 625 { 626 "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to RSV full relative", 627 "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.RSV / MEM_SCHEDULER_BLOCK.ALL", 628 "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", 629 "MetricName": "tma_rsv", 630 "MetricThreshold": "tma_rsv > 0.05", 631 "ScaleUnit": "100%" 632 }, 633 { 634 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", 635 "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / tma_info_core_slots", 636 "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", 637 "MetricName": "tma_serialization", 638 "MetricThreshold": "tma_serialization > 0.1", 639 "ScaleUnit": "100%" 640 }, 641 { 642 "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to SMC.", 643 "MetricExpr": "tma_nuke * (MACHINE_CLEARS.SMC / MACHINE_CLEARS.SLOW)", 644 "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", 645 "MetricName": "tma_smc", 646 "MetricThreshold": "tma_smc > 0.02", 647 "ScaleUnit": "100%" 648 }, 649 { 650 "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to store buffer full", 651 "MetricExpr": "tma_store_bound", 652 "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", 653 "MetricName": "tma_st_buffer", 654 "MetricThreshold": "tma_st_buffer > 0.05", 655 "ScaleUnit": "100%" 656 }, 657 { 658 "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a first level TLB miss.", 659 "MetricExpr": "LD_HEAD.DTLB_MISS_AT_RET / tma_info_core_clks", 660 "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", 661 "MetricName": "tma_stlb_hit", 662 "MetricThreshold": "tma_stlb_hit > 0.05", 663 "ScaleUnit": "100%" 664 }, 665 { 666 "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a second level TLB miss requiring a page walk.", 667 "MetricExpr": "LD_HEAD.PGWALK_AT_RET / tma_info_core_clks", 668 "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", 669 "MetricName": "tma_stlb_miss", 670 "MetricThreshold": "tma_stlb_miss > 0.05", 671 "ScaleUnit": "100%" 672 }, 673 { 674 "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.", 675 "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)", 676 "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", 677 "MetricName": "tma_store_bound", 678 "MetricThreshold": "tma_store_bound > 0.1", 679 "ScaleUnit": "100%" 680 }, 681 { 682 "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block.", 683 "MetricExpr": "LD_HEAD.ST_ADDR_AT_RET / tma_info_core_clks", 684 "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", 685 "MetricName": "tma_store_fwd_blk", 686 "MetricThreshold": "tma_store_fwd_blk > 0.05", 687 "ScaleUnit": "100%" 688 } 689] 690