1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2017 Intel Corporation. All rights reserved. 7 * 8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 */ 10 11#ifndef __SOF_INTEL_HDA_H 12#define __SOF_INTEL_HDA_H 13 14#include <linux/soundwire/sdw.h> 15#include <linux/soundwire/sdw_intel.h> 16#include <sound/compress_driver.h> 17#include <sound/hda_codec.h> 18#include <sound/hdaudio_ext.h> 19#include "../sof-client-probes.h" 20#include "../sof-audio.h" 21#include "shim.h" 22 23/* PCI registers */ 24#define PCI_TCSEL 0x44 25#define PCI_PGCTL PCI_TCSEL 26#define PCI_CGCTL 0x48 27 28/* PCI_PGCTL bits */ 29#define PCI_PGCTL_ADSPPGD BIT(2) 30#define PCI_PGCTL_LSRMD_MASK BIT(4) 31 32/* PCI_CGCTL bits */ 33#define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 34#define PCI_CGCTL_ADSPDCGE BIT(1) 35 36/* Legacy HDA registers and bits used - widths are variable */ 37#define SOF_HDA_GCAP 0x0 38#define SOF_HDA_GCTL 0x8 39/* accept unsol. response enable */ 40#define SOF_HDA_GCTL_UNSOL BIT(8) 41#define SOF_HDA_LLCH 0x14 42#define SOF_HDA_INTCTL 0x20 43#define SOF_HDA_INTSTS 0x24 44#define SOF_HDA_WAKESTS 0x0E 45#define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 46#define SOF_HDA_RIRBSTS 0x5d 47 48/* SOF_HDA_GCTL register bist */ 49#define SOF_HDA_GCTL_RESET BIT(0) 50 51/* SOF_HDA_INCTL regs */ 52#define SOF_HDA_INT_GLOBAL_EN BIT(31) 53#define SOF_HDA_INT_CTRL_EN BIT(30) 54#define SOF_HDA_INT_ALL_STREAM 0xff 55 56/* SOF_HDA_INTSTS regs */ 57#define SOF_HDA_INTSTS_GIS BIT(31) 58 59#define SOF_HDA_MAX_CAPS 10 60#define SOF_HDA_CAP_ID_OFF 16 61#define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 62 SOF_HDA_CAP_ID_OFF) 63#define SOF_HDA_CAP_NEXT_MASK 0xFFFF 64 65#define SOF_HDA_GTS_CAP_ID 0x1 66#define SOF_HDA_ML_CAP_ID 0x2 67 68#define SOF_HDA_PP_CAP_ID 0x3 69#define SOF_HDA_REG_PP_PPCH 0x10 70#define SOF_HDA_REG_PP_PPCTL 0x04 71#define SOF_HDA_REG_PP_PPSTS 0x08 72#define SOF_HDA_PPCTL_PIE BIT(31) 73#define SOF_HDA_PPCTL_GPROCEN BIT(30) 74 75/*Vendor Specific Registers*/ 76#define SOF_HDA_VS_D0I3C 0x104A 77 78/* D0I3C Register fields */ 79#define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ 80#define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ 81 82/* DPIB entry size: 8 Bytes = 2 DWords */ 83#define SOF_HDA_DPIB_ENTRY_SIZE 0x8 84 85#define SOF_HDA_SPIB_CAP_ID 0x4 86#define SOF_HDA_DRSM_CAP_ID 0x5 87 88#define SOF_HDA_SPIB_BASE 0x08 89#define SOF_HDA_SPIB_INTERVAL 0x08 90#define SOF_HDA_SPIB_SPIB 0x00 91#define SOF_HDA_SPIB_MAXFIFO 0x04 92 93#define SOF_HDA_PPHC_BASE 0x10 94#define SOF_HDA_PPHC_INTERVAL 0x10 95 96#define SOF_HDA_PPLC_BASE 0x10 97#define SOF_HDA_PPLC_MULTI 0x10 98#define SOF_HDA_PPLC_INTERVAL 0x10 99 100#define SOF_HDA_DRSM_BASE 0x08 101#define SOF_HDA_DRSM_INTERVAL 0x08 102 103/* Descriptor error interrupt */ 104#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 105 106/* FIFO error interrupt */ 107#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 108 109/* Buffer completion interrupt */ 110#define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 111 112#define SOF_HDA_CL_DMA_SD_INT_MASK \ 113 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 114 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 115 SOF_HDA_CL_DMA_SD_INT_COMPLETE) 116#define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 117 118/* Intel HD Audio Code Loader DMA Registers */ 119#define SOF_HDA_ADSP_LOADER_BASE 0x80 120#define SOF_HDA_ADSP_DPLBASE 0x70 121#define SOF_HDA_ADSP_DPUBASE 0x74 122#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 123 124/* Stream Registers */ 125#define SOF_HDA_ADSP_REG_SD_CTL 0x00 126#define SOF_HDA_ADSP_REG_SD_STS 0x03 127#define SOF_HDA_ADSP_REG_SD_LPIB 0x04 128#define SOF_HDA_ADSP_REG_SD_CBL 0x08 129#define SOF_HDA_ADSP_REG_SD_LVI 0x0C 130#define SOF_HDA_ADSP_REG_SD_FIFOW 0x0E 131#define SOF_HDA_ADSP_REG_SD_FIFOSIZE 0x10 132#define SOF_HDA_ADSP_REG_SD_FORMAT 0x12 133#define SOF_HDA_ADSP_REG_SD_FIFOL 0x14 134#define SOF_HDA_ADSP_REG_SD_BDLPL 0x18 135#define SOF_HDA_ADSP_REG_SD_BDLPU 0x1C 136#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 137 138/* SDxFIFOS FIFOS */ 139#define SOF_HDA_SD_FIFOSIZE_FIFOS_MASK GENMASK(15, 0) 140 141/* CL: Software Position Based FIFO Capability Registers */ 142#define SOF_DSP_REG_CL_SPBFIFO \ 143 (SOF_HDA_ADSP_LOADER_BASE + 0x20) 144#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 145#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 146#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 147#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 148 149/* Stream Number */ 150#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 151#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 152 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 153 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 154 155#define HDA_DSP_HDA_BAR 0 156#define HDA_DSP_PP_BAR 1 157#define HDA_DSP_SPIB_BAR 2 158#define HDA_DSP_DRSM_BAR 3 159#define HDA_DSP_BAR 4 160 161#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 162 163#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 164 165#define HDA_DSP_PANIC_OFFSET(x) \ 166 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 167 168/* SRAM window 0 FW "registers" */ 169#define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 170#define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 171/* FW and ROM share offset 4 */ 172#define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 173#define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 174#define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 175 176#define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 177 178#define HDA_DSP_STREAM_RESET_TIMEOUT 300 179/* 180 * Timeout in us, for setting the stream RUN bit, during 181 * start/stop the stream. The timeout expires if new RUN bit 182 * value cannot be read back within the specified time. 183 */ 184#define HDA_DSP_STREAM_RUN_TIMEOUT 300 185 186#define HDA_DSP_SPIB_ENABLE 1 187#define HDA_DSP_SPIB_DISABLE 0 188 189#define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 190 191#define HDA_DSP_STACK_DUMP_SIZE 32 192 193/* ROM/FW status register */ 194#define FSR_STATE_MASK GENMASK(23, 0) 195#define FSR_WAIT_STATE_MASK GENMASK(27, 24) 196#define FSR_MODULE_MASK GENMASK(30, 28) 197#define FSR_HALTED BIT(31) 198#define FSR_TO_STATE_CODE(x) ((x) & FSR_STATE_MASK) 199#define FSR_TO_WAIT_STATE_CODE(x) (((x) & FSR_WAIT_STATE_MASK) >> 24) 200#define FSR_TO_MODULE_CODE(x) (((x) & FSR_MODULE_MASK) >> 28) 201 202/* Wait states */ 203#define FSR_WAIT_FOR_IPC_BUSY 0x1 204#define FSR_WAIT_FOR_IPC_DONE 0x2 205#define FSR_WAIT_FOR_CACHE_INVALIDATION 0x3 206#define FSR_WAIT_FOR_LP_SRAM_OFF 0x4 207#define FSR_WAIT_FOR_DMA_BUFFER_FULL 0x5 208#define FSR_WAIT_FOR_CSE_CSR 0x6 209 210/* Module codes */ 211#define FSR_MOD_ROM 0x0 212#define FSR_MOD_ROM_BYP 0x1 213#define FSR_MOD_BASE_FW 0x2 214#define FSR_MOD_LP_BOOT 0x3 215#define FSR_MOD_BRNGUP 0x4 216#define FSR_MOD_ROM_EXT 0x5 217 218/* State codes (module dependent) */ 219/* Module independent states */ 220#define FSR_STATE_INIT 0x0 221#define FSR_STATE_INIT_DONE 0x1 222#define FSR_STATE_FW_ENTERED 0x5 223 224/* ROM states */ 225#define FSR_STATE_ROM_INIT FSR_STATE_INIT 226#define FSR_STATE_ROM_INIT_DONE FSR_STATE_INIT_DONE 227#define FSR_STATE_ROM_CSE_MANIFEST_LOADED 0x2 228#define FSR_STATE_ROM_FW_MANIFEST_LOADED 0x3 229#define FSR_STATE_ROM_FW_FW_LOADED 0x4 230#define FSR_STATE_ROM_FW_ENTERED FSR_STATE_FW_ENTERED 231#define FSR_STATE_ROM_VERIFY_FEATURE_MASK 0x6 232#define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7 233#define FSR_STATE_ROM_FETCH_ROM_EXT 0x8 234#define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9 235#define FSR_STATE_ROM_BASEFW_ENTERED 0xf /* SKL */ 236 237/* (ROM) CSE states */ 238#define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10 239#define FSR_STATE_ROM_CSE_IMR_GRANTED 0x11 240#define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST 0x12 241#define FSR_STATE_ROM_CSE_IMAGE_VALIDATED 0x13 242 243#define FSR_STATE_ROM_CSE_IPC_IFACE_INIT 0x20 244#define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 0x21 245#define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY 0x22 246#define FSR_STATE_ROM_CSE_IPC_OPERATIONAL 0x23 247#define FSR_STATE_ROM_CSE_IPC_DOWN 0x24 248 249/* BRINGUP (or BRNGUP) states */ 250#define FSR_STATE_BRINGUP_INIT FSR_STATE_INIT 251#define FSR_STATE_BRINGUP_INIT_DONE FSR_STATE_INIT_DONE 252#define FSR_STATE_BRINGUP_HPSRAM_LOAD 0x2 253#define FSR_STATE_BRINGUP_UNPACK_START 0X3 254#define FSR_STATE_BRINGUP_IMR_RESTORE 0x4 255#define FSR_STATE_BRINGUP_FW_ENTERED FSR_STATE_FW_ENTERED 256 257/* ROM status/error values */ 258#define HDA_DSP_ROM_CSE_ERROR 40 259#define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 260#define HDA_DSP_ROM_IMR_TO_SMALL 42 261#define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 262#define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 263#define HDA_DSP_ROM_IPC_FATAL_ERROR 45 264#define HDA_DSP_ROM_L2_CACHE_ERROR 46 265#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 266#define HDA_DSP_ROM_API_PTR_INVALID 50 267#define HDA_DSP_ROM_BASEFW_INCOMPAT 51 268#define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 269#define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 270#define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 271#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 272#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 273#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 274 275#define HDA_DSP_ROM_IPC_CONTROL 0x01000000 276#define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000 277 278/* various timeout values */ 279#define HDA_DSP_PU_TIMEOUT 50 280#define HDA_DSP_PD_TIMEOUT 50 281#define HDA_DSP_RESET_TIMEOUT_US 50000 282#define HDA_DSP_BASEFW_TIMEOUT_US 3000000 283#define HDA_DSP_INIT_TIMEOUT_US 500000 284#define HDA_DSP_CTRL_RESET_TIMEOUT 100 285#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 286#define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 287#define HDA_DSP_REG_POLL_RETRY_COUNT 50 288 289#define HDA_DSP_ADSPIC_IPC BIT(0) 290#define HDA_DSP_ADSPIS_IPC BIT(0) 291 292/* Intel HD Audio General DSP Registers */ 293#define HDA_DSP_GEN_BASE 0x0 294#define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 295#define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 296#define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 297#define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 298#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 299 300#define HDA_DSP_REG_ADSPIC2_SNDW BIT(5) 301#define HDA_DSP_REG_ADSPIS2_SNDW BIT(5) 302 303/* Intel HD Audio Inter-Processor Communication Registers */ 304#define HDA_DSP_IPC_BASE 0x40 305#define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 306#define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 307#define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 308#define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 309#define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 310 311/* Intel Vendor Specific Registers */ 312#define HDA_VS_INTEL_EM2 0x1030 313#define HDA_VS_INTEL_EM2_L1SEN BIT(13) 314#define HDA_VS_INTEL_LTRP 0x1048 315#define HDA_VS_INTEL_LTRP_GB_MASK 0x3F 316 317/* HIPCI */ 318#define HDA_DSP_REG_HIPCI_BUSY BIT(31) 319#define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 320 321/* HIPCIE */ 322#define HDA_DSP_REG_HIPCIE_DONE BIT(30) 323#define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 324 325/* HIPCCTL */ 326#define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 327#define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 328 329/* HIPCT */ 330#define HDA_DSP_REG_HIPCT_BUSY BIT(31) 331#define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 332 333/* HIPCTE */ 334#define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 335 336#define HDA_DSP_ADSPIC_CL_DMA BIT(1) 337#define HDA_DSP_ADSPIS_CL_DMA BIT(1) 338 339/* Delay before scheduling D0i3 entry */ 340#define BXT_D0I3_DELAY 5000 341 342#define FW_CL_STREAM_NUMBER 0x1 343#define HDA_FW_BOOT_ATTEMPTS 3 344 345/* ADSPCS - Audio DSP Control & Status */ 346 347/* 348 * Core Reset - asserted high 349 * CRST Mask for a given core mask pattern, cm 350 */ 351#define HDA_DSP_ADSPCS_CRST_SHIFT 0 352#define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 353 354/* 355 * Core run/stall - when set to '1' core is stalled 356 * CSTALL Mask for a given core mask pattern, cm 357 */ 358#define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 359#define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 360 361/* 362 * Set Power Active - when set to '1' turn cores on 363 * SPA Mask for a given core mask pattern, cm 364 */ 365#define HDA_DSP_ADSPCS_SPA_SHIFT 16 366#define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 367 368/* 369 * Current Power Active - power status of cores, set by hardware 370 * CPA Mask for a given core mask pattern, cm 371 */ 372#define HDA_DSP_ADSPCS_CPA_SHIFT 24 373#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 374 375/* 376 * Mask for a given number of cores 377 * nc = number of supported cores 378 */ 379#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 380 381/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 382#define CNL_DSP_IPC_BASE 0xc0 383#define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 384#define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 385#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 386#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 387#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 388#define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) 389#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 390 391/* HIPCI */ 392#define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 393#define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 394 395/* HIPCIE */ 396#define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 397#define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 398 399/* HIPCCTL */ 400#define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 401#define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 402 403/* HIPCT */ 404#define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 405#define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 406 407/* HIPCTDA */ 408#define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 409#define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 410 411/* HIPCTDD */ 412#define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 413 414/* BDL */ 415#define HDA_DSP_BDL_SIZE 4096 416#define HDA_DSP_MAX_BDL_ENTRIES \ 417 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 418 419/* Number of DAIs */ 420#define SOF_SKL_NUM_DAIS_NOCODEC 8 421 422#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 423#define SOF_SKL_NUM_DAIS 15 424#else 425#define SOF_SKL_NUM_DAIS SOF_SKL_NUM_DAIS_NOCODEC 426#endif 427 428/* Intel HD Audio SRAM Window 0*/ 429#define HDA_DSP_SRAM_REG_ROM_STATUS_SKL 0x8000 430#define HDA_ADSP_SRAM0_BASE_SKL 0x8000 431 432/* Firmware status window */ 433#define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 434#define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 435 436/* Host Device Memory Space */ 437#define APL_SSP_BASE_OFFSET 0x2000 438#define CNL_SSP_BASE_OFFSET 0x10000 439 440/* Host Device Memory Size of a Single SSP */ 441#define SSP_DEV_MEM_SIZE 0x1000 442 443/* SSP Count of the Platform */ 444#define APL_SSP_COUNT 6 445#define CNL_SSP_COUNT 3 446#define ICL_SSP_COUNT 6 447#define TGL_SSP_COUNT 3 448#define MTL_SSP_COUNT 3 449 450/* SSP Registers */ 451#define SSP_SSC1_OFFSET 0x4 452#define SSP_SET_SCLK_CONSUMER BIT(25) 453#define SSP_SET_SFRM_CONSUMER BIT(24) 454#define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER) 455 456#define HDA_IDISP_ADDR 2 457#define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR)) 458 459struct sof_intel_dsp_bdl { 460 __le32 addr_l; 461 __le32 addr_h; 462 __le32 size; 463 __le32 ioc; 464} __attribute((packed)); 465 466#define SOF_HDA_PLAYBACK_STREAMS 16 467#define SOF_HDA_CAPTURE_STREAMS 16 468#define SOF_HDA_PLAYBACK 0 469#define SOF_HDA_CAPTURE 1 470 471/* stream flags */ 472#define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1 473 474/* 475 * Time in ms for opportunistic D0I3 entry delay. 476 * This has been deliberately chosen to be long to avoid race conditions. 477 * Could be optimized in future. 478 */ 479#define SOF_HDA_D0I3_WORK_DELAY_MS 5000 480 481/* HDA DSP D0 substate */ 482enum sof_hda_D0_substate { 483 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ 484 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ 485}; 486 487/* represents DSP HDA controller frontend - i.e. host facing control */ 488struct sof_intel_hda_dev { 489 bool imrboot_supported; 490 bool skip_imr_boot; 491 bool booted_from_imr; 492 493 int boot_iteration; 494 495 struct hda_bus hbus; 496 497 /* hw config */ 498 const struct sof_intel_dsp_desc *desc; 499 500 /* trace */ 501 struct hdac_ext_stream *dtrace_stream; 502 503 /* if position update IPC needed */ 504 u32 no_ipc_position; 505 506 /* the maximum number of streams (playback + capture) supported */ 507 u32 stream_max; 508 509 /* PM related */ 510 bool l1_disabled;/* is DMI link L1 disabled? */ 511 512 /* DMIC device */ 513 struct platform_device *dmic_dev; 514 515 /* delayed work to enter D0I3 opportunistically */ 516 struct delayed_work d0i3_work; 517 518 /* ACPI information stored between scan and probe steps */ 519 struct sdw_intel_acpi_info info; 520 521 /* sdw context allocated by SoundWire driver */ 522 struct sdw_intel_ctx *sdw; 523 524 /* FW clock config, 0:HPRO, 1:LPRO */ 525 bool clk_config_lpro; 526 527 wait_queue_head_t waitq; 528 bool code_loading; 529 530 /* Intel NHLT information */ 531 struct nhlt_acpi_table *nhlt; 532 533 /* 534 * Pointing to the IPC message if immediate sending was not possible 535 * because the downlink communication channel was BUSY at the time. 536 * The message will be re-tried when the channel becomes free (the ACK 537 * is received from the DSP for the previous message) 538 */ 539 struct snd_sof_ipc_msg *delayed_ipc_tx_msg; 540}; 541 542static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 543{ 544 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 545 546 return &hda->hbus.core; 547} 548 549static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 550{ 551 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 552 553 return &hda->hbus; 554} 555 556struct sof_intel_hda_stream { 557 struct snd_sof_dev *sdev; 558 struct hdac_ext_stream hext_stream; 559 struct sof_intel_stream sof_intel_stream; 560 int host_reserved; /* reserve host DMA channel */ 561 u32 flags; 562}; 563 564#define hstream_to_sof_hda_stream(hstream) \ 565 container_of(hstream, struct sof_intel_hda_stream, hext_stream) 566 567#define bus_to_sof_hda(bus) \ 568 container_of(bus, struct sof_intel_hda_dev, hbus.core) 569 570#define SOF_STREAM_SD_OFFSET(s) \ 571 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 572 + SOF_HDA_ADSP_LOADER_BASE) 573 574#define SOF_STREAM_SD_OFFSET_CRST 0x1 575 576/* 577 * DAI support 578 */ 579bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type); 580 581/* 582 * DSP Core services. 583 */ 584int hda_dsp_probe_early(struct snd_sof_dev *sdev); 585int hda_dsp_probe(struct snd_sof_dev *sdev); 586void hda_dsp_remove(struct snd_sof_dev *sdev); 587void hda_dsp_remove_late(struct snd_sof_dev *sdev); 588int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); 589int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 590int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 591int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 592 unsigned int core_mask); 593int hda_power_down_dsp(struct snd_sof_dev *sdev); 594int hda_dsp_core_get(struct snd_sof_dev *sdev, int core); 595void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 596void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 597bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask); 598 599int hda_dsp_set_power_state_ipc3(struct snd_sof_dev *sdev, 600 const struct sof_dsp_power_state *target_state); 601int hda_dsp_set_power_state_ipc4(struct snd_sof_dev *sdev, 602 const struct sof_dsp_power_state *target_state); 603 604int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); 605int hda_dsp_resume(struct snd_sof_dev *sdev); 606int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 607int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 608int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 609int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev); 610int hda_dsp_shutdown(struct snd_sof_dev *sdev); 611int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 612void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 613void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 614void hda_ipc_dump(struct snd_sof_dev *sdev); 615void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 616void hda_dsp_d0i3_work(struct work_struct *work); 617int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev); 618 619/* 620 * DSP PCM Operations. 621 */ 622u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); 623u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); 624int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 625 struct snd_pcm_substream *substream); 626int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 627 struct snd_pcm_substream *substream); 628int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 629 struct snd_pcm_substream *substream, 630 struct snd_pcm_hw_params *params, 631 struct snd_sof_platform_stream_params *platform_params); 632int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 633 struct snd_pcm_substream *substream); 634int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 635 struct snd_pcm_substream *substream, int cmd); 636snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 637 struct snd_pcm_substream *substream); 638int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 639 640/* 641 * DSP Stream Operations. 642 */ 643 644int hda_dsp_stream_init(struct snd_sof_dev *sdev); 645void hda_dsp_stream_free(struct snd_sof_dev *sdev); 646int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 647 struct hdac_ext_stream *hext_stream, 648 struct snd_dma_buffer *dmab, 649 struct snd_pcm_hw_params *params); 650int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, 651 struct hdac_ext_stream *hext_stream, 652 struct snd_dma_buffer *dmab, 653 struct snd_pcm_hw_params *params); 654int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 655 struct hdac_ext_stream *hext_stream, int cmd); 656irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 657int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 658 struct snd_dma_buffer *dmab, 659 struct hdac_stream *hstream); 660bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 661bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); 662 663snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream, 664 int direction, bool can_sleep); 665u64 hda_dsp_get_stream_llp(struct snd_sof_dev *sdev, 666 struct snd_soc_component *component, 667 struct snd_pcm_substream *substream); 668u64 hda_dsp_get_stream_ldp(struct snd_sof_dev *sdev, 669 struct snd_soc_component *component, 670 struct snd_pcm_substream *substream); 671 672struct hdac_ext_stream * 673 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags); 674int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 675int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 676 struct hdac_ext_stream *hext_stream, 677 int enable, u32 size); 678 679int hda_ipc_msg_data(struct snd_sof_dev *sdev, 680 struct snd_sof_pcm_stream *sps, 681 void *p, size_t sz); 682int hda_set_stream_data_offset(struct snd_sof_dev *sdev, 683 struct snd_sof_pcm_stream *sps, 684 size_t posn_offset); 685 686/* 687 * DSP IPC Operations. 688 */ 689int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 690 struct snd_sof_ipc_msg *msg); 691void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 692int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 693int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 694 695irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 696int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 697 698/* 699 * DSP Code loader. 700 */ 701int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 702int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev); 703int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream); 704struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format, 705 unsigned int size, struct snd_dma_buffer *dmab, 706 int direction); 707int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 708 struct hdac_ext_stream *hext_stream); 709int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot); 710#define HDA_CL_STREAM_FORMAT 0x40 711 712/* pre and post fw run ops */ 713int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 714int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 715 716/* parse platform specific ext manifest ops */ 717int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, 718 const struct sof_ext_man_elem_header *hdr); 719 720/* 721 * HDA Controller Operations. 722 */ 723int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 724void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 725void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 726int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 727void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 728int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 729int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev); 730void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 731/* 732 * HDA bus operations. 733 */ 734void sof_hda_bus_init(struct snd_sof_dev *sdev, struct device *dev); 735void sof_hda_bus_exit(struct snd_sof_dev *sdev); 736 737#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 738/* 739 * HDA Codec operations. 740 */ 741void hda_codec_probe_bus(struct snd_sof_dev *sdev); 742void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable); 743void hda_codec_jack_check(struct snd_sof_dev *sdev); 744void hda_codec_check_for_state_change(struct snd_sof_dev *sdev); 745void hda_codec_init_cmd_io(struct snd_sof_dev *sdev); 746void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev); 747void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev); 748void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev); 749void hda_codec_detect_mask(struct snd_sof_dev *sdev); 750void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev); 751bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev); 752void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status); 753void hda_codec_device_remove(struct snd_sof_dev *sdev); 754 755#else 756 757static inline void hda_codec_probe_bus(struct snd_sof_dev *sdev) { } 758static inline void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable) { } 759static inline void hda_codec_jack_check(struct snd_sof_dev *sdev) { } 760static inline void hda_codec_check_for_state_change(struct snd_sof_dev *sdev) { } 761static inline void hda_codec_init_cmd_io(struct snd_sof_dev *sdev) { } 762static inline void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev) { } 763static inline void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev) { } 764static inline void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev) { } 765static inline void hda_codec_detect_mask(struct snd_sof_dev *sdev) { } 766static inline void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev) { } 767static inline bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev) { return false; } 768static inline void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status) { } 769static inline void hda_codec_device_remove(struct snd_sof_dev *sdev) { } 770 771#endif /* CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC */ 772 773#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) && IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 774 775void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); 776int hda_codec_i915_init(struct snd_sof_dev *sdev); 777int hda_codec_i915_exit(struct snd_sof_dev *sdev); 778 779#else 780 781static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable) { } 782static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 783static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 784 785#endif 786 787/* 788 * Trace Control. 789 */ 790int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 791 struct sof_ipc_dma_trace_params_ext *dtrace_params); 792int hda_dsp_trace_release(struct snd_sof_dev *sdev); 793int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 794 795/* 796 * SoundWire support 797 */ 798#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 799 800int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev); 801int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev); 802int hda_sdw_startup(struct snd_sof_dev *sdev); 803void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable); 804void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); 805bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev); 806void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); 807bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev); 808 809#else 810 811static inline int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) 812{ 813 return 0; 814} 815 816static inline int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev) 817{ 818 return 0; 819} 820 821static inline int hda_sdw_startup(struct snd_sof_dev *sdev) 822{ 823 return 0; 824} 825 826static inline void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 827{ 828} 829 830static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 831{ 832} 833 834static inline bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev) 835{ 836 return false; 837} 838 839static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 840{ 841} 842 843static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 844{ 845 return false; 846} 847 848#endif 849 850int sdw_hda_dai_hw_params(struct snd_pcm_substream *substream, 851 struct snd_pcm_hw_params *params, 852 struct snd_soc_dai *cpu_dai, 853 int link_id); 854 855int sdw_hda_dai_hw_free(struct snd_pcm_substream *substream, 856 struct snd_soc_dai *cpu_dai, 857 int link_id); 858 859int sdw_hda_dai_trigger(struct snd_pcm_substream *substream, int cmd, 860 struct snd_soc_dai *cpu_dai); 861 862/* common dai driver */ 863extern struct snd_soc_dai_driver skl_dai[]; 864int hda_dsp_dais_suspend(struct snd_sof_dev *sdev); 865 866/* 867 * Platform Specific HW abstraction Ops. 868 */ 869extern struct snd_sof_dsp_ops sof_hda_common_ops; 870 871extern struct snd_sof_dsp_ops sof_skl_ops; 872int sof_skl_ops_init(struct snd_sof_dev *sdev); 873extern struct snd_sof_dsp_ops sof_apl_ops; 874int sof_apl_ops_init(struct snd_sof_dev *sdev); 875extern struct snd_sof_dsp_ops sof_cnl_ops; 876int sof_cnl_ops_init(struct snd_sof_dev *sdev); 877extern struct snd_sof_dsp_ops sof_tgl_ops; 878int sof_tgl_ops_init(struct snd_sof_dev *sdev); 879extern struct snd_sof_dsp_ops sof_icl_ops; 880int sof_icl_ops_init(struct snd_sof_dev *sdev); 881extern struct snd_sof_dsp_ops sof_mtl_ops; 882int sof_mtl_ops_init(struct snd_sof_dev *sdev); 883extern struct snd_sof_dsp_ops sof_lnl_ops; 884int sof_lnl_ops_init(struct snd_sof_dev *sdev); 885 886extern const struct sof_intel_dsp_desc skl_chip_info; 887extern const struct sof_intel_dsp_desc apl_chip_info; 888extern const struct sof_intel_dsp_desc cnl_chip_info; 889extern const struct sof_intel_dsp_desc icl_chip_info; 890extern const struct sof_intel_dsp_desc tgl_chip_info; 891extern const struct sof_intel_dsp_desc tglh_chip_info; 892extern const struct sof_intel_dsp_desc ehl_chip_info; 893extern const struct sof_intel_dsp_desc jsl_chip_info; 894extern const struct sof_intel_dsp_desc adls_chip_info; 895extern const struct sof_intel_dsp_desc mtl_chip_info; 896extern const struct sof_intel_dsp_desc arl_s_chip_info; 897extern const struct sof_intel_dsp_desc lnl_chip_info; 898 899/* Probes support */ 900#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 901int hda_probes_register(struct snd_sof_dev *sdev); 902void hda_probes_unregister(struct snd_sof_dev *sdev); 903#else 904static inline int hda_probes_register(struct snd_sof_dev *sdev) 905{ 906 return 0; 907} 908 909static inline void hda_probes_unregister(struct snd_sof_dev *sdev) 910{ 911} 912#endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */ 913 914/* SOF client registration for HDA platforms */ 915int hda_register_clients(struct snd_sof_dev *sdev); 916void hda_unregister_clients(struct snd_sof_dev *sdev); 917 918/* machine driver select */ 919struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev); 920void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 921 struct snd_sof_dev *sdev); 922 923/* PCI driver selection and probe */ 924int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id); 925 926struct snd_sof_dai; 927struct sof_ipc_dai_config; 928 929#define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */ 930#define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */ 931#define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */ 932 933extern int sof_hda_position_quirk; 934 935void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops); 936void hda_ops_free(struct snd_sof_dev *sdev); 937 938/* SKL/KBL */ 939int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev); 940int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask); 941 942/* IPC4 */ 943irqreturn_t cnl_ipc4_irq_thread(int irq, void *context); 944int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); 945irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context); 946bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev); 947void hda_dsp_ipc4_schedule_d0i3_work(struct sof_intel_hda_dev *hdev, 948 struct snd_sof_ipc_msg *msg); 949int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); 950void hda_ipc4_dump(struct snd_sof_dev *sdev); 951extern struct sdw_intel_ops sdw_callback; 952 953struct sof_ipc4_fw_library; 954int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev, 955 struct sof_ipc4_fw_library *fw_lib, bool reload); 956 957/** 958 * struct hda_dai_widget_dma_ops - DAI DMA ops optional by default unless specified otherwise 959 * @get_hext_stream: Mandatory function pointer to get the saved pointer to struct hdac_ext_stream 960 * @assign_hext_stream: Function pointer to assign a hdac_ext_stream 961 * @release_hext_stream: Function pointer to release the hdac_ext_stream 962 * @setup_hext_stream: Function pointer for hdac_ext_stream setup 963 * @reset_hext_stream: Function pointer for hdac_ext_stream reset 964 * @pre_trigger: Function pointer for DAI DMA pre-trigger actions 965 * @trigger: Function pointer for DAI DMA trigger actions 966 * @post_trigger: Function pointer for DAI DMA post-trigger actions 967 * @codec_dai_set_stream: Function pointer to set codec-side stream information 968 * @calc_stream_format: Function pointer to determine stream format from hw_params and 969 * for HDaudio codec DAI from the .sig bits 970 * @get_hlink: Mandatory function pointer to retrieve hlink, mainly to program LOSIDV 971 * for legacy HDaudio links or program HDaudio Extended Link registers. 972 */ 973struct hda_dai_widget_dma_ops { 974 struct hdac_ext_stream *(*get_hext_stream)(struct snd_sof_dev *sdev, 975 struct snd_soc_dai *cpu_dai, 976 struct snd_pcm_substream *substream); 977 struct hdac_ext_stream *(*assign_hext_stream)(struct snd_sof_dev *sdev, 978 struct snd_soc_dai *cpu_dai, 979 struct snd_pcm_substream *substream); 980 void (*release_hext_stream)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 981 struct snd_pcm_substream *substream); 982 void (*setup_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream, 983 unsigned int format_val); 984 void (*reset_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_sream); 985 int (*pre_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 986 struct snd_pcm_substream *substream, int cmd); 987 int (*trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 988 struct snd_pcm_substream *substream, int cmd); 989 int (*post_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 990 struct snd_pcm_substream *substream, int cmd); 991 void (*codec_dai_set_stream)(struct snd_sof_dev *sdev, 992 struct snd_pcm_substream *substream, 993 struct hdac_stream *hstream); 994 unsigned int (*calc_stream_format)(struct snd_sof_dev *sdev, 995 struct snd_pcm_substream *substream, 996 struct snd_pcm_hw_params *params); 997 struct hdac_ext_link * (*get_hlink)(struct snd_sof_dev *sdev, 998 struct snd_pcm_substream *substream); 999}; 1000 1001const struct hda_dai_widget_dma_ops * 1002hda_select_dai_widget_ops(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget); 1003int hda_dai_config(struct snd_soc_dapm_widget *w, unsigned int flags, 1004 struct snd_sof_dai_config_data *data); 1005int hda_link_dma_cleanup(struct snd_pcm_substream *substream, struct hdac_ext_stream *hext_stream, 1006 struct snd_soc_dai *cpu_dai); 1007 1008#endif 1009