1// SPDX-License-Identifier: GPL-2.0 2// TLV320ADCX140 Sound driver 3// Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 4 5#ifndef _TLV320ADCX140_H 6#define _TLV320ADCX140_H 7 8#define ADCX140_RATES (SNDRV_PCM_RATE_44100 | \ 9 SNDRV_PCM_RATE_48000 | \ 10 SNDRV_PCM_RATE_96000 | \ 11 SNDRV_PCM_RATE_192000) 12 13#define ADCX140_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 14 SNDRV_PCM_FMTBIT_S20_3LE | \ 15 SNDRV_PCM_FMTBIT_S24_3LE | \ 16 SNDRV_PCM_FMTBIT_S24_LE | \ 17 SNDRV_PCM_FMTBIT_S32_LE) 18 19#define ADCX140_PAGE_SELECT 0x00 20#define ADCX140_SW_RESET 0x01 21#define ADCX140_SLEEP_CFG 0x02 22#define ADCX140_SHDN_CFG 0x05 23#define ADCX140_ASI_CFG0 0x07 24#define ADCX140_ASI_CFG1 0x08 25#define ADCX140_ASI_CFG2 0x09 26#define ADCX140_ASI_CH1 0x0b 27#define ADCX140_ASI_CH2 0x0c 28#define ADCX140_ASI_CH3 0x0d 29#define ADCX140_ASI_CH4 0x0e 30#define ADCX140_ASI_CH5 0x0f 31#define ADCX140_ASI_CH6 0x10 32#define ADCX140_ASI_CH7 0x11 33#define ADCX140_ASI_CH8 0x12 34#define ADCX140_MST_CFG0 0x13 35#define ADCX140_MST_CFG1 0x14 36#define ADCX140_ASI_STS 0x15 37#define ADCX140_CLK_SRC 0x16 38#define ADCX140_PDMCLK_CFG 0x1f 39#define ADCX140_PDM_CFG 0x20 40#define ADCX140_GPIO_CFG0 0x21 41#define ADCX140_GPO_CFG0 0x22 42#define ADCX140_GPO_CFG1 0x23 43#define ADCX140_GPO_CFG2 0x24 44#define ADCX140_GPO_CFG3 0x25 45#define ADCX140_GPO_VAL 0x29 46#define ADCX140_GPIO_MON 0x2a 47#define ADCX140_GPI_CFG0 0x2b 48#define ADCX140_GPI_CFG1 0x2c 49#define ADCX140_GPI_MON 0x2f 50#define ADCX140_INT_CFG 0x32 51#define ADCX140_INT_MASK0 0x33 52#define ADCX140_INT_LTCH0 0x36 53#define ADCX140_BIAS_CFG 0x3b 54#define ADCX140_CH1_CFG0 0x3c 55#define ADCX140_CH1_CFG1 0x3d 56#define ADCX140_CH1_CFG2 0x3e 57#define ADCX140_CH1_CFG3 0x3f 58#define ADCX140_CH1_CFG4 0x40 59#define ADCX140_CH2_CFG0 0x41 60#define ADCX140_CH2_CFG1 0x42 61#define ADCX140_CH2_CFG2 0x43 62#define ADCX140_CH2_CFG3 0x44 63#define ADCX140_CH2_CFG4 0x45 64#define ADCX140_CH3_CFG0 0x46 65#define ADCX140_CH3_CFG1 0x47 66#define ADCX140_CH3_CFG2 0x48 67#define ADCX140_CH3_CFG3 0x49 68#define ADCX140_CH3_CFG4 0x4a 69#define ADCX140_CH4_CFG0 0x4b 70#define ADCX140_CH4_CFG1 0x4c 71#define ADCX140_CH4_CFG2 0x4d 72#define ADCX140_CH4_CFG3 0x4e 73#define ADCX140_CH4_CFG4 0x4f 74#define ADCX140_CH5_CFG2 0x52 75#define ADCX140_CH5_CFG3 0x53 76#define ADCX140_CH5_CFG4 0x54 77#define ADCX140_CH6_CFG2 0x57 78#define ADCX140_CH6_CFG3 0x58 79#define ADCX140_CH6_CFG4 0x59 80#define ADCX140_CH7_CFG2 0x5c 81#define ADCX140_CH7_CFG3 0x5d 82#define ADCX140_CH7_CFG4 0x5e 83#define ADCX140_CH8_CFG2 0x61 84#define ADCX140_CH8_CFG3 0x62 85#define ADCX140_CH8_CFG4 0x63 86#define ADCX140_DSP_CFG0 0x6b 87#define ADCX140_DSP_CFG1 0x6c 88#define ADCX140_DRE_CFG0 0x6d 89#define ADCX140_AGC_CFG0 0x70 90#define ADCX140_IN_CH_EN 0x73 91#define ADCX140_ASI_OUT_CH_EN 0x74 92#define ADCX140_PWR_CFG 0x75 93#define ADCX140_DEV_STS0 0x76 94#define ADCX140_DEV_STS1 0x77 95#define ADCX140_PHASE_CALIB 0X7b 96 97#define ADCX140_RESET BIT(0) 98 99#define ADCX140_WAKE_DEV BIT(0) 100#define ADCX140_AREG_INTERNAL BIT(7) 101 102#define ADCX140_BCLKINV_BIT BIT(2) 103#define ADCX140_FSYNCINV_BIT BIT(3) 104#define ADCX140_INV_MSK (ADCX140_BCLKINV_BIT | ADCX140_FSYNCINV_BIT) 105#define ADCX140_BCLK_FSYNC_MASTER BIT(7) 106#define ADCX140_I2S_MODE_BIT BIT(6) 107#define ADCX140_LEFT_JUST_BIT BIT(7) 108#define ADCX140_ASI_FORMAT_MSK (ADCX140_I2S_MODE_BIT | ADCX140_LEFT_JUST_BIT) 109 110#define ADCX140_16_BIT_WORD 0x0 111#define ADCX140_20_BIT_WORD BIT(4) 112#define ADCX140_24_BIT_WORD BIT(5) 113#define ADCX140_32_BIT_WORD (BIT(4) | BIT(5)) 114#define ADCX140_WORD_LEN_MSK 0x30 115 116#define ADCX140_MAX_CHANNELS 8 117 118#define ADCX140_MIC_BIAS_VAL_VREF 0 119#define ADCX140_MIC_BIAS_VAL_VREF_1096 1 120#define ADCX140_MIC_BIAS_VAL_AVDD 6 121#define ADCX140_MIC_BIAS_VAL_MSK GENMASK(6, 4) 122#define ADCX140_MIC_BIAS_SHIFT 4 123 124#define ADCX140_MIC_BIAS_VREF_275V 0 125#define ADCX140_MIC_BIAS_VREF_25V 1 126#define ADCX140_MIC_BIAS_VREF_1375V 2 127#define ADCX140_MIC_BIAS_VREF_MSK GENMASK(1, 0) 128 129#define ADCX140_PWR_CTRL_MSK GENMASK(7, 5) 130#define ADCX140_PWR_CFG_BIAS_PDZ BIT(7) 131#define ADCX140_PWR_CFG_ADC_PDZ BIT(6) 132#define ADCX140_PWR_CFG_PLL_PDZ BIT(5) 133 134#define ADCX140_TX_OFFSET_MASK GENMASK(4, 0) 135 136#define ADCX140_NUM_PDM_EDGES 4 137#define ADCX140_PDM_EDGE_SHIFT 7 138 139#define ADCX140_NUM_GPI_PINS 4 140#define ADCX140_GPI_SHIFT 4 141#define ADCX140_GPI1_INDEX 0 142#define ADCX140_GPI2_INDEX 1 143#define ADCX140_GPI3_INDEX 2 144#define ADCX140_GPI4_INDEX 3 145 146#define ADCX140_NUM_GPOS 4 147#define ADCX140_NUM_GPO_CFGS 2 148#define ADCX140_GPO_SHIFT 4 149#define ADCX140_GPO_CFG_MAX 4 150#define ADCX140_GPO_DRV_MAX 5 151 152#define ADCX140_TX_FILL BIT(0) 153 154#define ADCX140_NUM_GPIO_CFGS 2 155#define ADCX140_GPIO_SHIFT 4 156#define ADCX140_GPIO_CFG_MAX 15 157#define ADCX140_GPIO_DRV_MAX 5 158 159#endif /* _TLV320ADCX140_ */ 160