1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) STMicroelectronics 2016 4 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> 5 */ 6 7#ifndef _LINUX_STM32_GPTIMER_H_ 8#define _LINUX_STM32_GPTIMER_H_ 9 10#include <linux/clk.h> 11#include <linux/dmaengine.h> 12#include <linux/dma-mapping.h> 13#include <linux/regmap.h> 14 15#define TIM_CR1 0x00 /* Control Register 1 */ 16#define TIM_CR2 0x04 /* Control Register 2 */ 17#define TIM_SMCR 0x08 /* Slave mode control reg */ 18#define TIM_DIER 0x0C /* DMA/interrupt register */ 19#define TIM_SR 0x10 /* Status register */ 20#define TIM_EGR 0x14 /* Event Generation Reg */ 21#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */ 22#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */ 23#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */ 24#define TIM_CNT 0x24 /* Counter */ 25#define TIM_PSC 0x28 /* Prescaler */ 26#define TIM_ARR 0x2c /* Auto-Reload Register */ 27#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */ 28#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */ 29#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */ 30#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */ 31#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ 32#define TIM_DCR 0x48 /* DMA control register */ 33#define TIM_DMAR 0x4C /* DMA register for transfer */ 34#define TIM_TISEL 0x68 /* Input Selection */ 35 36#define TIM_CR1_CEN BIT(0) /* Counter Enable */ 37#define TIM_CR1_DIR BIT(4) /* Counter Direction */ 38#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */ 39#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */ 40#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */ 41#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ 42#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ 43#define TIM_DIER_UIE BIT(0) /* Update interrupt */ 44#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ 45#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */ 46#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */ 47#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */ 48#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */ 49#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */ 50#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */ 51#define TIM_SR_UIF BIT(0) /* Update interrupt flag */ 52#define TIM_EGR_UG BIT(0) /* Update Generation */ 53#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ 54#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ 55#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */ 56#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */ 57#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */ 58#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */ 59#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */ 60#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */ 61#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */ 62#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */ 63#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ 64#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ 65#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ 66#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ 67#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ 68#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */ 69#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ 70#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */ 71#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ 72#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */ 73#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) 74#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */ 75#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */ 76#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */ 77#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ 78#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4)) 79#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */ 80#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */ 81 82#define MAX_TIM_PSC 0xFFFF 83#define MAX_TIM_ICPSC 0x3 84#define TIM_CR2_MMS_SHIFT 4 85#define TIM_CR2_MMS2_SHIFT 20 86#define TIM_SMCR_SMS_SLAVE_MODE_DISABLED 0 /* counts on internal clock when CEN=1 */ 87#define TIM_SMCR_SMS_ENCODER_MODE_1 1 /* counts TI1FP1 edges, depending on TI2FP2 level */ 88#define TIM_SMCR_SMS_ENCODER_MODE_2 2 /* counts TI2FP2 edges, depending on TI1FP1 level */ 89#define TIM_SMCR_SMS_ENCODER_MODE_3 3 /* counts on both TI1FP1 and TI2FP2 edges */ 90#define TIM_SMCR_TS_SHIFT 4 91#define TIM_BDTR_BKF_MASK 0xF 92#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4) 93 94enum stm32_timers_dmas { 95 STM32_TIMERS_DMA_CH1, 96 STM32_TIMERS_DMA_CH2, 97 STM32_TIMERS_DMA_CH3, 98 STM32_TIMERS_DMA_CH4, 99 STM32_TIMERS_DMA_UP, 100 STM32_TIMERS_DMA_TRIG, 101 STM32_TIMERS_DMA_COM, 102 STM32_TIMERS_MAX_DMAS, 103}; 104 105/* STM32 Timer may have either a unique global interrupt or 4 interrupt lines */ 106enum stm32_timers_irqs { 107 STM32_TIMERS_IRQ_GLOBAL_BRK, /* global or brk IRQ */ 108 STM32_TIMERS_IRQ_UP, 109 STM32_TIMERS_IRQ_TRG_COM, 110 STM32_TIMERS_IRQ_CC, 111 STM32_TIMERS_MAX_IRQS, 112}; 113 114/** 115 * struct stm32_timers_dma - STM32 timer DMA handling. 116 * @completion: end of DMA transfer completion 117 * @phys_base: control registers physical base address 118 * @lock: protect DMA access 119 * @chan: DMA channel in use 120 * @chans: DMA channels available for this timer instance 121 */ 122struct stm32_timers_dma { 123 struct completion completion; 124 phys_addr_t phys_base; 125 struct mutex lock; 126 struct dma_chan *chan; 127 struct dma_chan *chans[STM32_TIMERS_MAX_DMAS]; 128}; 129 130struct stm32_timers { 131 struct clk *clk; 132 struct regmap *regmap; 133 u32 max_arr; 134 struct stm32_timers_dma dma; /* Only to be used by the parent */ 135 unsigned int nr_irqs; 136 int irq[STM32_TIMERS_MAX_IRQS]; 137}; 138 139#if IS_REACHABLE(CONFIG_MFD_STM32_TIMERS) 140int stm32_timers_dma_burst_read(struct device *dev, u32 *buf, 141 enum stm32_timers_dmas id, u32 reg, 142 unsigned int num_reg, unsigned int bursts, 143 unsigned long tmo_ms); 144#else 145static inline int stm32_timers_dma_burst_read(struct device *dev, u32 *buf, 146 enum stm32_timers_dmas id, 147 u32 reg, 148 unsigned int num_reg, 149 unsigned int bursts, 150 unsigned long tmo_ms) 151{ 152 return -ENODEV; 153} 154#endif 155#endif 156