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1c7ea43f |
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29-Aug-2023 |
Fabrice Gasnier <fabrice.gasnier@foss.st.com> |
mfd: stm32-timers: Add support for interrupts There are two types of STM32 timers that may have: - a global interrupt line - 4 dedicated interrupt lines. Those interrupts are optional as defined in the dt-bindings. Enforce checks on either one, four or no interrupts are provided with their names. Optionally get them here, to be used by child devices. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20230829134029.2402868-5-fabrice.gasnier@foss.st.com Signed-off-by: Lee Jones <lee@kernel.org>
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d0a4564b |
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13-Dec-2022 |
Olivier Moysan <olivier.moysan@foss.st.com> |
pwm: stm32: Enforce settings for PWM capture The PWM capture assumes that the input selector is set to default input and that the slave mode is disabled. Force reset state for TISEL and SMCR registers to match this requirement. Note that slave mode disabling is not a pre-requisite by itself for capture mode, as hardware supports it for PWM capture. However, the current implementation of the driver does not allow slave mode for PWM capture. Setting slave mode for PWM capture results in wrong capture values. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Acked-by: Lee Jones <lee@kernel.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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ea434ff8 |
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26-Aug-2021 |
William Breathitt Gray <vilhelm.gray@gmail.com> |
counter: stm32-timer-cnt: Provide defines for slave mode selection The STM32 timer permits configuration of the counter encoder mode via the slave mode control register (SMCR) slave mode selection (SMS) bits. This patch provides preprocessor defines for the supported encoder modes. Cc: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/ad3d9cd7af580d586316d368f74964cbc394f981.1630031207.git.vilhelm.gray@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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8e536225 |
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15-Oct-2019 |
Thierry Reding <thierry.reding@gmail.com> |
pwm: stm32: Remove clutter from ternary operator Remove usage of the ternary operator to assign values for register fields. Instead, parameterize the register and field offset macros and pass the index to them. This removes clutter and improves readability. Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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d95c9760 |
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18-May-2018 |
Fabrice Gasnier <fabrice.gasnier@st.com> |
mfd: stm32-timers: Fix pwm-stm32 linker issue with COMPILE_TEST This is seen when COMPILE_TEST=y and MFD_STM32_TIMERS=n. drivers/pwm/pwm-stm32.o: In function 'stm32_pwm_raw_capture': pwm-stm32.c:... undefined reference to 'stm32_timers_dma_burst_read' Fixes: 0c6609805b63 ("mfd: stm32-timers: Add support for DMAs") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reported-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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ab3a8978 |
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16-May-2018 |
Fabrice Gasnier <fabrice.gasnier@st.com> |
pwm: stm32: Use input prescaler to improve period capture Using input prescaler, capture unit will trigger DMA once every configurable /2, /4 or /8 events (rising edge). This helps improve period (only) capture accuracy at high rates. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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53e38fe7 |
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16-May-2018 |
Fabrice Gasnier <fabrice.gasnier@st.com> |
pwm: stm32: Add capture support Add support for PMW input mode on pwm-stm32. STM32 timers support period and duty cycle capture as long as they have at least two PWM channels. One capture channel is used for period (rising-edge), one for duty-cycle (falling-edge). When there's only one channel available, only period can be captured. Duty-cycle is simply zero'ed in such a case. Capture requires exclusive access (e.g. no pwm output running at the same time, to protect common prescaler). Timer DMA burst mode (from MFD core) is being used, to take two snapshots of capture registers (upon each period rising edge). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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0c660980 |
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16-May-2018 |
Fabrice Gasnier <fabrice.gasnier@st.com> |
mfd: stm32-timers: Add support for DMAs STM32 Timers can support up to 7 DMA requests: - 4 channels, update, compare and trigger. Optionally request part, or all DMAs from stm32-timers MFD core. Also add routine to implement burst reads using DMA from timer registers. This is exported. So, it can be used by child drivers, PWM capture for instance (but not limited to). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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fa93f5b7 |
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05-Dec-2017 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
mfd: stm32: Adopt SPDX identifier Add SPDX identifier Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Philippe Ombredanne <pombredanne@nexb.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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6fb34812 |
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02-May-2017 |
Fabrice Gasnier <fabrice.gasnier@st.com> |
iio: stm32 trigger: Add support for TRGO2 triggers Add support for TRGO2 trigger that can be found on STM32F7. Add additional master modes supported by TRGO2. Register additional "tim[1/8]_trgo2" triggers for timer1 & timer8. Detect TRGO2 timer capability (master mode selection 2). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Acked-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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4adec7da |
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04-Apr-2017 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
iio: stm32 trigger: Add quadrature encoder device One of the features of STM32 trigger hardware block is a quadrature encoder that can counts up/down depending of the levels and edges of the selected external pins. This patch allow to read/write the counter, get it direction, set/get quadrature modes and get scale factor. When counting up preset value is the limit of the counter. When counting down the counter start from preset value down to 0. This preset value could be set/get by using /sys/bus/iio/devices/iio:deviceX/in_count0_preset attribute. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Reviewed-by: William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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d0f949e2 |
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20-Jan-2017 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
mfd: Add STM32 Timers driver This hardware block could at used at same time for PWM generation and IIO timers. PWM and IIO timer configuration are mixed in the same registers so we need a multi fonction driver to be able to share those registers. version 7: - rebase on v4.10-rc2 version 6: - rename files to stm32-timers - rename functions to stm32_timers_xxx version 5: - fix Lee comments about detect function - add missing dependency on REGMAP_MMIO version 4: - add a function to detect Auto Reload Register (ARR) size - rename the structure shared with other drivers version 2: - rename driver "stm32-gptimer" to be align with SoC documentation - only keep one compatible - use of_platform_populate() instead of devm_mfd_add_devices() Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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