1// SPDX-License-Identifier: GPL-2.0
2//
3// CS42L43 SPI Controller Driver
4//
5// Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6//                         Cirrus Logic International Semiconductor Ltd.
7
8#include <linux/bits.h>
9#include <linux/bitfield.h>
10#include <linux/device.h>
11#include <linux/errno.h>
12#include <linux/mfd/cs42l43.h>
13#include <linux/mfd/cs42l43-regs.h>
14#include <linux/mod_devicetable.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/regmap.h>
20#include <linux/spi/spi.h>
21#include <linux/units.h>
22
23#define CS42L43_FIFO_SIZE		16
24#define CS42L43_SPI_ROOT_HZ		(40 * HZ_PER_MHZ)
25#define CS42L43_SPI_MAX_LENGTH		65532
26
27enum cs42l43_spi_cmd {
28	CS42L43_WRITE,
29	CS42L43_READ
30};
31
32struct cs42l43_spi {
33	struct device *dev;
34	struct regmap *regmap;
35	struct spi_controller *ctlr;
36};
37
38static const unsigned int cs42l43_clock_divs[] = {
39	2, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
40};
41
42static int cs42l43_spi_tx(struct regmap *regmap, const u8 *buf, unsigned int len)
43{
44	const u8 *end = buf + len;
45	u32 val = 0;
46	int ret;
47
48	while (buf < end) {
49		const u8 *block = min(buf + CS42L43_FIFO_SIZE, end);
50
51		while (buf < block) {
52			const u8 *word = min(buf + sizeof(u32), block);
53			int pad = (buf + sizeof(u32)) - word;
54
55			while (buf < word) {
56				val >>= BITS_PER_BYTE;
57				val |= FIELD_PREP(GENMASK(31, 24), *buf);
58
59				buf++;
60			}
61
62			val >>= pad * BITS_PER_BYTE;
63
64			regmap_write(regmap, CS42L43_TX_DATA, val);
65		}
66
67		regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_TX_DONE_MASK);
68
69		ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,
70					       val, (val & CS42L43_SPI_TX_REQUEST_MASK),
71					       1000, 5000);
72		if (ret)
73			return ret;
74	}
75
76	return 0;
77}
78
79static int cs42l43_spi_rx(struct regmap *regmap, u8 *buf, unsigned int len)
80{
81	u8 *end = buf + len;
82	u32 val;
83	int ret;
84
85	while (buf < end) {
86		u8 *block = min(buf + CS42L43_FIFO_SIZE, end);
87
88		ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,
89					       val, (val & CS42L43_SPI_RX_REQUEST_MASK),
90					       1000, 5000);
91		if (ret)
92			return ret;
93
94		while (buf < block) {
95			u8 *word = min(buf + sizeof(u32), block);
96
97			ret = regmap_read(regmap, CS42L43_RX_DATA, &val);
98			if (ret)
99				return ret;
100
101			while (buf < word) {
102				*buf = FIELD_GET(GENMASK(7, 0), val);
103
104				val >>= BITS_PER_BYTE;
105				buf++;
106			}
107		}
108
109		regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_RX_DONE_MASK);
110	}
111
112	return 0;
113}
114
115static int cs42l43_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,
116				struct spi_transfer *tfr)
117{
118	struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);
119	int i, ret = -EINVAL;
120
121	for (i = 0; i < ARRAY_SIZE(cs42l43_clock_divs); i++) {
122		if (CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[i] <= tfr->speed_hz)
123			break;
124	}
125
126	if (i == ARRAY_SIZE(cs42l43_clock_divs))
127		return -EINVAL;
128
129	regmap_write(priv->regmap, CS42L43_SPI_CLK_CONFIG1, i);
130
131	if (tfr->tx_buf) {
132		regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_WRITE);
133		regmap_write(priv->regmap, CS42L43_TRAN_CONFIG4, tfr->len - 1);
134	} else if (tfr->rx_buf) {
135		regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_READ);
136		regmap_write(priv->regmap, CS42L43_TRAN_CONFIG5, tfr->len - 1);
137	}
138
139	regmap_write(priv->regmap, CS42L43_TRAN_CONFIG1, CS42L43_SPI_START_MASK);
140
141	if (tfr->tx_buf)
142		ret = cs42l43_spi_tx(priv->regmap, (const u8 *)tfr->tx_buf, tfr->len);
143	else if (tfr->rx_buf)
144		ret = cs42l43_spi_rx(priv->regmap, (u8 *)tfr->rx_buf, tfr->len);
145
146	return ret;
147}
148
149static void cs42l43_set_cs(struct spi_device *spi, bool is_high)
150{
151	struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);
152
153	regmap_write(priv->regmap, CS42L43_SPI_CONFIG2, !is_high);
154}
155
156static int cs42l43_prepare_message(struct spi_controller *ctlr, struct spi_message *msg)
157{
158	struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
159	struct spi_device *spi = msg->spi;
160	unsigned int spi_config1 = 0;
161
162	/* select another internal CS, which doesn't exist, so CS 0 is not used */
163	if (spi_get_csgpiod(spi, 0))
164		spi_config1 |= 1 << CS42L43_SPI_SS_SEL_SHIFT;
165	if (spi->mode & SPI_CPOL)
166		spi_config1 |= CS42L43_SPI_CPOL_MASK;
167	if (spi->mode & SPI_CPHA)
168		spi_config1 |= CS42L43_SPI_CPHA_MASK;
169	if (spi->mode & SPI_3WIRE)
170		spi_config1 |= CS42L43_SPI_THREE_WIRE_MASK;
171
172	regmap_write(priv->regmap, CS42L43_SPI_CONFIG1, spi_config1);
173
174	return 0;
175}
176
177static int cs42l43_prepare_transfer_hardware(struct spi_controller *ctlr)
178{
179	struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
180	int ret;
181
182	ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, CS42L43_SPI_MSTR_EN_MASK);
183	if (ret)
184		dev_err(priv->dev, "Failed to enable SPI controller: %d\n", ret);
185
186	return ret;
187}
188
189static int cs42l43_unprepare_transfer_hardware(struct spi_controller *ctlr)
190{
191	struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
192	int ret;
193
194	ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, 0);
195	if (ret)
196		dev_err(priv->dev, "Failed to disable SPI controller: %d\n", ret);
197
198	return ret;
199}
200
201static size_t cs42l43_spi_max_length(struct spi_device *spi)
202{
203	return CS42L43_SPI_MAX_LENGTH;
204}
205
206static void cs42l43_release_of_node(void *data)
207{
208	fwnode_handle_put(data);
209}
210
211static int cs42l43_spi_probe(struct platform_device *pdev)
212{
213	struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
214	struct cs42l43_spi *priv;
215	struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev);
216	int ret;
217
218	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
219	if (!priv)
220		return -ENOMEM;
221
222	priv->ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*priv->ctlr));
223	if (!priv->ctlr)
224		return -ENOMEM;
225
226	spi_controller_set_devdata(priv->ctlr, priv);
227
228	priv->dev = &pdev->dev;
229	priv->regmap = cs42l43->regmap;
230
231	priv->ctlr->prepare_message = cs42l43_prepare_message;
232	priv->ctlr->prepare_transfer_hardware = cs42l43_prepare_transfer_hardware;
233	priv->ctlr->unprepare_transfer_hardware = cs42l43_unprepare_transfer_hardware;
234	priv->ctlr->transfer_one = cs42l43_transfer_one;
235	priv->ctlr->set_cs = cs42l43_set_cs;
236	priv->ctlr->max_transfer_size = cs42l43_spi_max_length;
237	priv->ctlr->mode_bits = SPI_3WIRE | SPI_MODE_X_MASK;
238	priv->ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
239	priv->ctlr->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
240					 SPI_BPW_MASK(32);
241	priv->ctlr->min_speed_hz = CS42L43_SPI_ROOT_HZ /
242				   cs42l43_clock_divs[ARRAY_SIZE(cs42l43_clock_divs) - 1];
243	priv->ctlr->max_speed_hz = CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[0];
244	priv->ctlr->use_gpio_descriptors = true;
245	priv->ctlr->auto_runtime_pm = true;
246
247	ret = devm_pm_runtime_enable(priv->dev);
248	if (ret)
249		return ret;
250
251	pm_runtime_idle(priv->dev);
252
253	regmap_write(priv->regmap, CS42L43_TRAN_CONFIG6, CS42L43_FIFO_SIZE - 1);
254	regmap_write(priv->regmap, CS42L43_TRAN_CONFIG7, CS42L43_FIFO_SIZE - 1);
255
256	// Disable Watchdog timer and enable stall
257	regmap_write(priv->regmap, CS42L43_SPI_CONFIG3, 0);
258	regmap_write(priv->regmap, CS42L43_SPI_CONFIG4, CS42L43_SPI_STALL_ENA_MASK);
259
260	if (is_of_node(fwnode)) {
261		fwnode = fwnode_get_named_child_node(fwnode, "spi");
262		ret = devm_add_action(priv->dev, cs42l43_release_of_node, fwnode);
263		if (ret) {
264			fwnode_handle_put(fwnode);
265			return ret;
266		}
267	}
268
269	device_set_node(&priv->ctlr->dev, fwnode);
270
271	ret = devm_spi_register_controller(priv->dev, priv->ctlr);
272	if (ret) {
273		dev_err(priv->dev, "Failed to register SPI controller: %d\n", ret);
274	}
275
276	return ret;
277}
278
279static const struct platform_device_id cs42l43_spi_id_table[] = {
280	{ "cs42l43-spi", },
281	{}
282};
283MODULE_DEVICE_TABLE(platform, cs42l43_spi_id_table);
284
285static struct platform_driver cs42l43_spi_driver = {
286	.driver = {
287		.name	= "cs42l43-spi",
288	},
289	.probe		= cs42l43_spi_probe,
290	.id_table	= cs42l43_spi_id_table,
291};
292module_platform_driver(cs42l43_spi_driver);
293
294MODULE_DESCRIPTION("CS42L43 SPI Driver");
295MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
296MODULE_AUTHOR("Maciej Strozek <mstrozek@opensource.cirrus.com>");
297MODULE_LICENSE("GPL");
298