1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2019 MediaTek Inc. 4 */ 5 6#ifndef __RPROC_MTK_COMMON_H 7#define __RPROC_MTK_COMMON_H 8 9#include <linux/interrupt.h> 10#include <linux/kernel.h> 11#include <linux/platform_device.h> 12#include <linux/remoteproc.h> 13#include <linux/remoteproc/mtk_scp.h> 14 15#define MT8183_SW_RSTN 0x0 16#define MT8183_SW_RSTN_BIT BIT(0) 17#define MT8183_SCP_TO_HOST 0x1C 18#define MT8183_SCP_IPC_INT_BIT BIT(0) 19#define MT8183_SCP_WDT_INT_BIT BIT(8) 20#define MT8183_HOST_TO_SCP 0x28 21#define MT8183_HOST_IPC_INT_BIT BIT(0) 22#define MT8183_WDT_CFG 0x84 23#define MT8183_SCP_CLK_SW_SEL 0x4000 24#define MT8183_SCP_CLK_DIV_SEL 0x4024 25#define MT8183_SCP_SRAM_PDN 0x402C 26#define MT8183_SCP_L1_SRAM_PD 0x4080 27#define MT8183_SCP_TCM_TAIL_SRAM_PD 0x4094 28 29#define MT8183_SCP_CACHE_SEL(x) (0x14000 + (x) * 0x3000) 30#define MT8183_SCP_CACHE_CON MT8183_SCP_CACHE_SEL(0) 31#define MT8183_SCP_DCACHE_CON MT8183_SCP_CACHE_SEL(1) 32#define MT8183_SCP_CACHESIZE_8KB BIT(8) 33#define MT8183_SCP_CACHE_CON_WAYEN BIT(10) 34 35#define MT8186_SCP_L1_SRAM_PD_P1 0x40B0 36#define MT8186_SCP_L1_SRAM_PD_p2 0x40B4 37 38#define MT8192_L2TCM_SRAM_PD_0 0x10C0 39#define MT8192_L2TCM_SRAM_PD_1 0x10C4 40#define MT8192_L2TCM_SRAM_PD_2 0x10C8 41#define MT8192_L1TCM_SRAM_PDN 0x102C 42#define MT8192_CPU0_SRAM_PD 0x1080 43 44#define MT8192_SCP2APMCU_IPC_SET 0x4080 45#define MT8192_SCP2APMCU_IPC_CLR 0x4084 46#define MT8192_SCP_IPC_INT_BIT BIT(0) 47#define MT8192_SCP2SPM_IPC_CLR 0x4094 48#define MT8192_GIPC_IN_SET 0x4098 49#define MT8192_HOST_IPC_INT_BIT BIT(0) 50#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4) 51 52#define MT8192_CORE0_SW_RSTN_CLR 0x10000 53#define MT8192_CORE0_SW_RSTN_SET 0x10004 54#define MT8192_CORE0_MEM_ATT_PREDEF 0x10008 55#define MT8192_CORE0_WDT_IRQ 0x10030 56#define MT8192_CORE0_WDT_CFG 0x10034 57 58#define MT8195_SYS_STATUS 0x4004 59#define MT8195_CORE0_WDT BIT(16) 60#define MT8195_CORE1_WDT BIT(17) 61 62#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) 63 64#define MT8195_CPU1_SRAM_PD 0x1084 65#define MT8195_SSHUB2APMCU_IPC_SET 0x4088 66#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C 67#define MT8195_CORE1_SW_RSTN_CLR 0x20000 68#define MT8195_CORE1_SW_RSTN_SET 0x20004 69#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 70#define MT8195_CORE1_WDT_IRQ 0x20030 71#define MT8195_CORE1_WDT_CFG 0x20034 72 73#define MT8195_SEC_CTRL 0x85000 74#define MT8195_CORE_OFFSET_ENABLE_D BIT(13) 75#define MT8195_CORE_OFFSET_ENABLE_I BIT(12) 76#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0 77#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4 78#define MT8195_L2TCM_OFFSET 0x850d0 79 80#define SCP_FW_VER_LEN 32 81#define SCP_SHARE_BUFFER_SIZE 288 82 83struct scp_run { 84 u32 signaled; 85 s8 fw_ver[SCP_FW_VER_LEN]; 86 u32 dec_capability; 87 u32 enc_capability; 88 wait_queue_head_t wq; 89}; 90 91struct scp_ipi_desc { 92 /* For protecting handler. */ 93 struct mutex lock; 94 scp_ipi_handler_t handler; 95 void *priv; 96}; 97 98struct mtk_scp; 99 100struct mtk_scp_of_data { 101 int (*scp_clk_get)(struct mtk_scp *scp); 102 int (*scp_before_load)(struct mtk_scp *scp); 103 void (*scp_irq_handler)(struct mtk_scp *scp); 104 void (*scp_reset_assert)(struct mtk_scp *scp); 105 void (*scp_reset_deassert)(struct mtk_scp *scp); 106 void (*scp_stop)(struct mtk_scp *scp); 107 void *(*scp_da_to_va)(struct mtk_scp *scp, u64 da, size_t len); 108 109 u32 host_to_scp_reg; 110 u32 host_to_scp_int_bit; 111 112 size_t ipi_buf_offset; 113}; 114 115struct mtk_scp_of_cluster { 116 void __iomem *reg_base; 117 void __iomem *l1tcm_base; 118 size_t l1tcm_size; 119 phys_addr_t l1tcm_phys; 120 struct list_head mtk_scp_list; 121 /* Prevent concurrent operations of this structure and L2TCM power control. */ 122 struct mutex cluster_lock; 123 u32 l2tcm_refcnt; 124}; 125 126struct mtk_scp { 127 struct device *dev; 128 struct rproc *rproc; 129 struct clk *clk; 130 void __iomem *sram_base; 131 size_t sram_size; 132 phys_addr_t sram_phys; 133 134 const struct mtk_scp_of_data *data; 135 136 struct mtk_share_obj __iomem *recv_buf; 137 struct mtk_share_obj __iomem *send_buf; 138 struct scp_run run; 139 /* To prevent multiple ipi_send run concurrently. */ 140 struct mutex send_lock; 141 struct scp_ipi_desc ipi_desc[SCP_IPI_MAX]; 142 bool ipi_id_ack[SCP_IPI_MAX]; 143 wait_queue_head_t ack_wq; 144 145 void *cpu_addr; 146 dma_addr_t dma_addr; 147 size_t dram_size; 148 149 struct rproc_subdev *rpmsg_subdev; 150 151 struct list_head elem; 152 struct mtk_scp_of_cluster *cluster; 153}; 154 155/** 156 * struct mtk_share_obj - SRAM buffer shared with AP and SCP 157 * 158 * @id: IPI id 159 * @len: share buffer length 160 * @share_buf: share buffer data 161 */ 162struct mtk_share_obj { 163 u32 id; 164 u32 len; 165 u8 share_buf[SCP_SHARE_BUFFER_SIZE]; 166}; 167 168void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int len); 169void scp_ipi_lock(struct mtk_scp *scp, u32 id); 170void scp_ipi_unlock(struct mtk_scp *scp, u32 id); 171 172#endif 173