1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com> 4 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 5 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 6 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 7 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 8 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 9 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 10 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 11 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> 12 <http://rt2x00.serialmonkey.com> 13 14 */ 15 16/* 17 Module: rt2800 18 Abstract: Data structures and registers for the rt2800 modules. 19 Supported chipsets: RT2800E, RT2800ED & RT2800U. 20 */ 21 22#ifndef RT2800_H 23#define RT2800_H 24 25/* 26 * RF chip defines. 27 * 28 * RF2820 2.4G 2T3R 29 * RF2850 2.4G/5G 2T3R 30 * RF2720 2.4G 1T2R 31 * RF2750 2.4G/5G 1T2R 32 * RF3020 2.4G 1T1R 33 * RF2020 2.4G B/G 34 * RF3021 2.4G 1T2R 35 * RF3022 2.4G 2T2R 36 * RF3052 2.4G/5G 2T2R 37 * RF2853 2.4G/5G 3T3R 38 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390) 39 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392) 40 * RF3053 2.4G/5G 3T3R(RT3563/RT3573/RT3593) 41 * RF3853 2.4G/5G 3T3R(RT3883/RT3662) 42 * RF5592 2.4G/5G 2T2R 43 * RF3070 2.4G 1T1R 44 * RF5360 2.4G 1T1R 45 * RF5362 2.4G 1T1R 46 * RF5370 2.4G 1T1R 47 * RF5390 2.4G 1T1R 48 */ 49#define RF2820 0x0001 50#define RF2850 0x0002 51#define RF2720 0x0003 52#define RF2750 0x0004 53#define RF3020 0x0005 54#define RF2020 0x0006 55#define RF3021 0x0007 56#define RF3022 0x0008 57#define RF3052 0x0009 58#define RF2853 0x000a 59#define RF3320 0x000b 60#define RF3322 0x000c 61#define RF3053 0x000d 62#define RF5592 0x000f 63#define RF3070 0x3070 64#define RF3290 0x3290 65#define RF3853 0x3853 66#define RF5350 0x5350 67#define RF5360 0x5360 68#define RF5362 0x5362 69#define RF5370 0x5370 70#define RF5372 0x5372 71#define RF5390 0x5390 72#define RF5392 0x5392 73#define RF7620 0x7620 74 75/* 76 * Chipset revisions. 77 */ 78#define REV_RT2860C 0x0100 79#define REV_RT2860D 0x0101 80#define REV_RT2872E 0x0200 81#define REV_RT3070E 0x0200 82#define REV_RT3070F 0x0201 83#define REV_RT3071E 0x0211 84#define REV_RT3090E 0x0211 85#define REV_RT3390E 0x0211 86#define REV_RT3593E 0x0211 87#define REV_RT5390F 0x0502 88#define REV_RT5370G 0x0503 89#define REV_RT5390R 0x1502 90#define REV_RT5592C 0x0221 91 92#define DEFAULT_RSSI_OFFSET 120 93 94/* 95 * Register layout information. 96 */ 97#define CSR_REG_BASE 0x1000 98#define CSR_REG_SIZE 0x0800 99#define EEPROM_BASE 0x0000 100#define EEPROM_SIZE 0x0200 101#define BBP_BASE 0x0000 102#define BBP_SIZE 0x00ff 103#define RF_BASE 0x0004 104#define RF_SIZE 0x0010 105#define RFCSR_BASE 0x0000 106#define RFCSR_SIZE 0x0040 107 108/* 109 * Number of TX queues. 110 */ 111#define NUM_TX_QUEUES 4 112 113/* 114 * Registers. 115 */ 116 117 118/* 119 * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number. 120 */ 121#define MAC_CSR0_3290 0x0000 122 123/* 124 * E2PROM_CSR: PCI EEPROM control register. 125 * RELOAD: Write 1 to reload eeprom content. 126 * TYPE: 0: 93c46, 1:93c66. 127 * LOAD_STATUS: 1:loading, 0:done. 128 */ 129#define E2PROM_CSR 0x0004 130#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001) 131#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002) 132#define E2PROM_CSR_DATA_IN FIELD32(0x00000004) 133#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008) 134#define E2PROM_CSR_TYPE FIELD32(0x00000030) 135#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040) 136#define E2PROM_CSR_RELOAD FIELD32(0x00000080) 137 138/* 139 * CMB_CTRL_CFG 140 */ 141#define CMB_CTRL 0x0020 142#define AUX_OPT_BIT0 FIELD32(0x00000001) 143#define AUX_OPT_BIT1 FIELD32(0x00000002) 144#define AUX_OPT_BIT2 FIELD32(0x00000004) 145#define AUX_OPT_BIT3 FIELD32(0x00000008) 146#define AUX_OPT_BIT4 FIELD32(0x00000010) 147#define AUX_OPT_BIT5 FIELD32(0x00000020) 148#define AUX_OPT_BIT6 FIELD32(0x00000040) 149#define AUX_OPT_BIT7 FIELD32(0x00000080) 150#define AUX_OPT_BIT8 FIELD32(0x00000100) 151#define AUX_OPT_BIT9 FIELD32(0x00000200) 152#define AUX_OPT_BIT10 FIELD32(0x00000400) 153#define AUX_OPT_BIT11 FIELD32(0x00000800) 154#define AUX_OPT_BIT12 FIELD32(0x00001000) 155#define AUX_OPT_BIT13 FIELD32(0x00002000) 156#define AUX_OPT_BIT14 FIELD32(0x00004000) 157#define AUX_OPT_BIT15 FIELD32(0x00008000) 158#define LDO25_LEVEL FIELD32(0x00030000) 159#define LDO25_LARGEA FIELD32(0x00040000) 160#define LDO25_FRC_ON FIELD32(0x00080000) 161#define CMB_RSV FIELD32(0x00300000) 162#define XTAL_RDY FIELD32(0x00400000) 163#define PLL_LD FIELD32(0x00800000) 164#define LDO_CORE_LEVEL FIELD32(0x0F000000) 165#define LDO_BGSEL FIELD32(0x30000000) 166#define LDO3_EN FIELD32(0x40000000) 167#define LDO0_EN FIELD32(0x80000000) 168 169/* 170 * EFUSE_CSR_3290: RT3290 EEPROM 171 */ 172#define EFUSE_CTRL_3290 0x0024 173 174/* 175 * EFUSE_DATA3 of 3290 176 */ 177#define EFUSE_DATA3_3290 0x0028 178 179/* 180 * EFUSE_DATA2 of 3290 181 */ 182#define EFUSE_DATA2_3290 0x002c 183 184/* 185 * EFUSE_DATA1 of 3290 186 */ 187#define EFUSE_DATA1_3290 0x0030 188 189/* 190 * EFUSE_DATA0 of 3290 191 */ 192#define EFUSE_DATA0_3290 0x0034 193 194/* 195 * OSC_CTRL_CFG 196 * Ring oscillator configuration 197 */ 198#define OSC_CTRL 0x0038 199#define OSC_REF_CYCLE FIELD32(0x00001fff) 200#define OSC_RSV FIELD32(0x0000e000) 201#define OSC_CAL_CNT FIELD32(0x0fff0000) 202#define OSC_CAL_ACK FIELD32(0x10000000) 203#define OSC_CLK_32K_VLD FIELD32(0x20000000) 204#define OSC_CAL_REQ FIELD32(0x40000000) 205#define OSC_ROSC_EN FIELD32(0x80000000) 206 207/* 208 * COEX_CFG_0 209 */ 210#define COEX_CFG0 0x0040 211#define COEX_CFG_ANT FIELD32(0xff000000) 212/* 213 * COEX_CFG_1 214 */ 215#define COEX_CFG1 0x0044 216 217/* 218 * COEX_CFG_2 219 */ 220#define COEX_CFG2 0x0048 221#define BT_COEX_CFG1 FIELD32(0xff000000) 222#define BT_COEX_CFG0 FIELD32(0x00ff0000) 223#define WL_COEX_CFG1 FIELD32(0x0000ff00) 224#define WL_COEX_CFG0 FIELD32(0x000000ff) 225/* 226 * PLL_CTRL_CFG 227 * PLL configuration register 228 */ 229#define PLL_CTRL 0x0050 230#define PLL_RESERVED_INPUT1 FIELD32(0x000000ff) 231#define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00) 232#define PLL_CONTROL FIELD32(0x00070000) 233#define PLL_LPF_R1 FIELD32(0x00080000) 234#define PLL_LPF_C1_CTRL FIELD32(0x00300000) 235#define PLL_LPF_C2_CTRL FIELD32(0x00c00000) 236#define PLL_CP_CURRENT_CTRL FIELD32(0x03000000) 237#define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000) 238#define PLL_LOCK_CTRL FIELD32(0x70000000) 239#define PLL_VBGBK_EN FIELD32(0x80000000) 240 241 242/* 243 * WLAN_CTRL_CFG 244 * RT3290 wlan configuration 245 */ 246#define WLAN_FUN_CTRL 0x0080 247#define WLAN_EN FIELD32(0x00000001) 248#define WLAN_CLK_EN FIELD32(0x00000002) 249#define WLAN_RSV1 FIELD32(0x00000004) 250#define WLAN_RESET FIELD32(0x00000008) 251#define PCIE_APP0_CLK_REQ FIELD32(0x00000010) 252#define FRC_WL_ANT_SET FIELD32(0x00000020) 253#define INV_TR_SW0 FIELD32(0x00000040) 254#define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100) 255#define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200) 256#define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400) 257#define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800) 258#define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000) 259#define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000) 260#define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000) 261#define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000) 262#define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00) 263#define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000) 264#define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000) 265#define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000) 266#define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000) 267#define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000) 268#define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000) 269#define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000) 270#define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000) 271#define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000) 272#define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000) 273#define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000) 274#define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000) 275#define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000) 276#define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000) 277#define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000) 278#define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000) 279#define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000) 280#define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000) 281 282/* 283 * AUX_CTRL: Aux/PCI-E related configuration 284 */ 285#define AUX_CTRL 0x10c 286#define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002) 287#define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400) 288 289/* 290 * OPT_14: Unknown register used by rt3xxx devices. 291 */ 292#define OPT_14_CSR 0x0114 293#define OPT_14_CSR_BIT0 FIELD32(0x00000001) 294 295/* 296 * INT_SOURCE_CSR: Interrupt source register. 297 * Write one to clear corresponding bit. 298 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO 299 */ 300#define INT_SOURCE_CSR 0x0200 301#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001) 302#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002) 303#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004) 304#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008) 305#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010) 306#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020) 307#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040) 308#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080) 309#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100) 310#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200) 311#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400) 312#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800) 313#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000) 314#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000) 315#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000) 316#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000) 317#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000) 318#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000) 319 320/* 321 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. 322 */ 323#define INT_MASK_CSR 0x0204 324#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001) 325#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002) 326#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004) 327#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008) 328#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010) 329#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020) 330#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040) 331#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080) 332#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100) 333#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200) 334#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400) 335#define INT_MASK_CSR_TBTT FIELD32(0x00000800) 336#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000) 337#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000) 338#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000) 339#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000) 340#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000) 341#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000) 342 343/* 344 * WPDMA_GLO_CFG 345 */ 346#define WPDMA_GLO_CFG 0x0208 347#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001) 348#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002) 349#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004) 350#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008) 351#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030) 352#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040) 353#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080) 354#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00) 355#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000) 356 357/* 358 * WPDMA_RST_IDX 359 */ 360#define WPDMA_RST_IDX 0x020c 361#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001) 362#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002) 363#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004) 364#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008) 365#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010) 366#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020) 367#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000) 368 369/* 370 * DELAY_INT_CFG 371 */ 372#define DELAY_INT_CFG 0x0210 373#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff) 374#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00) 375#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000) 376#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000) 377#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000) 378#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000) 379 380/* 381 * WMM_AIFSN_CFG: Aifsn for each EDCA AC 382 * AIFSN0: AC_VO 383 * AIFSN1: AC_VI 384 * AIFSN2: AC_BE 385 * AIFSN3: AC_BK 386 */ 387#define WMM_AIFSN_CFG 0x0214 388#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f) 389#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0) 390#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00) 391#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000) 392 393/* 394 * WMM_CWMIN_CSR: CWmin for each EDCA AC 395 * CWMIN0: AC_VO 396 * CWMIN1: AC_VI 397 * CWMIN2: AC_BE 398 * CWMIN3: AC_BK 399 */ 400#define WMM_CWMIN_CFG 0x0218 401#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f) 402#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0) 403#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00) 404#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000) 405 406/* 407 * WMM_CWMAX_CSR: CWmax for each EDCA AC 408 * CWMAX0: AC_VO 409 * CWMAX1: AC_VI 410 * CWMAX2: AC_BE 411 * CWMAX3: AC_BK 412 */ 413#define WMM_CWMAX_CFG 0x021c 414#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f) 415#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0) 416#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00) 417#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000) 418 419/* 420 * AC_TXOP0: AC_VO/AC_VI TXOP register 421 * AC0TXOP: AC_VO in unit of 32us 422 * AC1TXOP: AC_VI in unit of 32us 423 */ 424#define WMM_TXOP0_CFG 0x0220 425#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff) 426#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000) 427 428/* 429 * AC_TXOP1: AC_BE/AC_BK TXOP register 430 * AC2TXOP: AC_BE in unit of 32us 431 * AC3TXOP: AC_BK in unit of 32us 432 */ 433#define WMM_TXOP1_CFG 0x0224 434#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff) 435#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000) 436 437/* 438 * GPIO_CTRL: 439 * GPIO_CTRL_VALx: GPIO value 440 * GPIO_CTRL_DIRx: GPIO direction: 0 = output; 1 = input 441 */ 442#define GPIO_CTRL 0x0228 443#define GPIO_CTRL_VAL0 FIELD32(0x00000001) 444#define GPIO_CTRL_VAL1 FIELD32(0x00000002) 445#define GPIO_CTRL_VAL2 FIELD32(0x00000004) 446#define GPIO_CTRL_VAL3 FIELD32(0x00000008) 447#define GPIO_CTRL_VAL4 FIELD32(0x00000010) 448#define GPIO_CTRL_VAL5 FIELD32(0x00000020) 449#define GPIO_CTRL_VAL6 FIELD32(0x00000040) 450#define GPIO_CTRL_VAL7 FIELD32(0x00000080) 451#define GPIO_CTRL_DIR0 FIELD32(0x00000100) 452#define GPIO_CTRL_DIR1 FIELD32(0x00000200) 453#define GPIO_CTRL_DIR2 FIELD32(0x00000400) 454#define GPIO_CTRL_DIR3 FIELD32(0x00000800) 455#define GPIO_CTRL_DIR4 FIELD32(0x00001000) 456#define GPIO_CTRL_DIR5 FIELD32(0x00002000) 457#define GPIO_CTRL_DIR6 FIELD32(0x00004000) 458#define GPIO_CTRL_DIR7 FIELD32(0x00008000) 459#define GPIO_CTRL_VAL8 FIELD32(0x00010000) 460#define GPIO_CTRL_VAL9 FIELD32(0x00020000) 461#define GPIO_CTRL_VAL10 FIELD32(0x00040000) 462#define GPIO_CTRL_DIR8 FIELD32(0x01000000) 463#define GPIO_CTRL_DIR9 FIELD32(0x02000000) 464#define GPIO_CTRL_DIR10 FIELD32(0x04000000) 465 466/* 467 * MCU_CMD_CFG 468 */ 469#define MCU_CMD_CFG 0x022c 470 471/* 472 * AC_VO register offsets 473 */ 474#define TX_BASE_PTR0 0x0230 475#define TX_MAX_CNT0 0x0234 476#define TX_CTX_IDX0 0x0238 477#define TX_DTX_IDX0 0x023c 478 479/* 480 * AC_VI register offsets 481 */ 482#define TX_BASE_PTR1 0x0240 483#define TX_MAX_CNT1 0x0244 484#define TX_CTX_IDX1 0x0248 485#define TX_DTX_IDX1 0x024c 486 487/* 488 * AC_BE register offsets 489 */ 490#define TX_BASE_PTR2 0x0250 491#define TX_MAX_CNT2 0x0254 492#define TX_CTX_IDX2 0x0258 493#define TX_DTX_IDX2 0x025c 494 495/* 496 * AC_BK register offsets 497 */ 498#define TX_BASE_PTR3 0x0260 499#define TX_MAX_CNT3 0x0264 500#define TX_CTX_IDX3 0x0268 501#define TX_DTX_IDX3 0x026c 502 503/* 504 * HCCA register offsets 505 */ 506#define TX_BASE_PTR4 0x0270 507#define TX_MAX_CNT4 0x0274 508#define TX_CTX_IDX4 0x0278 509#define TX_DTX_IDX4 0x027c 510 511/* 512 * MGMT register offsets 513 */ 514#define TX_BASE_PTR5 0x0280 515#define TX_MAX_CNT5 0x0284 516#define TX_CTX_IDX5 0x0288 517#define TX_DTX_IDX5 0x028c 518 519/* 520 * RX register offsets 521 */ 522#define RX_BASE_PTR 0x0290 523#define RX_MAX_CNT 0x0294 524#define RX_CRX_IDX 0x0298 525#define RX_DRX_IDX 0x029c 526 527/* 528 * USB_DMA_CFG 529 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns. 530 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes. 531 * PHY_CLEAR: phy watch dog enable. 532 * TX_CLEAR: Clear USB DMA TX path. 533 * TXOP_HALT: Halt TXOP count down when TX buffer is full. 534 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation. 535 * RX_BULK_EN: Enable USB DMA Rx. 536 * TX_BULK_EN: Enable USB DMA Tx. 537 * EP_OUT_VALID: OUT endpoint data valid. 538 * RX_BUSY: USB DMA RX FSM busy. 539 * TX_BUSY: USB DMA TX FSM busy. 540 */ 541#define USB_DMA_CFG 0x02a0 542#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff) 543#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00) 544#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000) 545#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000) 546#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000) 547#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000) 548#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000) 549#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000) 550#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000) 551#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000) 552#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000) 553 554/* 555 * US_CYC_CNT 556 * BT_MODE_EN: Bluetooth mode enable 557 * CLOCK CYCLE: Clock cycle count in 1us. 558 * PCI:0x21, PCIE:0x7d, USB:0x1e 559 */ 560#define US_CYC_CNT 0x02a4 561#define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100) 562#define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff) 563 564/* 565 * PBF_SYS_CTRL 566 * HOST_RAM_WRITE: enable Host program ram write selection 567 */ 568#define PBF_SYS_CTRL 0x0400 569#define PBF_SYS_CTRL_READY FIELD32(0x00000080) 570#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000) 571 572/* 573 * HOST-MCU shared memory 574 */ 575#define HOST_CMD_CSR 0x0404 576#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff) 577 578/* 579 * PBF registers 580 * Most are for debug. Driver doesn't touch PBF register. 581 */ 582#define PBF_CFG 0x0408 583#define PBF_MAX_PCNT 0x040c 584#define PBF_CTRL 0x0410 585#define PBF_INT_STA 0x0414 586#define PBF_INT_ENA 0x0418 587 588/* 589 * BCN_OFFSET0: 590 */ 591#define BCN_OFFSET0 0x042c 592#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff) 593#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00) 594#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000) 595#define BCN_OFFSET0_BCN3 FIELD32(0xff000000) 596 597/* 598 * BCN_OFFSET1: 599 */ 600#define BCN_OFFSET1 0x0430 601#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff) 602#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00) 603#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000) 604#define BCN_OFFSET1_BCN7 FIELD32(0xff000000) 605 606/* 607 * TXRXQ_PCNT: PBF register 608 * PCNT_TX0Q: Page count for TX hardware queue 0 609 * PCNT_TX1Q: Page count for TX hardware queue 1 610 * PCNT_TX2Q: Page count for TX hardware queue 2 611 * PCNT_RX0Q: Page count for RX hardware queue 612 */ 613#define TXRXQ_PCNT 0x0438 614#define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff) 615#define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00) 616#define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000) 617#define TXRXQ_PCNT_RX0Q FIELD32(0xff000000) 618 619/* 620 * PBF register 621 * Debug. Driver doesn't touch PBF register. 622 */ 623#define PBF_DBG 0x043c 624 625/* 626 * RF registers 627 */ 628#define RF_CSR_CFG 0x0500 629#define RF_CSR_CFG_DATA FIELD32(0x000000ff) 630#define RF_CSR_CFG_REGNUM FIELD32(0x00003f00) 631#define RF_CSR_CFG_WRITE FIELD32(0x00010000) 632#define RF_CSR_CFG_BUSY FIELD32(0x00020000) 633 634/* 635 * MT7620 RF registers (reversed order) 636 */ 637#define RF_CSR_CFG_DATA_MT7620 FIELD32(0x0000ff00) 638#define RF_CSR_CFG_REGNUM_MT7620 FIELD32(0x03ff0000) 639#define RF_CSR_CFG_WRITE_MT7620 FIELD32(0x00000010) 640#define RF_CSR_CFG_BUSY_MT7620 FIELD32(0x00000001) 641 642/* undocumented registers for calibration of new MAC */ 643#define RF_CONTROL0 0x0518 644#define RF_BYPASS0 0x051c 645#define RF_CONTROL1 0x0520 646#define RF_BYPASS1 0x0524 647#define RF_CONTROL2 0x0528 648#define RF_BYPASS2 0x052c 649#define RF_CONTROL3 0x0530 650#define RF_BYPASS3 0x0534 651 652/* 653 * EFUSE_CSR: RT30x0 EEPROM 654 */ 655#define EFUSE_CTRL 0x0580 656#define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000) 657#define EFUSE_CTRL_MODE FIELD32(0x000000c0) 658#define EFUSE_CTRL_KICK FIELD32(0x40000000) 659#define EFUSE_CTRL_PRESENT FIELD32(0x80000000) 660 661/* 662 * EFUSE_DATA0 663 */ 664#define EFUSE_DATA0 0x0590 665 666/* 667 * EFUSE_DATA1 668 */ 669#define EFUSE_DATA1 0x0594 670 671/* 672 * EFUSE_DATA2 673 */ 674#define EFUSE_DATA2 0x0598 675 676/* 677 * EFUSE_DATA3 678 */ 679#define EFUSE_DATA3 0x059c 680 681/* 682 * LDO_CFG0 683 */ 684#define LDO_CFG0 0x05d4 685#define LDO_CFG0_DELAY3 FIELD32(0x000000ff) 686#define LDO_CFG0_DELAY2 FIELD32(0x0000ff00) 687#define LDO_CFG0_DELAY1 FIELD32(0x00ff0000) 688#define LDO_CFG0_BGSEL FIELD32(0x03000000) 689#define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000) 690#define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000) 691#define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000) 692 693/* 694 * GPIO_SWITCH 695 */ 696#define GPIO_SWITCH 0x05dc 697#define GPIO_SWITCH_0 FIELD32(0x00000001) 698#define GPIO_SWITCH_1 FIELD32(0x00000002) 699#define GPIO_SWITCH_2 FIELD32(0x00000004) 700#define GPIO_SWITCH_3 FIELD32(0x00000008) 701#define GPIO_SWITCH_4 FIELD32(0x00000010) 702#define GPIO_SWITCH_5 FIELD32(0x00000020) 703#define GPIO_SWITCH_6 FIELD32(0x00000040) 704#define GPIO_SWITCH_7 FIELD32(0x00000080) 705 706/* 707 * FIXME: where the DEBUG_INDEX name come from? 708 */ 709#define MAC_DEBUG_INDEX 0x05e8 710#define MAC_DEBUG_INDEX_XTAL FIELD32(0x80000000) 711 712/* 713 * MAC Control/Status Registers(CSR). 714 * Some values are set in TU, whereas 1 TU == 1024 us. 715 */ 716 717/* 718 * MAC_CSR0: ASIC revision number. 719 * ASIC_REV: 0 720 * ASIC_VER: 2860 or 2870 721 */ 722#define MAC_CSR0 0x1000 723#define MAC_CSR0_REVISION FIELD32(0x0000ffff) 724#define MAC_CSR0_CHIPSET FIELD32(0xffff0000) 725 726/* 727 * MAC_SYS_CTRL: 728 */ 729#define MAC_SYS_CTRL 0x1004 730#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001) 731#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002) 732#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004) 733#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008) 734#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010) 735#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020) 736#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040) 737#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080) 738 739/* 740 * MAC_ADDR_DW0: STA MAC register 0 741 */ 742#define MAC_ADDR_DW0 0x1008 743#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff) 744#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00) 745#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000) 746#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000) 747 748/* 749 * MAC_ADDR_DW1: STA MAC register 1 750 * UNICAST_TO_ME_MASK: 751 * Used to mask off bits from byte 5 of the MAC address 752 * to determine the UNICAST_TO_ME bit for RX frames. 753 * The full mask is complemented by BSS_ID_MASK: 754 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK 755 */ 756#define MAC_ADDR_DW1 0x100c 757#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff) 758#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00) 759#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000) 760 761/* 762 * MAC_BSSID_DW0: BSSID register 0 763 */ 764#define MAC_BSSID_DW0 0x1010 765#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff) 766#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00) 767#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000) 768#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000) 769 770/* 771 * MAC_BSSID_DW1: BSSID register 1 772 * BSS_ID_MASK: 773 * 0: 1-BSSID mode (BSS index = 0) 774 * 1: 2-BSSID mode (BSS index: Byte5, bit 0) 775 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1) 776 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2) 777 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the 778 * BSSID. This will make sure that those bits will be ignored 779 * when determining the MY_BSS of RX frames. 780 */ 781#define MAC_BSSID_DW1 0x1014 782#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff) 783#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00) 784#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000) 785#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000) 786 787/* 788 * MAX_LEN_CFG: Maximum frame length register. 789 * MAX_MPDU: rt2860b max 16k bytes 790 * MAX_PSDU: Maximum PSDU length 791 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 792 */ 793#define MAX_LEN_CFG 0x1018 794#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff) 795#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000) 796#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000) 797#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000) 798 799/* 800 * BBP_CSR_CFG: BBP serial control register 801 * VALUE: Register value to program into BBP 802 * REG_NUM: Selected BBP register 803 * READ_CONTROL: 0 write BBP, 1 read BBP 804 * BUSY: ASIC is busy executing BBP commands 805 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks 806 * BBP_RW_MODE: 0 serial, 1 parallel 807 */ 808#define BBP_CSR_CFG 0x101c 809#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff) 810#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00) 811#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000) 812#define BBP_CSR_CFG_BUSY FIELD32(0x00020000) 813#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000) 814#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000) 815 816/* 817 * RF_CSR_CFG0: RF control register 818 * REGID_AND_VALUE: Register value to program into RF 819 * BITWIDTH: Selected RF register 820 * STANDBYMODE: 0 high when standby, 1 low when standby 821 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate 822 * BUSY: ASIC is busy executing RF commands 823 */ 824#define RF_CSR_CFG0 0x1020 825#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff) 826#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000) 827#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff) 828#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000) 829#define RF_CSR_CFG0_SEL FIELD32(0x40000000) 830#define RF_CSR_CFG0_BUSY FIELD32(0x80000000) 831 832/* 833 * RF_CSR_CFG1: RF control register 834 * REGID_AND_VALUE: Register value to program into RF 835 * RFGAP: Gap between BB_CONTROL_RF and RF_LE 836 * 0: 3 system clock cycle (37.5usec) 837 * 1: 5 system clock cycle (62.5usec) 838 */ 839#define RF_CSR_CFG1 0x1024 840#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff) 841#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000) 842 843/* 844 * RF_CSR_CFG2: RF control register 845 * VALUE: Register value to program into RF 846 */ 847#define RF_CSR_CFG2 0x1028 848#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff) 849 850/* 851 * LED_CFG: LED control 852 * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1) 853 * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1) 854 * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2) 855 * color LED's: 856 * 0: off 857 * 1: blinking upon TX2 858 * 2: periodic slow blinking 859 * 3: always on 860 * LED polarity: 861 * 0: active low 862 * 1: active high 863 */ 864#define LED_CFG 0x102c 865#define LED_CFG_ON_PERIOD FIELD32(0x000000ff) 866#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00) 867#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000) 868#define LED_CFG_R_LED_MODE FIELD32(0x03000000) 869#define LED_CFG_G_LED_MODE FIELD32(0x0c000000) 870#define LED_CFG_Y_LED_MODE FIELD32(0x30000000) 871#define LED_CFG_LED_POLAR FIELD32(0x40000000) 872 873/* 874 * AMPDU_MAX_LEN_20M1S: Per MCS max A-MPDU length, 20 MHz, MCS 0-7 875 * AMPDU_MAX_LEN_20M2S: Per MCS max A-MPDU length, 20 MHz, MCS 8-15 876 * AMPDU_MAX_LEN_40M1S: Per MCS max A-MPDU length, 40 MHz, MCS 0-7 877 * AMPDU_MAX_LEN_40M2S: Per MCS max A-MPDU length, 40 MHz, MCS 8-15 878 * Maximum A-MPDU length = 2^(AMPDU_MAX - 5) kilobytes 879 */ 880#define AMPDU_MAX_LEN_20M1S 0x1030 881#define AMPDU_MAX_LEN_20M2S 0x1034 882#define AMPDU_MAX_LEN_40M1S 0x1038 883#define AMPDU_MAX_LEN_40M2S 0x103C 884 885/* 886 * AMPDU_BA_WINSIZE: Force BlockAck window size 887 * FORCE_WINSIZE_ENABLE: 888 * 0: Disable forcing of BlockAck window size 889 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck 890 * window size values in the TXWI 891 * FORCE_WINSIZE: BlockAck window size 892 */ 893#define AMPDU_BA_WINSIZE 0x1040 894#define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020) 895#define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f) 896 897/* 898 * XIFS_TIME_CFG: MAC timing 899 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX 900 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX 901 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX 902 * when MAC doesn't reference BBP signal BBRXEND 903 * EIFS: unit 1us 904 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer 905 * 906 */ 907#define XIFS_TIME_CFG 0x1100 908#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff) 909#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00) 910#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000) 911#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000) 912#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000) 913 914/* 915 * BKOFF_SLOT_CFG: 916 */ 917#define BKOFF_SLOT_CFG 0x1104 918#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff) 919#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00) 920 921/* 922 * NAV_TIME_CFG: 923 */ 924#define NAV_TIME_CFG 0x1108 925#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff) 926#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00) 927#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000) 928#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000) 929 930/* 931 * CH_TIME_CFG: count as channel busy 932 * EIFS_BUSY: Count EIFS as channel busy 933 * NAV_BUSY: Count NAS as channel busy 934 * RX_BUSY: Count RX as channel busy 935 * TX_BUSY: Count TX as channel busy 936 * TMR_EN: Enable channel statistics timer 937 */ 938#define CH_TIME_CFG 0x110c 939#define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010) 940#define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008) 941#define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004) 942#define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002) 943#define CH_TIME_CFG_TMR_EN FIELD32(0x00000001) 944 945/* 946 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us 947 */ 948#define PBF_LIFE_TIMER 0x1110 949 950/* 951 * BCN_TIME_CFG: 952 * BEACON_INTERVAL: in unit of 1/16 TU 953 * TSF_TICKING: Enable TSF auto counting 954 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode 955 * BEACON_GEN: Enable beacon generator 956 */ 957#define BCN_TIME_CFG 0x1114 958#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff) 959#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000) 960#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000) 961#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000) 962#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000) 963#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000) 964 965/* 966 * TBTT_SYNC_CFG: 967 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots 968 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots 969 */ 970#define TBTT_SYNC_CFG 0x1118 971#define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff) 972#define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00) 973#define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000) 974#define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000) 975 976/* 977 * TSF_TIMER_DW0: Local lsb TSF timer, read-only 978 */ 979#define TSF_TIMER_DW0 0x111c 980#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff) 981 982/* 983 * TSF_TIMER_DW1: Local msb TSF timer, read-only 984 */ 985#define TSF_TIMER_DW1 0x1120 986#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff) 987 988/* 989 * TBTT_TIMER: TImer remains till next TBTT, read-only 990 */ 991#define TBTT_TIMER 0x1124 992 993/* 994 * INT_TIMER_CFG: timer configuration 995 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU 996 * GP_TIMER: period of general purpose timer in units of 1/16 TU 997 */ 998#define INT_TIMER_CFG 0x1128 999#define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff) 1000#define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000) 1001 1002/* 1003 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable 1004 */ 1005#define INT_TIMER_EN 0x112c 1006#define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001) 1007#define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002) 1008 1009/* 1010 * CH_IDLE_STA: channel idle time (in us) 1011 */ 1012#define CH_IDLE_STA 0x1130 1013 1014/* 1015 * CH_BUSY_STA: channel busy time on primary channel (in us) 1016 */ 1017#define CH_BUSY_STA 0x1134 1018 1019/* 1020 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us) 1021 */ 1022#define CH_BUSY_STA_SEC 0x1138 1023 1024/* 1025 * MAC_STATUS_CFG: 1026 * BBP_RF_BUSY: When set to 0, BBP and RF are stable. 1027 * if 1 or higher one of the 2 registers is busy. 1028 */ 1029#define MAC_STATUS_CFG 0x1200 1030#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003) 1031#define MAC_STATUS_CFG_BBP_RF_BUSY_TX FIELD32(0x00000001) 1032#define MAC_STATUS_CFG_BBP_RF_BUSY_RX FIELD32(0x00000002) 1033 1034/* 1035 * PWR_PIN_CFG: 1036 */ 1037#define PWR_PIN_CFG 0x1204 1038 1039/* 1040 * AUTOWAKEUP_CFG: Manual power control / status register 1041 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set 1042 * AUTOWAKE: 0:sleep, 1:awake 1043 */ 1044#define AUTOWAKEUP_CFG 0x1208 1045#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff) 1046#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00) 1047#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000) 1048 1049/* 1050 * MIMO_PS_CFG: MIMO Power-save Configuration 1051 */ 1052#define MIMO_PS_CFG 0x1210 1053#define MIMO_PS_CFG_MMPS_BB_EN FIELD32(0x00000001) 1054#define MIMO_PS_CFG_MMPS_RX_ANT_NUM FIELD32(0x00000006) 1055#define MIMO_PS_CFG_MMPS_RF_EN FIELD32(0x00000008) 1056#define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010) 1057#define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020) 1058 1059/* 1060 * EDCA_AC0_CFG: 1061 */ 1062#define EDCA_AC0_CFG 0x1300 1063#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff) 1064#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00) 1065#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000) 1066#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000) 1067 1068/* 1069 * EDCA_AC1_CFG: 1070 */ 1071#define EDCA_AC1_CFG 0x1304 1072#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff) 1073#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00) 1074#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000) 1075#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000) 1076 1077/* 1078 * EDCA_AC2_CFG: 1079 */ 1080#define EDCA_AC2_CFG 0x1308 1081#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff) 1082#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00) 1083#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000) 1084#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000) 1085 1086/* 1087 * EDCA_AC3_CFG: 1088 */ 1089#define EDCA_AC3_CFG 0x130c 1090#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff) 1091#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00) 1092#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000) 1093#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000) 1094 1095/* 1096 * EDCA_TID_AC_MAP: 1097 */ 1098#define EDCA_TID_AC_MAP 0x1310 1099 1100/* 1101 * TX_PWR_CFG: 1102 */ 1103#define TX_PWR_CFG_RATE0 FIELD32(0x0000000f) 1104#define TX_PWR_CFG_RATE1 FIELD32(0x000000f0) 1105#define TX_PWR_CFG_RATE2 FIELD32(0x00000f00) 1106#define TX_PWR_CFG_RATE3 FIELD32(0x0000f000) 1107#define TX_PWR_CFG_RATE4 FIELD32(0x000f0000) 1108#define TX_PWR_CFG_RATE5 FIELD32(0x00f00000) 1109#define TX_PWR_CFG_RATE6 FIELD32(0x0f000000) 1110#define TX_PWR_CFG_RATE7 FIELD32(0xf0000000) 1111 1112/* 1113 * TX_PWR_CFG_0: 1114 */ 1115#define TX_PWR_CFG_0 0x1314 1116#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f) 1117#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0) 1118#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00) 1119#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000) 1120#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000) 1121#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000) 1122#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000) 1123#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000) 1124/* bits for 3T devices */ 1125#define TX_PWR_CFG_0_CCK1_CH0 FIELD32(0x0000000f) 1126#define TX_PWR_CFG_0_CCK1_CH1 FIELD32(0x000000f0) 1127#define TX_PWR_CFG_0_CCK5_CH0 FIELD32(0x00000f00) 1128#define TX_PWR_CFG_0_CCK5_CH1 FIELD32(0x0000f000) 1129#define TX_PWR_CFG_0_OFDM6_CH0 FIELD32(0x000f0000) 1130#define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000) 1131#define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000) 1132#define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000) 1133/* bits for new 2T devices */ 1134#define TX_PWR_CFG_0B_1MBS_2MBS FIELD32(0x000000ff) 1135#define TX_PWR_CFG_0B_5MBS_11MBS FIELD32(0x0000ff00) 1136#define TX_PWR_CFG_0B_6MBS_9MBS FIELD32(0x00ff0000) 1137#define TX_PWR_CFG_0B_12MBS_18MBS FIELD32(0xff000000) 1138 1139 1140/* 1141 * TX_PWR_CFG_1: 1142 */ 1143#define TX_PWR_CFG_1 0x1318 1144#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f) 1145#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0) 1146#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00) 1147#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000) 1148#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000) 1149#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000) 1150#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000) 1151#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000) 1152/* bits for 3T devices */ 1153#define TX_PWR_CFG_1_OFDM24_CH0 FIELD32(0x0000000f) 1154#define TX_PWR_CFG_1_OFDM24_CH1 FIELD32(0x000000f0) 1155#define TX_PWR_CFG_1_OFDM48_CH0 FIELD32(0x00000f00) 1156#define TX_PWR_CFG_1_OFDM48_CH1 FIELD32(0x0000f000) 1157#define TX_PWR_CFG_1_MCS0_CH0 FIELD32(0x000f0000) 1158#define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000) 1159#define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000) 1160#define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000) 1161/* bits for new 2T devices */ 1162#define TX_PWR_CFG_1B_24MBS_36MBS FIELD32(0x000000ff) 1163#define TX_PWR_CFG_1B_48MBS FIELD32(0x0000ff00) 1164#define TX_PWR_CFG_1B_MCS0_MCS1 FIELD32(0x00ff0000) 1165#define TX_PWR_CFG_1B_MCS2_MCS3 FIELD32(0xff000000) 1166 1167/* 1168 * TX_PWR_CFG_2: 1169 */ 1170#define TX_PWR_CFG_2 0x131c 1171#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f) 1172#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0) 1173#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00) 1174#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000) 1175#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000) 1176#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000) 1177#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000) 1178#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000) 1179/* bits for 3T devices */ 1180#define TX_PWR_CFG_2_MCS4_CH0 FIELD32(0x0000000f) 1181#define TX_PWR_CFG_2_MCS4_CH1 FIELD32(0x000000f0) 1182#define TX_PWR_CFG_2_MCS6_CH0 FIELD32(0x00000f00) 1183#define TX_PWR_CFG_2_MCS6_CH1 FIELD32(0x0000f000) 1184#define TX_PWR_CFG_2_MCS8_CH0 FIELD32(0x000f0000) 1185#define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000) 1186#define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000) 1187#define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000) 1188/* bits for new 2T devices */ 1189#define TX_PWR_CFG_2B_MCS4_MCS5 FIELD32(0x000000ff) 1190#define TX_PWR_CFG_2B_MCS6_MCS7 FIELD32(0x0000ff00) 1191#define TX_PWR_CFG_2B_MCS8_MCS9 FIELD32(0x00ff0000) 1192#define TX_PWR_CFG_2B_MCS10_MCS11 FIELD32(0xff000000) 1193 1194/* 1195 * TX_PWR_CFG_3: 1196 */ 1197#define TX_PWR_CFG_3 0x1320 1198#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f) 1199#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0) 1200#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00) 1201#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000) 1202#define TX_PWR_CFG_3_UNKNOWN1 FIELD32(0x000f0000) 1203#define TX_PWR_CFG_3_UNKNOWN2 FIELD32(0x00f00000) 1204#define TX_PWR_CFG_3_UNKNOWN3 FIELD32(0x0f000000) 1205#define TX_PWR_CFG_3_UNKNOWN4 FIELD32(0xf0000000) 1206/* bits for 3T devices */ 1207#define TX_PWR_CFG_3_MCS12_CH0 FIELD32(0x0000000f) 1208#define TX_PWR_CFG_3_MCS12_CH1 FIELD32(0x000000f0) 1209#define TX_PWR_CFG_3_MCS14_CH0 FIELD32(0x00000f00) 1210#define TX_PWR_CFG_3_MCS14_CH1 FIELD32(0x0000f000) 1211#define TX_PWR_CFG_3_STBC0_CH0 FIELD32(0x000f0000) 1212#define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000) 1213#define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000) 1214#define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000) 1215/* bits for new 2T devices */ 1216#define TX_PWR_CFG_3B_MCS12_MCS13 FIELD32(0x000000ff) 1217#define TX_PWR_CFG_3B_MCS14 FIELD32(0x0000ff00) 1218#define TX_PWR_CFG_3B_STBC_MCS0_MCS1 FIELD32(0x00ff0000) 1219#define TX_PWR_CFG_3B_STBC_MCS2_MSC3 FIELD32(0xff000000) 1220 1221/* 1222 * TX_PWR_CFG_4: 1223 */ 1224#define TX_PWR_CFG_4 0x1324 1225#define TX_PWR_CFG_4_UNKNOWN5 FIELD32(0x0000000f) 1226#define TX_PWR_CFG_4_UNKNOWN6 FIELD32(0x000000f0) 1227#define TX_PWR_CFG_4_UNKNOWN7 FIELD32(0x00000f00) 1228#define TX_PWR_CFG_4_UNKNOWN8 FIELD32(0x0000f000) 1229/* bits for 3T devices */ 1230#define TX_PWR_CFG_4_STBC4_CH0 FIELD32(0x0000000f) 1231#define TX_PWR_CFG_4_STBC4_CH1 FIELD32(0x000000f0) 1232#define TX_PWR_CFG_4_STBC6_CH0 FIELD32(0x00000f00) 1233#define TX_PWR_CFG_4_STBC6_CH1 FIELD32(0x0000f000) 1234/* bits for new 2T devices */ 1235#define TX_PWR_CFG_4B_STBC_MCS4_MCS5 FIELD32(0x000000ff) 1236#define TX_PWR_CFG_4B_STBC_MCS6 FIELD32(0x0000ff00) 1237 1238/* 1239 * TX_PIN_CFG: 1240 */ 1241#define TX_PIN_CFG 0x1328 1242#define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0 1243#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001) 1244#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002) 1245#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004) 1246#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008) 1247#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010) 1248#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020) 1249#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040) 1250#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080) 1251#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100) 1252#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200) 1253#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400) 1254#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800) 1255#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000) 1256#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000) 1257#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000) 1258#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000) 1259#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000) 1260#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000) 1261#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000) 1262#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000) 1263#define TX_PIN_CFG_RFRX_EN FIELD32(0x00100000) 1264#define TX_PIN_CFG_RFRX_POL FIELD32(0x00200000) 1265#define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000) 1266#define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000) 1267#define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000) 1268#define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000) 1269#define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000) 1270#define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000) 1271#define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000) 1272#define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000) 1273 1274/* 1275 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz 1276 */ 1277#define TX_BAND_CFG 0x132c 1278#define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001) 1279#define TX_BAND_CFG_A FIELD32(0x00000002) 1280#define TX_BAND_CFG_BG FIELD32(0x00000004) 1281 1282/* 1283 * TX_SW_CFG0: 1284 */ 1285#define TX_SW_CFG0 0x1330 1286 1287/* 1288 * TX_SW_CFG1: 1289 */ 1290#define TX_SW_CFG1 0x1334 1291 1292/* 1293 * TX_SW_CFG2: 1294 */ 1295#define TX_SW_CFG2 0x1338 1296 1297/* 1298 * TXOP_THRES_CFG: 1299 */ 1300#define TXOP_THRES_CFG 0x133c 1301 1302/* 1303 * TXOP_CTRL_CFG: 1304 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation 1305 * AC_TRUN_EN: Enable/Disable truncation for AC change 1306 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change 1307 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode 1308 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS 1309 * RESERVED_TRUN_EN: Reserved 1310 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection 1311 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz 1312 * transmissions if extension CCA is clear). 1313 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us) 1314 * EXT_CWMIN: CwMin for extension channel backoff 1315 * 0: Disabled 1316 * 1317 */ 1318#define TXOP_CTRL_CFG 0x1340 1319#define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001) 1320#define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002) 1321#define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004) 1322#define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008) 1323#define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010) 1324#define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020) 1325#define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040) 1326#define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080) 1327#define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00) 1328#define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000) 1329 1330/* 1331 * TX_RTS_CFG: 1332 * RTS_THRES: unit:byte 1333 * RTS_FBK_EN: enable rts rate fallback 1334 */ 1335#define TX_RTS_CFG 0x1344 1336#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff) 1337#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00) 1338#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000) 1339 1340/* 1341 * TX_TIMEOUT_CFG: 1342 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us 1343 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure 1344 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation. 1345 * it is recommended that: 1346 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) 1347 */ 1348#define TX_TIMEOUT_CFG 0x1348 1349#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0) 1350#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00) 1351#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000) 1352 1353/* 1354 * TX_RTY_CFG: 1355 * SHORT_RTY_LIMIT: short retry limit 1356 * LONG_RTY_LIMIT: long retry limit 1357 * LONG_RTY_THRE: Long retry threshoold 1358 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode 1359 * 0:expired by retry limit, 1: expired by mpdu life timer 1360 * AGG_RTY_MODE: Aggregate MPDU retry mode 1361 * 0:expired by retry limit, 1: expired by mpdu life timer 1362 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable 1363 */ 1364#define TX_RTY_CFG 0x134c 1365#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff) 1366#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00) 1367#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000) 1368#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000) 1369#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000) 1370#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000) 1371 1372/* 1373 * TX_LINK_CFG: 1374 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us 1375 * MFB_ENABLE: TX apply remote MFB 1:enable 1376 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable 1377 * 0: not apply remote remote unsolicit (MFS=7) 1378 * TX_MRQ_EN: MCS request TX enable 1379 * TX_RDG_EN: RDG TX enable 1380 * TX_CF_ACK_EN: Piggyback CF-ACK enable 1381 * REMOTE_MFB: remote MCS feedback 1382 * REMOTE_MFS: remote MCS feedback sequence number 1383 */ 1384#define TX_LINK_CFG 0x1350 1385#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff) 1386#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100) 1387#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200) 1388#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400) 1389#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800) 1390#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000) 1391#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000) 1392#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000) 1393 1394/* 1395 * HT_FBK_CFG0: 1396 */ 1397#define HT_FBK_CFG0 0x1354 1398#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f) 1399#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0) 1400#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00) 1401#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000) 1402#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000) 1403#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000) 1404#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000) 1405#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000) 1406 1407/* 1408 * HT_FBK_CFG1: 1409 */ 1410#define HT_FBK_CFG1 0x1358 1411#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f) 1412#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0) 1413#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00) 1414#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000) 1415#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000) 1416#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000) 1417#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000) 1418#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000) 1419 1420/* 1421 * LG_FBK_CFG0: 1422 */ 1423#define LG_FBK_CFG0 0x135c 1424#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f) 1425#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0) 1426#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00) 1427#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000) 1428#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000) 1429#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000) 1430#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000) 1431#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000) 1432 1433/* 1434 * LG_FBK_CFG1: 1435 */ 1436#define LG_FBK_CFG1 0x1360 1437#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f) 1438#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0) 1439#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00) 1440#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000) 1441 1442/* 1443 * CCK_PROT_CFG: CCK Protection 1444 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd) 1445 * PROTECT_CTRL: Protection control frame type for CCK TX 1446 * 0:none, 1:RTS/CTS, 2:CTS-to-self 1447 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV 1448 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV 1449 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow 1450 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow 1451 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow 1452 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow 1453 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow 1454 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow 1455 * RTS_TH_EN: RTS threshold enable on CCK TX 1456 */ 1457#define CCK_PROT_CFG 0x1364 1458#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1459#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1460#define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1461#define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1462#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1463#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1464#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1465#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1466#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1467#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1468#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1469 1470/* 1471 * OFDM_PROT_CFG: OFDM Protection 1472 */ 1473#define OFDM_PROT_CFG 0x1368 1474#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1475#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1476#define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1477#define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1478#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1479#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1480#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1481#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1482#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1483#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1484#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1485 1486/* 1487 * MM20_PROT_CFG: MM20 Protection 1488 */ 1489#define MM20_PROT_CFG 0x136c 1490#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1491#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1492#define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1493#define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1494#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1495#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1496#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1497#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1498#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1499#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1500#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1501 1502/* 1503 * MM40_PROT_CFG: MM40 Protection 1504 */ 1505#define MM40_PROT_CFG 0x1370 1506#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1507#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1508#define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1509#define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1510#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1511#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1512#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1513#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1514#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1515#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1516#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1517 1518/* 1519 * GF20_PROT_CFG: GF20 Protection 1520 */ 1521#define GF20_PROT_CFG 0x1374 1522#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1523#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1524#define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1525#define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1526#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1527#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1528#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1529#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1530#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1531#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1532#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1533 1534/* 1535 * GF40_PROT_CFG: GF40 Protection 1536 */ 1537#define GF40_PROT_CFG 0x1378 1538#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1539#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1540#define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1541#define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1542#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1543#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1544#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1545#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1546#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1547#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1548#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1549 1550/* 1551 * EXP_CTS_TIME: 1552 */ 1553#define EXP_CTS_TIME 0x137c 1554 1555/* 1556 * EXP_ACK_TIME: 1557 */ 1558#define EXP_ACK_TIME 0x1380 1559 1560/* 1561 * HT_FBK_TO_LEGACY: Enable/Disable HT/RTS fallback to OFDM/CCK rate 1562 * Not available for legacy SoCs 1563 */ 1564#define HT_FBK_TO_LEGACY 0x1384 1565 1566/* TX_PWR_CFG_5 */ 1567#define TX_PWR_CFG_5 0x1384 1568#define TX_PWR_CFG_5_MCS16_CH0 FIELD32(0x0000000f) 1569#define TX_PWR_CFG_5_MCS16_CH1 FIELD32(0x000000f0) 1570#define TX_PWR_CFG_5_MCS16_CH2 FIELD32(0x00000f00) 1571#define TX_PWR_CFG_5_MCS18_CH0 FIELD32(0x000f0000) 1572#define TX_PWR_CFG_5_MCS18_CH1 FIELD32(0x00f00000) 1573#define TX_PWR_CFG_5_MCS18_CH2 FIELD32(0x0f000000) 1574 1575/* TX_PWR_CFG_6 */ 1576#define TX_PWR_CFG_6 0x1388 1577#define TX_PWR_CFG_6_MCS20_CH0 FIELD32(0x0000000f) 1578#define TX_PWR_CFG_6_MCS20_CH1 FIELD32(0x000000f0) 1579#define TX_PWR_CFG_6_MCS20_CH2 FIELD32(0x00000f00) 1580#define TX_PWR_CFG_6_MCS22_CH0 FIELD32(0x000f0000) 1581#define TX_PWR_CFG_6_MCS22_CH1 FIELD32(0x00f00000) 1582#define TX_PWR_CFG_6_MCS22_CH2 FIELD32(0x0f000000) 1583 1584/* TX_PWR_CFG_0_EXT */ 1585#define TX_PWR_CFG_0_EXT 0x1390 1586#define TX_PWR_CFG_0_EXT_CCK1_CH2 FIELD32(0x0000000f) 1587#define TX_PWR_CFG_0_EXT_CCK5_CH2 FIELD32(0x00000f00) 1588#define TX_PWR_CFG_0_EXT_OFDM6_CH2 FIELD32(0x000f0000) 1589#define TX_PWR_CFG_0_EXT_OFDM12_CH2 FIELD32(0x0f000000) 1590 1591/* TX_PWR_CFG_1_EXT */ 1592#define TX_PWR_CFG_1_EXT 0x1394 1593#define TX_PWR_CFG_1_EXT_OFDM24_CH2 FIELD32(0x0000000f) 1594#define TX_PWR_CFG_1_EXT_OFDM48_CH2 FIELD32(0x00000f00) 1595#define TX_PWR_CFG_1_EXT_MCS0_CH2 FIELD32(0x000f0000) 1596#define TX_PWR_CFG_1_EXT_MCS2_CH2 FIELD32(0x0f000000) 1597 1598/* TX_PWR_CFG_2_EXT */ 1599#define TX_PWR_CFG_2_EXT 0x1398 1600#define TX_PWR_CFG_2_EXT_MCS4_CH2 FIELD32(0x0000000f) 1601#define TX_PWR_CFG_2_EXT_MCS6_CH2 FIELD32(0x00000f00) 1602#define TX_PWR_CFG_2_EXT_MCS8_CH2 FIELD32(0x000f0000) 1603#define TX_PWR_CFG_2_EXT_MCS10_CH2 FIELD32(0x0f000000) 1604 1605/* TX_PWR_CFG_3_EXT */ 1606#define TX_PWR_CFG_3_EXT 0x139c 1607#define TX_PWR_CFG_3_EXT_MCS12_CH2 FIELD32(0x0000000f) 1608#define TX_PWR_CFG_3_EXT_MCS14_CH2 FIELD32(0x00000f00) 1609#define TX_PWR_CFG_3_EXT_STBC0_CH2 FIELD32(0x000f0000) 1610#define TX_PWR_CFG_3_EXT_STBC2_CH2 FIELD32(0x0f000000) 1611 1612/* TX_PWR_CFG_4_EXT */ 1613#define TX_PWR_CFG_4_EXT 0x13a0 1614#define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f) 1615#define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00) 1616 1617/* TXn_RF_GAIN_CORRECT: RF Gain Correction for each RF_ALC[3:2] 1618 * Unit: 0.1 dB, Range: -3.2 dB to 3.1 dB 1619 */ 1620#define TX0_RF_GAIN_CORRECT 0x13a0 1621#define TX0_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f) 1622#define TX0_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00) 1623#define TX0_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000) 1624#define TX0_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000) 1625 1626#define TX1_RF_GAIN_CORRECT 0x13a4 1627#define TX1_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f) 1628#define TX1_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00) 1629#define TX1_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000) 1630#define TX1_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000) 1631 1632/* TXn_RF_GAIN_ATTEN: TXn RF Gain Attenuation Level 1633 * Format: 7-bit, signed value 1634 * Unit: 0.5 dB, Range: -20 dB to -5 dB 1635 */ 1636#define TX0_RF_GAIN_ATTEN 0x13a8 1637#define TX0_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f) 1638#define TX0_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00) 1639#define TX0_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000) 1640#define TX0_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000) 1641#define TX1_RF_GAIN_ATTEN 0x13ac 1642#define TX1_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f) 1643#define TX1_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00) 1644#define TX1_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000) 1645#define TX1_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000) 1646 1647/* TX_ALC_CFG_0: TX Automatic Level Control Configuration 0 1648 * TX_ALC_LIMIT_n: TXn upper limit 1649 * TX_ALC_CH_INIT_n: TXn channel initial transmission gain 1650 * Unit: 0.5 dB, Range: 0 to 23.5 dB 1651 */ 1652#define TX_ALC_CFG_0 0x13b0 1653#define TX_ALC_CFG_0_CH_INIT_0 FIELD32(0x0000003f) 1654#define TX_ALC_CFG_0_CH_INIT_1 FIELD32(0x00003f00) 1655#define TX_ALC_CFG_0_LIMIT_0 FIELD32(0x003f0000) 1656#define TX_ALC_CFG_0_LIMIT_1 FIELD32(0x3f000000) 1657 1658/* TX_ALC_CFG_1: TX Automatic Level Control Configuration 1 1659 * TX_TEMP_COMP: TX Power Temperature Compensation 1660 * Unit: 0.5 dB, Range: -10 dB to 10 dB 1661 * TXn_GAIN_FINE: TXn Gain Fine Adjustment 1662 * Unit: 0.1 dB, Range: -0.8 dB to 0.7 dB 1663 * RF_TOS_DLY: Sets the RF_TOS_EN assertion delay after 1664 * deassertion of PA_PE. 1665 * Unit: 0.25 usec 1666 * TXn_RF_GAIN_ATTEN: TXn RF gain attentuation selector 1667 * RF_TOS_TIMEOUT: time-out value for RF_TOS_ENABLE 1668 * deassertion if RF_TOS_DONE is missing. 1669 * Unit: 0.25 usec 1670 * RF_TOS_ENABLE: TX offset calibration enable 1671 * ROS_BUSY_EN: RX offset calibration busy enable 1672 */ 1673#define TX_ALC_CFG_1 0x13b4 1674#define TX_ALC_CFG_1_TX_TEMP_COMP FIELD32(0x0000003f) 1675#define TX_ALC_CFG_1_TX0_GAIN_FINE FIELD32(0x00000f00) 1676#define TX_ALC_CFG_1_TX1_GAIN_FINE FIELD32(0x0000f000) 1677#define TX_ALC_CFG_1_RF_TOS_DLY FIELD32(0x00070000) 1678#define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN FIELD32(0x00300000) 1679#define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN FIELD32(0x00c00000) 1680#define TX_ALC_CFG_1_RF_TOS_TIMEOUT FIELD32(0x3f000000) 1681#define TX_ALC_CFG_1_RF_TOS_ENABLE FIELD32(0x40000000) 1682#define TX_ALC_CFG_1_ROS_BUSY_EN FIELD32(0x80000000) 1683 1684/* TXn_BB_GAIN_ATTEN: TXn RF Gain Attenuation Level 1685 * Format: 5-bit signed values 1686 * Unit: 0.5 dB, Range: -8 dB to 7 dB 1687 */ 1688#define TX0_BB_GAIN_ATTEN 0x13c0 1689#define TX0_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f) 1690#define TX0_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00) 1691#define TX0_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000) 1692#define TX0_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000) 1693#define TX1_BB_GAIN_ATTEN 0x13c4 1694#define TX1_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f) 1695#define TX1_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00) 1696#define TX1_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000) 1697#define TX1_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000) 1698 1699/* TX_ALC_VGA3: TX Automatic Level Correction Variable Gain Amplifier 3 */ 1700#define TX_ALC_VGA3 0x13c8 1701#define TX_ALC_VGA3_TX0_ALC_VGA3 FIELD32(0x0000001f) 1702#define TX_ALC_VGA3_TX1_ALC_VGA3 FIELD32(0x00001f00) 1703#define TX_ALC_VGA3_TX0_ALC_VGA2 FIELD32(0x001f0000) 1704#define TX_ALC_VGA3_TX1_ALC_VGA2 FIELD32(0x1f000000) 1705 1706/* TX_PWR_CFG_7 */ 1707#define TX_PWR_CFG_7 0x13d4 1708#define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f) 1709#define TX_PWR_CFG_7_OFDM54_CH1 FIELD32(0x000000f0) 1710#define TX_PWR_CFG_7_OFDM54_CH2 FIELD32(0x00000f00) 1711#define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000) 1712#define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000) 1713#define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000) 1714/* bits for new 2T devices */ 1715#define TX_PWR_CFG_7B_54MBS FIELD32(0x000000ff) 1716#define TX_PWR_CFG_7B_MCS7 FIELD32(0x00ff0000) 1717 1718 1719/* TX_PWR_CFG_8 */ 1720#define TX_PWR_CFG_8 0x13d8 1721#define TX_PWR_CFG_8_MCS15_CH0 FIELD32(0x0000000f) 1722#define TX_PWR_CFG_8_MCS15_CH1 FIELD32(0x000000f0) 1723#define TX_PWR_CFG_8_MCS15_CH2 FIELD32(0x00000f00) 1724#define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000) 1725#define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000) 1726#define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000) 1727/* bits for new 2T devices */ 1728#define TX_PWR_CFG_8B_MCS15 FIELD32(0x000000ff) 1729 1730 1731/* TX_PWR_CFG_9 */ 1732#define TX_PWR_CFG_9 0x13dc 1733#define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f) 1734#define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0) 1735#define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00) 1736/* bits for new 2T devices */ 1737#define TX_PWR_CFG_9B_STBC_MCS7 FIELD32(0x000000ff) 1738 1739/* 1740 * TX_TXBF_CFG: 1741 */ 1742#define TX_TXBF_CFG_0 0x138c 1743#define TX_TXBF_CFG_1 0x13a4 1744#define TX_TXBF_CFG_2 0x13a8 1745#define TX_TXBF_CFG_3 0x13ac 1746 1747/* 1748 * TX_FBK_CFG_3S: 1749 */ 1750#define TX_FBK_CFG_3S_0 0x13c4 1751#define TX_FBK_CFG_3S_1 0x13c8 1752 1753/* 1754 * RX_FILTER_CFG: RX configuration register. 1755 */ 1756#define RX_FILTER_CFG 0x1400 1757#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001) 1758#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002) 1759#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004) 1760#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008) 1761#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010) 1762#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020) 1763#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040) 1764#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080) 1765#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100) 1766#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200) 1767#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400) 1768#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800) 1769#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000) 1770#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000) 1771#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000) 1772#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000) 1773#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000) 1774 1775/* 1776 * AUTO_RSP_CFG: 1777 * AUTORESPONDER: 0: disable, 1: enable 1778 * BAC_ACK_POLICY: 0:long, 1:short preamble 1779 * CTS_40_MMODE: Response CTS 40MHz duplicate mode 1780 * CTS_40_MREF: Response CTS 40MHz duplicate mode 1781 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble 1782 * DUAL_CTS_EN: Power bit value in control frame 1783 * ACK_CTS_PSM_BIT:Power bit value in control frame 1784 */ 1785#define AUTO_RSP_CFG 0x1404 1786#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001) 1787#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002) 1788#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004) 1789#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008) 1790#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010) 1791#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040) 1792#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080) 1793 1794/* 1795 * LEGACY_BASIC_RATE: 1796 */ 1797#define LEGACY_BASIC_RATE 0x1408 1798 1799/* 1800 * HT_BASIC_RATE: 1801 */ 1802#define HT_BASIC_RATE 0x140c 1803 1804/* 1805 * HT_CTRL_CFG: 1806 */ 1807#define HT_CTRL_CFG 0x1410 1808 1809/* 1810 * SIFS_COST_CFG: 1811 */ 1812#define SIFS_COST_CFG 0x1414 1813 1814/* 1815 * RX_PARSER_CFG: 1816 * Set NAV for all received frames 1817 */ 1818#define RX_PARSER_CFG 0x1418 1819 1820/* 1821 * TX_SEC_CNT0: 1822 */ 1823#define TX_SEC_CNT0 0x1500 1824 1825/* 1826 * RX_SEC_CNT0: 1827 */ 1828#define RX_SEC_CNT0 0x1504 1829 1830/* 1831 * CCMP_FC_MUTE: 1832 */ 1833#define CCMP_FC_MUTE 0x1508 1834 1835/* 1836 * TXOP_HLDR_ADDR0: 1837 */ 1838#define TXOP_HLDR_ADDR0 0x1600 1839 1840/* 1841 * TXOP_HLDR_ADDR1: 1842 */ 1843#define TXOP_HLDR_ADDR1 0x1604 1844 1845/* 1846 * TXOP_HLDR_ET: 1847 */ 1848#define TXOP_HLDR_ET 0x1608 1849 1850/* 1851 * QOS_CFPOLL_RA_DW0: 1852 */ 1853#define QOS_CFPOLL_RA_DW0 0x160c 1854 1855/* 1856 * QOS_CFPOLL_RA_DW1: 1857 */ 1858#define QOS_CFPOLL_RA_DW1 0x1610 1859 1860/* 1861 * QOS_CFPOLL_QC: 1862 */ 1863#define QOS_CFPOLL_QC 0x1614 1864 1865/* 1866 * RX_STA_CNT0: RX PLCP error count & RX CRC error count 1867 */ 1868#define RX_STA_CNT0 0x1700 1869#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff) 1870#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000) 1871 1872/* 1873 * RX_STA_CNT1: RX False CCA count & RX LONG frame count 1874 */ 1875#define RX_STA_CNT1 0x1704 1876#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff) 1877#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000) 1878 1879/* 1880 * RX_STA_CNT2: 1881 */ 1882#define RX_STA_CNT2 0x1708 1883#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff) 1884#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000) 1885 1886/* 1887 * TX_STA_CNT0: TX Beacon count 1888 */ 1889#define TX_STA_CNT0 0x170c 1890#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff) 1891#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000) 1892 1893/* 1894 * TX_STA_CNT1: TX tx count 1895 */ 1896#define TX_STA_CNT1 0x1710 1897#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff) 1898#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000) 1899 1900/* 1901 * TX_STA_CNT2: TX tx count 1902 */ 1903#define TX_STA_CNT2 0x1714 1904#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff) 1905#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000) 1906 1907/* 1908 * TX_STA_FIFO: TX Result for specific PID status fifo register. 1909 * 1910 * This register is implemented as FIFO with 16 entries in the HW. Each 1911 * register read fetches the next tx result. If the FIFO is full because 1912 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS) 1913 * triggered, the hw seems to simply drop further tx results. 1914 * 1915 * VALID: 1: this tx result is valid 1916 * 0: no valid tx result -> driver should stop reading 1917 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used 1918 * to match a frame with its tx result (even though the PID is 1919 * only 4 bits wide). 1920 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3) 1921 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3) 1922 * This identification number is calculated by ((idx % 3) + 1). 1923 * TX_SUCCESS: Indicates tx success (1) or failure (0) 1924 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0) 1925 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0) 1926 * WCID: The wireless client ID. 1927 * MCS: The tx rate used during the last transmission of this frame, be it 1928 * successful or not. 1929 * PHYMODE: The phymode used for the transmission. 1930 */ 1931#define TX_STA_FIFO 0x1718 1932#define TX_STA_FIFO_VALID FIELD32(0x00000001) 1933#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e) 1934#define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006) 1935#define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018) 1936#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020) 1937#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040) 1938#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080) 1939#define TX_STA_FIFO_WCID FIELD32(0x0000ff00) 1940#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000) 1941#define TX_STA_FIFO_MCS FIELD32(0x007f0000) 1942#define TX_STA_FIFO_BW FIELD32(0x00800000) 1943#define TX_STA_FIFO_SGI FIELD32(0x01000000) 1944#define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000) 1945 1946/* 1947 * TX_AGG_CNT: Debug counter 1948 */ 1949#define TX_AGG_CNT 0x171c 1950#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff) 1951#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000) 1952 1953/* 1954 * TX_AGG_CNT0: 1955 */ 1956#define TX_AGG_CNT0 0x1720 1957#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff) 1958#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000) 1959 1960/* 1961 * TX_AGG_CNT1: 1962 */ 1963#define TX_AGG_CNT1 0x1724 1964#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff) 1965#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000) 1966 1967/* 1968 * TX_AGG_CNT2: 1969 */ 1970#define TX_AGG_CNT2 0x1728 1971#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff) 1972#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000) 1973 1974/* 1975 * TX_AGG_CNT3: 1976 */ 1977#define TX_AGG_CNT3 0x172c 1978#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff) 1979#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000) 1980 1981/* 1982 * TX_AGG_CNT4: 1983 */ 1984#define TX_AGG_CNT4 0x1730 1985#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff) 1986#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000) 1987 1988/* 1989 * TX_AGG_CNT5: 1990 */ 1991#define TX_AGG_CNT5 0x1734 1992#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff) 1993#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000) 1994 1995/* 1996 * TX_AGG_CNT6: 1997 */ 1998#define TX_AGG_CNT6 0x1738 1999#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff) 2000#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000) 2001 2002/* 2003 * TX_AGG_CNT7: 2004 */ 2005#define TX_AGG_CNT7 0x173c 2006#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff) 2007#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000) 2008 2009/* 2010 * MPDU_DENSITY_CNT: 2011 * TX_ZERO_DEL: TX zero length delimiter count 2012 * RX_ZERO_DEL: RX zero length delimiter count 2013 */ 2014#define MPDU_DENSITY_CNT 0x1740 2015#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff) 2016#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000) 2017 2018/* 2019 * Security key table memory. 2020 * 2021 * The pairwise key table shares some memory with the beacon frame 2022 * buffers 6 and 7. That basically means that when beacon 6 & 7 2023 * are used we should only use the reduced pairwise key table which 2024 * has a maximum of 222 entries. 2025 * 2026 * --------------------------------------------- 2027 * |0x4000 | Pairwise Key | Reduced Pairwise | 2028 * | | Table | Key Table | 2029 * | | Size: 256 * 32 | Size: 222 * 32 | 2030 * |0x5BC0 | |------------------- 2031 * | | | Beacon 6 | 2032 * |0x5DC0 | |------------------- 2033 * | | | Beacon 7 | 2034 * |0x5FC0 | |------------------- 2035 * |0x5FFF | | 2036 * -------------------------- 2037 * 2038 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry 2039 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry 2040 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry 2041 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry 2042 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry 2043 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry 2044 */ 2045#define MAC_WCID_BASE 0x1800 2046#define PAIRWISE_KEY_TABLE_BASE 0x4000 2047#define MAC_IVEIV_TABLE_BASE 0x6000 2048#define MAC_WCID_ATTRIBUTE_BASE 0x6800 2049#define SHARED_KEY_TABLE_BASE 0x6c00 2050#define SHARED_KEY_MODE_BASE 0x7000 2051 2052#define MAC_WCID_ENTRY(__idx) \ 2053 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry))) 2054#define PAIRWISE_KEY_ENTRY(__idx) \ 2055 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry))) 2056#define MAC_IVEIV_ENTRY(__idx) \ 2057 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry))) 2058#define MAC_WCID_ATTR_ENTRY(__idx) \ 2059 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32))) 2060#define SHARED_KEY_ENTRY(__idx) \ 2061 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry))) 2062#define SHARED_KEY_MODE_ENTRY(__idx) \ 2063 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32))) 2064 2065struct mac_wcid_entry { 2066 u8 mac[6]; 2067 u8 reserved[2]; 2068} __packed; 2069 2070struct hw_key_entry { 2071 u8 key[16]; 2072 u8 tx_mic[8]; 2073 u8 rx_mic[8]; 2074} __packed; 2075 2076struct mac_iveiv_entry { 2077 u8 iv[8]; 2078} __packed; 2079 2080/* 2081 * MAC_WCID_ATTRIBUTE: 2082 */ 2083#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001) 2084#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e) 2085#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070) 2086#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380) 2087#define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400) 2088#define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800) 2089#define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000) 2090#define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000) 2091 2092/* 2093 * SHARED_KEY_MODE: 2094 */ 2095#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007) 2096#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070) 2097#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700) 2098#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000) 2099#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000) 2100#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000) 2101#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000) 2102#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000) 2103 2104/* 2105 * HOST-MCU communication 2106 */ 2107 2108/* 2109 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox. 2110 * CMD_TOKEN: Command id, 0xff disable status reporting. 2111 */ 2112#define H2M_MAILBOX_CSR 0x7010 2113#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff) 2114#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00) 2115#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000) 2116#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000) 2117 2118/* 2119 * H2M_MAILBOX_CID: 2120 * Free slots contain 0xff. MCU will store command's token to lowest free slot. 2121 * If all slots are occupied status will be dropped. 2122 */ 2123#define H2M_MAILBOX_CID 0x7014 2124#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff) 2125#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00) 2126#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000) 2127#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000) 2128 2129/* 2130 * H2M_MAILBOX_STATUS: 2131 * Command status will be saved to same slot as command id. 2132 */ 2133#define H2M_MAILBOX_STATUS 0x701c 2134 2135/* 2136 * H2M_INT_SRC: 2137 */ 2138#define H2M_INT_SRC 0x7024 2139 2140/* 2141 * H2M_BBP_AGENT: 2142 */ 2143#define H2M_BBP_AGENT 0x7028 2144 2145/* 2146 * MCU_LEDCS: LED control for MCU Mailbox. 2147 */ 2148#define MCU_LEDCS_LED_MODE FIELD8(0x1f) 2149#define MCU_LEDCS_POLARITY FIELD8(0x01) 2150 2151/* 2152 * HW_CS_CTS_BASE: 2153 * Carrier-sense CTS frame base address. 2154 * It's where mac stores carrier-sense frame for carrier-sense function. 2155 */ 2156#define HW_CS_CTS_BASE 0x7700 2157 2158/* 2159 * HW_DFS_CTS_BASE: 2160 * DFS CTS frame base address. It's where mac stores CTS frame for DFS. 2161 */ 2162#define HW_DFS_CTS_BASE 0x7780 2163 2164/* 2165 * TXRX control registers - base address 0x3000 2166 */ 2167 2168/* 2169 * TXRX_CSR1: 2170 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. 2171 */ 2172#define TXRX_CSR1 0x77d0 2173 2174/* 2175 * HW_DEBUG_SETTING_BASE: 2176 * since NULL frame won't be that long (256 byte) 2177 * We steal 16 tail bytes to save debugging settings 2178 */ 2179#define HW_DEBUG_SETTING_BASE 0x77f0 2180#define HW_DEBUG_SETTING_BASE2 0x7770 2181 2182/* 2183 * HW_BEACON_BASE 2184 * In order to support maximum 8 MBSS and its maximum length 2185 * is 512 bytes for each beacon 2186 * Three section discontinue memory segments will be used. 2187 * 1. The original region for BCN 0~3 2188 * 2. Extract memory from FCE table for BCN 4~5 2189 * 3. Extract memory from Pair-wise key table for BCN 6~7 2190 * It occupied those memory of wcid 238~253 for BCN 6 2191 * and wcid 222~237 for BCN 7 (see Security key table memory 2192 * for more info). 2193 * 2194 * IMPORTANT NOTE: Not sure why legacy driver does this, 2195 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6. 2196 */ 2197#define HW_BEACON_BASE0 0x7800 2198#define HW_BEACON_BASE1 0x7a00 2199#define HW_BEACON_BASE2 0x7c00 2200#define HW_BEACON_BASE3 0x7e00 2201#define HW_BEACON_BASE4 0x7200 2202#define HW_BEACON_BASE5 0x7400 2203#define HW_BEACON_BASE6 0x5dc0 2204#define HW_BEACON_BASE7 0x5bc0 2205 2206#define HW_BEACON_BASE(__index) \ 2207 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \ 2208 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \ 2209 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200)))) 2210 2211#define BEACON_BASE_TO_OFFSET(_base) (((_base) - 0x4000) / 64) 2212 2213/* 2214 * BBP registers. 2215 * The wordsize of the BBP is 8 bits. 2216 */ 2217 2218/* 2219 * BBP 1: TX Antenna & Power Control 2220 * POWER_CTRL: 2221 * 0 - normal, 2222 * 1 - drop tx power by 6dBm, 2223 * 2 - drop tx power by 12dBm, 2224 * 3 - increase tx power by 6dBm 2225 */ 2226#define BBP1_TX_POWER_CTRL FIELD8(0x03) 2227#define BBP1_TX_ANTENNA FIELD8(0x18) 2228 2229/* 2230 * BBP 3: RX Antenna 2231 */ 2232#define BBP3_RX_ADC FIELD8(0x03) 2233#define BBP3_RX_ANTENNA FIELD8(0x18) 2234#define BBP3_HT40_MINUS FIELD8(0x20) 2235#define BBP3_ADC_MODE_SWITCH FIELD8(0x40) 2236#define BBP3_ADC_INIT_MODE FIELD8(0x80) 2237 2238/* 2239 * BBP 4: Bandwidth 2240 */ 2241#define BBP4_TX_BF FIELD8(0x01) 2242#define BBP4_BANDWIDTH FIELD8(0x18) 2243#define BBP4_MAC_IF_CTRL FIELD8(0x40) 2244 2245/* BBP27 */ 2246#define BBP27_RX_CHAIN_SEL FIELD8(0x60) 2247 2248/* 2249 * BBP 47: Bandwidth 2250 */ 2251#define BBP47_TSSI_REPORT_SEL FIELD8(0x03) 2252#define BBP47_TSSI_UPDATE_REQ FIELD8(0x04) 2253#define BBP47_TSSI_TSSI_MODE FIELD8(0x18) 2254#define BBP47_TSSI_ADC6 FIELD8(0x80) 2255 2256/* 2257 * BBP 49 2258 */ 2259#define BBP49_UPDATE_FLAG FIELD8(0x01) 2260 2261/* 2262 * BBP 105: 2263 * - bit0: detect SIG on primary channel only (on 40MHz bandwidth) 2264 * - bit1: FEQ (Feed Forward Compensation) for independend streams 2265 * - bit2: MLD (Maximum Likehood Detection) for 2 streams (reserved on single 2266 * stream) 2267 * - bit4: channel estimation updates based on remodulation of 2268 * L-SIG and HT-SIG symbols 2269 */ 2270#define BBP105_DETECT_SIG_ON_PRIMARY FIELD8(0x01) 2271#define BBP105_FEQ FIELD8(0x02) 2272#define BBP105_MLD FIELD8(0x04) 2273#define BBP105_SIG_REMODULATION FIELD8(0x08) 2274 2275/* 2276 * BBP 109 2277 */ 2278#define BBP109_TX0_POWER FIELD8(0x0f) 2279#define BBP109_TX1_POWER FIELD8(0xf0) 2280 2281/* BBP 110 */ 2282#define BBP110_TX2_POWER FIELD8(0x0f) 2283 2284 2285/* 2286 * BBP 138: Unknown 2287 */ 2288#define BBP138_RX_ADC1 FIELD8(0x02) 2289#define BBP138_RX_ADC2 FIELD8(0x04) 2290#define BBP138_TX_DAC1 FIELD8(0x20) 2291#define BBP138_TX_DAC2 FIELD8(0x40) 2292 2293/* 2294 * BBP 152: Rx Ant 2295 */ 2296#define BBP152_RX_DEFAULT_ANT FIELD8(0x80) 2297 2298/* 2299 * BBP 254: unknown 2300 */ 2301#define BBP254_BIT7 FIELD8(0x80) 2302 2303/* 2304 * RFCSR registers 2305 * The wordsize of the RFCSR is 8 bits. 2306 */ 2307 2308/* 2309 * RFCSR 1: 2310 */ 2311#define RFCSR1_RF_BLOCK_EN FIELD8(0x01) 2312#define RFCSR1_PLL_PD FIELD8(0x02) 2313#define RFCSR1_RX0_PD FIELD8(0x04) 2314#define RFCSR1_TX0_PD FIELD8(0x08) 2315#define RFCSR1_RX1_PD FIELD8(0x10) 2316#define RFCSR1_TX1_PD FIELD8(0x20) 2317#define RFCSR1_RX2_PD FIELD8(0x40) 2318#define RFCSR1_TX2_PD FIELD8(0x80) 2319#define RFCSR1_TX2_EN_MT7620 FIELD8(0x02) 2320 2321/* 2322 * RFCSR 2: 2323 */ 2324#define RFCSR2_RESCAL_BP FIELD8(0x40) 2325#define RFCSR2_RESCAL_EN FIELD8(0x80) 2326#define RFCSR2_RX2_EN_MT7620 FIELD8(0x02) 2327#define RFCSR2_TX2_EN_MT7620 FIELD8(0x20) 2328 2329/* 2330 * RFCSR 3: 2331 */ 2332#define RFCSR3_K FIELD8(0x0f) 2333/* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */ 2334#define RFCSR3_PA1_BIAS_CCK FIELD8(0x70) 2335#define RFCSR3_PA2_CASCODE_BIAS_CCKK FIELD8(0x80) 2336/* Bits for RF3290/RF5360/RF5362/RF5370/RF5372/RF5390/RF5392 */ 2337#define RFCSR3_VCOCAL_EN FIELD8(0x80) 2338/* Bits for RF3050 */ 2339#define RFCSR3_BIT1 FIELD8(0x02) 2340#define RFCSR3_BIT2 FIELD8(0x04) 2341#define RFCSR3_BIT3 FIELD8(0x08) 2342#define RFCSR3_BIT4 FIELD8(0x10) 2343#define RFCSR3_BIT5 FIELD8(0x20) 2344 2345/* 2346 * RFCSR 4: 2347 * VCOCAL_EN used by MT7620 2348 */ 2349#define RFCSR4_VCOCAL_EN FIELD8(0x80) 2350 2351/* 2352 * FRCSR 5: 2353 */ 2354#define RFCSR5_R1 FIELD8(0x0c) 2355 2356/* 2357 * RFCSR 6: 2358 */ 2359#define RFCSR6_R1 FIELD8(0x03) 2360#define RFCSR6_R2 FIELD8(0x40) 2361#define RFCSR6_TXDIV FIELD8(0x0c) 2362/* bits for RF3053 */ 2363#define RFCSR6_VCO_IC FIELD8(0xc0) 2364 2365/* 2366 * RFCSR 7: 2367 */ 2368#define RFCSR7_RF_TUNING FIELD8(0x01) 2369#define RFCSR7_BIT1 FIELD8(0x02) 2370#define RFCSR7_BIT2 FIELD8(0x04) 2371#define RFCSR7_BIT3 FIELD8(0x08) 2372#define RFCSR7_BIT4 FIELD8(0x10) 2373#define RFCSR7_BIT5 FIELD8(0x20) 2374#define RFCSR7_BITS67 FIELD8(0xc0) 2375 2376/* 2377 * RFCSR 9: 2378 */ 2379#define RFCSR9_K FIELD8(0x0f) 2380#define RFCSR9_N FIELD8(0x10) 2381#define RFCSR9_UNKNOWN FIELD8(0x60) 2382#define RFCSR9_MOD FIELD8(0x80) 2383 2384/* 2385 * RFCSR 11: 2386 */ 2387#define RFCSR11_R FIELD8(0x03) 2388#define RFCSR11_PLL_MOD FIELD8(0x0c) 2389#define RFCSR11_MOD FIELD8(0xc0) 2390/* bits for RF3053 */ 2391/* TODO: verify RFCSR11_MOD usage on other chips */ 2392#define RFCSR11_PLL_IDOH FIELD8(0x40) 2393 2394 2395/* 2396 * RFCSR 12: 2397 */ 2398#define RFCSR12_TX_POWER FIELD8(0x1f) 2399#define RFCSR12_DR0 FIELD8(0xe0) 2400 2401/* 2402 * RFCSR 13: 2403 */ 2404#define RFCSR13_TX_POWER FIELD8(0x1f) 2405#define RFCSR13_DR0 FIELD8(0xe0) 2406#define RFCSR13_RDIV_MT7620 FIELD8(0x03) 2407 2408/* 2409 * RFCSR 15: 2410 */ 2411#define RFCSR15_TX_LO2_EN FIELD8(0x08) 2412 2413/* 2414 * RFCSR 16: 2415 */ 2416#define RFCSR16_TXMIXER_GAIN FIELD8(0x07) 2417#define RFCSR16_RF_PLL_FREQ_SEL_MT7620 FIELD8(0x0F) 2418#define RFCSR16_SDM_MODE_MT7620 FIELD8(0xE0) 2419 2420/* 2421 * RFCSR 17: 2422 */ 2423#define RFCSR17_TXMIXER_GAIN FIELD8(0x07) 2424#define RFCSR17_TX_LO1_EN FIELD8(0x08) 2425#define RFCSR17_R FIELD8(0x20) 2426#define RFCSR17_CODE FIELD8(0x7f) 2427 2428/* RFCSR 18 */ 2429#define RFCSR18_XO_TUNE_BYPASS FIELD8(0x40) 2430 2431/* RFCSR 19 */ 2432#define RFCSR19_K FIELD8(0x03) 2433 2434/* 2435 * RFCSR 20: 2436 */ 2437#define RFCSR20_RX_LO1_EN FIELD8(0x08) 2438 2439/* 2440 * RFCSR 21: 2441 */ 2442#define RFCSR21_RX_LO2_EN FIELD8(0x08) 2443#define RFCSR21_BIT1 FIELD8(0x01) 2444#define RFCSR21_BIT8 FIELD8(0x80) 2445 2446/* 2447 * RFCSR 22: 2448 */ 2449#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) 2450#define RFCSR22_FREQPLAN_D_MT7620 FIELD8(0x07) 2451 2452/* 2453 * RFCSR 23: 2454 */ 2455#define RFCSR23_FREQ_OFFSET FIELD8(0x7f) 2456 2457/* 2458 * RFCSR 24: 2459 */ 2460#define RFCSR24_TX_AGC_FC FIELD8(0x1f) 2461#define RFCSR24_TX_H20M FIELD8(0x20) 2462#define RFCSR24_TX_CALIB FIELD8(0x7f) 2463 2464/* 2465 * RFCSR 27: 2466 */ 2467#define RFCSR27_R1 FIELD8(0x03) 2468#define RFCSR27_R2 FIELD8(0x04) 2469#define RFCSR27_R3 FIELD8(0x30) 2470#define RFCSR27_R4 FIELD8(0x40) 2471 2472/* 2473 * RFCSR 28: 2474 */ 2475#define RFCSR28_CH11_HT40 FIELD8(0x04) 2476 2477/* 2478 * RFCSR 29: 2479 */ 2480#define RFCSR29_ADC6_TEST FIELD8(0x01) 2481#define RFCSR29_ADC6_INT_TEST FIELD8(0x02) 2482#define RFCSR29_RSSI_RESET FIELD8(0x04) 2483#define RFCSR29_RSSI_ON FIELD8(0x08) 2484#define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30) 2485#define RFCSR29_RSSI_GAIN FIELD8(0xc0) 2486 2487/* 2488 * RFCSR 30: 2489 */ 2490#define RFCSR30_TX_H20M FIELD8(0x02) 2491#define RFCSR30_RX_H20M FIELD8(0x04) 2492#define RFCSR30_RX_VCM FIELD8(0x18) 2493#define RFCSR30_RF_CALIBRATION FIELD8(0x80) 2494#define RF3322_RFCSR30_TX_H20M FIELD8(0x01) 2495#define RF3322_RFCSR30_RX_H20M FIELD8(0x02) 2496 2497/* 2498 * RFCSR 31: 2499 */ 2500#define RFCSR31_RX_AGC_FC FIELD8(0x1f) 2501#define RFCSR31_RX_H20M FIELD8(0x20) 2502#define RFCSR31_RX_CALIB FIELD8(0x7f) 2503 2504/* RFCSR 32 bits for RF3053 */ 2505#define RFCSR32_TX_AGC_FC FIELD8(0xf8) 2506 2507/* RFCSR 36 bits for RF3053 */ 2508#define RFCSR36_RF_BS FIELD8(0x80) 2509 2510/* 2511 * RFCSR 34: 2512 */ 2513#define RFCSR34_TX0_EXT_PA FIELD8(0x04) 2514#define RFCSR34_TX1_EXT_PA FIELD8(0x08) 2515 2516/* 2517 * RFCSR 38: 2518 */ 2519#define RFCSR38_RX_LO1_EN FIELD8(0x20) 2520 2521/* 2522 * RFCSR 39: 2523 */ 2524#define RFCSR39_RX_DIV FIELD8(0x40) 2525#define RFCSR39_RX_LO2_EN FIELD8(0x80) 2526 2527/* 2528 * RFCSR 41: 2529 */ 2530#define RFCSR41_BIT1 FIELD8(0x01) 2531#define RFCSR41_BIT4 FIELD8(0x08) 2532 2533/* 2534 * RFCSR 42: 2535 */ 2536#define RFCSR42_BIT1 FIELD8(0x01) 2537#define RFCSR42_BIT4 FIELD8(0x08) 2538#define RFCSR42_TX2_EN_MT7620 FIELD8(0x40) 2539 2540/* 2541 * RFCSR 49: 2542 */ 2543#define RFCSR49_TX FIELD8(0x3f) 2544#define RFCSR49_EP FIELD8(0xc0) 2545/* bits for RT3593 */ 2546#define RFCSR49_TX_LO1_IC FIELD8(0x1c) 2547#define RFCSR49_TX_DIV FIELD8(0x20) 2548 2549/* 2550 * RFCSR 50: 2551 */ 2552#define RFCSR50_TX FIELD8(0x3f) 2553#define RFCSR50_TX0_EXT_PA FIELD8(0x02) 2554#define RFCSR50_TX1_EXT_PA FIELD8(0x10) 2555#define RFCSR50_EP FIELD8(0xc0) 2556/* bits for RT3593 */ 2557#define RFCSR50_TX_LO1_EN FIELD8(0x20) 2558#define RFCSR50_TX_LO2_EN FIELD8(0x10) 2559 2560/* RFCSR 51 */ 2561/* bits for RT3593 */ 2562#define RFCSR51_BITS01 FIELD8(0x03) 2563#define RFCSR51_BITS24 FIELD8(0x1c) 2564#define RFCSR51_BITS57 FIELD8(0xe0) 2565 2566#define RFCSR53_TX_POWER FIELD8(0x3f) 2567#define RFCSR53_UNKNOWN FIELD8(0xc0) 2568 2569#define RFCSR54_TX_POWER FIELD8(0x3f) 2570#define RFCSR54_UNKNOWN FIELD8(0xc0) 2571 2572#define RFCSR55_TX_POWER FIELD8(0x3f) 2573#define RFCSR55_UNKNOWN FIELD8(0xc0) 2574 2575#define RFCSR57_DRV_CC FIELD8(0xfc) 2576 2577 2578/* 2579 * RF registers 2580 */ 2581 2582/* 2583 * RF 2 2584 */ 2585#define RF2_ANTENNA_RX2 FIELD32(0x00000040) 2586#define RF2_ANTENNA_TX1 FIELD32(0x00004000) 2587#define RF2_ANTENNA_RX1 FIELD32(0x00020000) 2588 2589/* 2590 * RF 3 2591 */ 2592#define RF3_TXPOWER_G FIELD32(0x00003e00) 2593#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200) 2594#define RF3_TXPOWER_A FIELD32(0x00003c00) 2595 2596/* 2597 * RF 4 2598 */ 2599#define RF4_TXPOWER_G FIELD32(0x000007c0) 2600#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040) 2601#define RF4_TXPOWER_A FIELD32(0x00000780) 2602#define RF4_FREQ_OFFSET FIELD32(0x001f8000) 2603#define RF4_HT40 FIELD32(0x00200000) 2604 2605/* 2606 * EEPROM content. 2607 * The wordsize of the EEPROM is 16 bits. 2608 */ 2609 2610enum rt2800_eeprom_word { 2611 EEPROM_CHIP_ID = 0, 2612 EEPROM_VERSION, 2613 EEPROM_MAC_ADDR_0, 2614 EEPROM_MAC_ADDR_1, 2615 EEPROM_MAC_ADDR_2, 2616 EEPROM_NIC_CONF0, 2617 EEPROM_NIC_CONF1, 2618 EEPROM_FREQ, 2619 EEPROM_LED_AG_CONF, 2620 EEPROM_LED_ACT_CONF, 2621 EEPROM_LED_POLARITY, 2622 EEPROM_NIC_CONF2, 2623 EEPROM_LNA, 2624 EEPROM_RSSI_BG, 2625 EEPROM_RSSI_BG2, 2626 EEPROM_TXMIXER_GAIN_BG, 2627 EEPROM_RSSI_A, 2628 EEPROM_RSSI_A2, 2629 EEPROM_TXMIXER_GAIN_A, 2630 EEPROM_EIRP_MAX_TX_POWER, 2631 EEPROM_TXPOWER_DELTA, 2632 EEPROM_TXPOWER_BG1, 2633 EEPROM_TXPOWER_BG2, 2634 EEPROM_TSSI_BOUND_BG1, 2635 EEPROM_TSSI_BOUND_BG2, 2636 EEPROM_TSSI_BOUND_BG3, 2637 EEPROM_TSSI_BOUND_BG4, 2638 EEPROM_TSSI_BOUND_BG5, 2639 EEPROM_TXPOWER_A1, 2640 EEPROM_TXPOWER_A2, 2641 EEPROM_TXPOWER_INIT, 2642 EEPROM_TSSI_BOUND_A1, 2643 EEPROM_TSSI_BOUND_A2, 2644 EEPROM_TSSI_BOUND_A3, 2645 EEPROM_TSSI_BOUND_A4, 2646 EEPROM_TSSI_BOUND_A5, 2647 EEPROM_TXPOWER_BYRATE, 2648 EEPROM_BBP_START, 2649 2650 /* IDs for extended EEPROM format used by three-chain devices */ 2651 EEPROM_EXT_LNA2, 2652 EEPROM_EXT_TXPOWER_BG3, 2653 EEPROM_EXT_TXPOWER_A3, 2654 2655 /* New values must be added before this */ 2656 EEPROM_WORD_COUNT 2657}; 2658 2659/* 2660 * EEPROM Version 2661 */ 2662#define EEPROM_VERSION_FAE FIELD16(0x00ff) 2663#define EEPROM_VERSION_VERSION FIELD16(0xff00) 2664 2665/* 2666 * HW MAC address. 2667 */ 2668#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) 2669#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) 2670#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) 2671#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) 2672#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) 2673#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) 2674 2675/* 2676 * EEPROM NIC Configuration 0 2677 * RXPATH: 1: 1R, 2: 2R, 3: 3R 2678 * TXPATH: 1: 1T, 2: 2T, 3: 3T 2679 * RF_TYPE: RFIC type 2680 */ 2681#define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f) 2682#define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0) 2683#define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00) 2684 2685/* 2686 * EEPROM NIC Configuration 1 2687 * HW_RADIO: 0: disable, 1: enable 2688 * EXTERNAL_TX_ALC: 0: disable, 1: enable 2689 * EXTERNAL_LNA_2G: 0: disable, 1: enable 2690 * EXTERNAL_LNA_5G: 0: disable, 1: enable 2691 * CARDBUS_ACCEL: 0: enable, 1: disable 2692 * BW40M_SB_2G: 0: disable, 1: enable 2693 * BW40M_SB_5G: 0: disable, 1: enable 2694 * WPS_PBC: 0: disable, 1: enable 2695 * BW40M_2G: 0: enable, 1: disable 2696 * BW40M_5G: 0: enable, 1: disable 2697 * BROADBAND_EXT_LNA: 0: disable, 1: enable 2698 * ANT_DIVERSITY: 00: Disable, 01: Diversity, 2699 * 10: Main antenna, 11: Aux antenna 2700 * INTERNAL_TX_ALC: 0: disable, 1: enable 2701 * BT_COEXIST: 0: disable, 1: enable 2702 * DAC_TEST: 0: disable, 1: enable 2703 * EXTERNAL_TX0_PA: 0: disable, 1: enable (only on RT3352) 2704 * EXTERNAL_TX1_PA: 0: disable, 1: enable (only on RT3352) 2705 */ 2706#define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001) 2707#define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002) 2708#define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004) 2709#define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008) 2710#define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010) 2711#define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020) 2712#define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040) 2713#define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080) 2714#define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100) 2715#define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200) 2716#define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400) 2717#define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800) 2718#define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000) 2719#define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000) 2720#define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000) 2721#define EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352 FIELD16(0x4000) 2722#define EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352 FIELD16(0x8000) 2723 2724/* 2725 * EEPROM frequency 2726 */ 2727#define EEPROM_FREQ_OFFSET FIELD16(0x00ff) 2728#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00) 2729#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000) 2730 2731/* 2732 * EEPROM LED 2733 * POLARITY_RDY_G: Polarity RDY_G setting. 2734 * POLARITY_RDY_A: Polarity RDY_A setting. 2735 * POLARITY_ACT: Polarity ACT setting. 2736 * POLARITY_GPIO_0: Polarity GPIO0 setting. 2737 * POLARITY_GPIO_1: Polarity GPIO1 setting. 2738 * POLARITY_GPIO_2: Polarity GPIO2 setting. 2739 * POLARITY_GPIO_3: Polarity GPIO3 setting. 2740 * POLARITY_GPIO_4: Polarity GPIO4 setting. 2741 * LED_MODE: Led mode. 2742 */ 2743#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001) 2744#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002) 2745#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004) 2746#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008) 2747#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010) 2748#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020) 2749#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040) 2750#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080) 2751#define EEPROM_LED_LED_MODE FIELD16(0x1f00) 2752 2753/* 2754 * EEPROM NIC Configuration 2 2755 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream 2756 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream 2757 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved 2758 */ 2759#define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f) 2760#define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0) 2761#define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600) 2762#define EEPROM_NIC_CONF2_EXTERNAL_PA FIELD16(0x8000) 2763 2764/* 2765 * EEPROM LNA 2766 */ 2767#define EEPROM_LNA_BG FIELD16(0x00ff) 2768#define EEPROM_LNA_A0 FIELD16(0xff00) 2769 2770/* 2771 * EEPROM RSSI BG offset 2772 */ 2773#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff) 2774#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00) 2775 2776/* 2777 * EEPROM RSSI BG2 offset 2778 */ 2779#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff) 2780#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00) 2781 2782/* 2783 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2). 2784 */ 2785#define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007) 2786 2787/* 2788 * EEPROM RSSI A offset 2789 */ 2790#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff) 2791#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00) 2792 2793/* 2794 * EEPROM RSSI A2 offset 2795 */ 2796#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff) 2797#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00) 2798 2799/* 2800 * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2). 2801 */ 2802#define EEPROM_TXMIXER_GAIN_A_VAL FIELD16(0x0007) 2803 2804/* 2805 * EEPROM EIRP Maximum TX power values(unit: dbm) 2806 */ 2807#define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff) 2808#define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00) 2809 2810/* 2811 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power. 2812 * This is delta in 40MHZ. 2813 * VALUE: Tx Power dalta value, MAX=4(unit: dbm) 2814 * TYPE: 1: Plus the delta value, 0: minus the delta value 2815 * ENABLE: enable tx power compensation for 40BW 2816 */ 2817#define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f) 2818#define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040) 2819#define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080) 2820#define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00) 2821#define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000) 2822#define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000) 2823 2824/* 2825 * EEPROM TXPOWER 802.11BG 2826 */ 2827#define EEPROM_TXPOWER_BG_SIZE 7 2828#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff) 2829#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00) 2830 2831/* 2832 * EEPROM temperature compensation boundaries 802.11BG 2833 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be 2834 * reduced by (agc_step * -4) 2835 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be 2836 * reduced by (agc_step * -3) 2837 */ 2838#define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff) 2839#define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00) 2840 2841/* 2842 * EEPROM temperature compensation boundaries 802.11BG 2843 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be 2844 * reduced by (agc_step * -2) 2845 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be 2846 * reduced by (agc_step * -1) 2847 */ 2848#define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff) 2849#define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00) 2850 2851/* 2852 * EEPROM temperature compensation boundaries 802.11BG 2853 * REF: Reference TSSI value, no tx power changes needed 2854 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be 2855 * increased by (agc_step * 1) 2856 */ 2857#define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff) 2858#define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00) 2859 2860/* 2861 * EEPROM temperature compensation boundaries 802.11BG 2862 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be 2863 * increased by (agc_step * 2) 2864 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be 2865 * increased by (agc_step * 3) 2866 */ 2867#define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff) 2868#define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00) 2869 2870/* 2871 * EEPROM temperature compensation boundaries 802.11BG 2872 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be 2873 * increased by (agc_step * 4) 2874 * AGC_STEP: Temperature compensation step. 2875 */ 2876#define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff) 2877#define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00) 2878 2879/* 2880 * EEPROM TXPOWER 802.11A 2881 */ 2882#define EEPROM_TXPOWER_A_SIZE 6 2883#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff) 2884#define EEPROM_TXPOWER_A_2 FIELD16(0xff00) 2885 2886/* EEPROM_TXPOWER_{A,G} fields for RT3593 */ 2887#define EEPROM_TXPOWER_ALC FIELD8(0x1f) 2888#define EEPROM_TXPOWER_FINE_CTRL FIELD8(0xe0) 2889 2890/* 2891 * EEPROM temperature compensation boundaries 802.11A 2892 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be 2893 * reduced by (agc_step * -4) 2894 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be 2895 * reduced by (agc_step * -3) 2896 */ 2897#define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff) 2898#define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00) 2899 2900/* 2901 * EEPROM temperature compensation boundaries 802.11A 2902 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be 2903 * reduced by (agc_step * -2) 2904 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be 2905 * reduced by (agc_step * -1) 2906 */ 2907#define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff) 2908#define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00) 2909 2910/* 2911 * EEPROM temperature compensation boundaries 802.11A 2912 * REF: Reference TSSI value, no tx power changes needed 2913 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be 2914 * increased by (agc_step * 1) 2915 */ 2916#define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff) 2917#define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00) 2918 2919/* 2920 * EEPROM temperature compensation boundaries 802.11A 2921 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be 2922 * increased by (agc_step * 2) 2923 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be 2924 * increased by (agc_step * 3) 2925 */ 2926#define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff) 2927#define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00) 2928 2929/* 2930 * EEPROM temperature compensation boundaries 802.11A 2931 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be 2932 * increased by (agc_step * 4) 2933 * AGC_STEP: Temperature compensation step. 2934 */ 2935#define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff) 2936#define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00) 2937 2938/* 2939 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode 2940 */ 2941#define EEPROM_TXPOWER_BYRATE_SIZE 9 2942 2943#define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f) 2944#define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0) 2945#define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00) 2946#define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000) 2947 2948/* 2949 * EEPROM BBP. 2950 */ 2951#define EEPROM_BBP_SIZE 16 2952#define EEPROM_BBP_VALUE FIELD16(0x00ff) 2953#define EEPROM_BBP_REG_ID FIELD16(0xff00) 2954 2955/* EEPROM_EXT_LNA2 */ 2956#define EEPROM_EXT_LNA2_A1 FIELD16(0x00ff) 2957#define EEPROM_EXT_LNA2_A2 FIELD16(0xff00) 2958 2959/* 2960 * EEPROM IQ Calibration, unlike other entries those are byte addresses. 2961 */ 2962 2963#define EEPROM_IQ_GAIN_CAL_TX0_2G 0x130 2964#define EEPROM_IQ_PHASE_CAL_TX0_2G 0x131 2965#define EEPROM_IQ_GROUPDELAY_CAL_TX0_2G 0x132 2966#define EEPROM_IQ_GAIN_CAL_TX1_2G 0x133 2967#define EEPROM_IQ_PHASE_CAL_TX1_2G 0x134 2968#define EEPROM_IQ_GROUPDELAY_CAL_TX1_2G 0x135 2969#define EEPROM_IQ_GAIN_CAL_RX0_2G 0x136 2970#define EEPROM_IQ_PHASE_CAL_RX0_2G 0x137 2971#define EEPROM_IQ_GROUPDELAY_CAL_RX0_2G 0x138 2972#define EEPROM_IQ_GAIN_CAL_RX1_2G 0x139 2973#define EEPROM_IQ_PHASE_CAL_RX1_2G 0x13A 2974#define EEPROM_IQ_GROUPDELAY_CAL_RX1_2G 0x13B 2975#define EEPROM_RF_IQ_COMPENSATION_CONTROL 0x13C 2976#define EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL 0x13D 2977#define EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G 0x144 2978#define EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G 0x145 2979#define EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G 0X146 2980#define EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G 0x147 2981#define EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G 0x148 2982#define EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G 0x149 2983#define EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G 0x14A 2984#define EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G 0x14B 2985#define EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G 0X14C 2986#define EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G 0x14D 2987#define EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G 0x14E 2988#define EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G 0x14F 2989#define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH36_TO_CH64_5G 0x150 2990#define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH36_TO_CH64_5G 0x151 2991#define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH100_TO_CH138_5G 0x152 2992#define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH100_TO_CH138_5G 0x153 2993#define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH140_TO_CH165_5G 0x154 2994#define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH140_TO_CH165_5G 0x155 2995#define EEPROM_IQ_GAIN_CAL_RX0_CH36_TO_CH64_5G 0x156 2996#define EEPROM_IQ_PHASE_CAL_RX0_CH36_TO_CH64_5G 0x157 2997#define EEPROM_IQ_GAIN_CAL_RX0_CH100_TO_CH138_5G 0X158 2998#define EEPROM_IQ_PHASE_CAL_RX0_CH100_TO_CH138_5G 0x159 2999#define EEPROM_IQ_GAIN_CAL_RX0_CH140_TO_CH165_5G 0x15A 3000#define EEPROM_IQ_PHASE_CAL_RX0_CH140_TO_CH165_5G 0x15B 3001#define EEPROM_IQ_GAIN_CAL_RX1_CH36_TO_CH64_5G 0x15C 3002#define EEPROM_IQ_PHASE_CAL_RX1_CH36_TO_CH64_5G 0x15D 3003#define EEPROM_IQ_GAIN_CAL_RX1_CH100_TO_CH138_5G 0X15E 3004#define EEPROM_IQ_PHASE_CAL_RX1_CH100_TO_CH138_5G 0x15F 3005#define EEPROM_IQ_GAIN_CAL_RX1_CH140_TO_CH165_5G 0x160 3006#define EEPROM_IQ_PHASE_CAL_RX1_CH140_TO_CH165_5G 0x161 3007#define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH36_TO_CH64_5G 0x162 3008#define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH36_TO_CH64_5G 0x163 3009#define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH100_TO_CH138_5G 0x164 3010#define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH100_TO_CH138_5G 0x165 3011#define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH140_TO_CH165_5G 0x166 3012#define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH140_TO_CH165_5G 0x167 3013 3014/* 3015 * MCU mailbox commands. 3016 * MCU_SLEEP - go to power-save mode. 3017 * arg1: 1: save as much power as possible, 0: save less power. 3018 * status: 1: success, 2: already asleep, 3019 * 3: maybe MAC is busy so can't finish this task. 3020 * MCU_RADIO_OFF 3021 * arg0: 0: do power-saving, NOT turn off radio. 3022 */ 3023#define MCU_SLEEP 0x30 3024#define MCU_WAKEUP 0x31 3025#define MCU_RADIO_OFF 0x35 3026#define MCU_CURRENT 0x36 3027#define MCU_LED 0x50 3028#define MCU_LED_STRENGTH 0x51 3029#define MCU_LED_AG_CONF 0x52 3030#define MCU_LED_ACT_CONF 0x53 3031#define MCU_LED_LED_POLARITY 0x54 3032#define MCU_RADAR 0x60 3033#define MCU_BOOT_SIGNAL 0x72 3034#define MCU_ANT_SELECT 0X73 3035#define MCU_FREQ_OFFSET 0x74 3036#define MCU_BBP_SIGNAL 0x80 3037#define MCU_POWER_SAVE 0x83 3038#define MCU_BAND_SELECT 0x91 3039 3040/* 3041 * MCU mailbox tokens 3042 */ 3043#define TOKEN_SLEEP 1 3044#define TOKEN_RADIO_OFF 2 3045#define TOKEN_WAKEUP 3 3046 3047 3048/* 3049 * DMA descriptor defines. 3050 */ 3051 3052#define TXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32)) 3053#define TXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32)) 3054 3055#define RXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32)) 3056#define RXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32)) 3057#define RXWI_DESC_SIZE_6WORDS (6 * sizeof(__le32)) 3058 3059/* 3060 * TX WI structure 3061 */ 3062 3063/* 3064 * Word0 3065 * FRAG: 1 To inform TKIP engine this is a fragment. 3066 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode 3067 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs 3068 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will 3069 * duplicate the frame to both channels). 3070 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED 3071 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will 3072 * aggregate consecutive frames with the same RA and QoS TID. If 3073 * a frame A with the same RA and QoS TID but AMPDU=0 is queued 3074 * directly after a frame B with AMPDU=1, frame A might still 3075 * get aggregated into the AMPDU started by frame B. So, setting 3076 * AMPDU to 0 does _not_ necessarily mean the frame is sent as 3077 * MPDU, it can still end up in an AMPDU if the previous frame 3078 * was tagged as AMPDU. 3079 */ 3080#define TXWI_W0_FRAG FIELD32(0x00000001) 3081#define TXWI_W0_MIMO_PS FIELD32(0x00000002) 3082#define TXWI_W0_CF_ACK FIELD32(0x00000004) 3083#define TXWI_W0_TS FIELD32(0x00000008) 3084#define TXWI_W0_AMPDU FIELD32(0x00000010) 3085#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0) 3086#define TXWI_W0_TX_OP FIELD32(0x00000300) 3087#define TXWI_W0_MCS FIELD32(0x007f0000) 3088#define TXWI_W0_BW FIELD32(0x00800000) 3089#define TXWI_W0_SHORT_GI FIELD32(0x01000000) 3090#define TXWI_W0_STBC FIELD32(0x06000000) 3091#define TXWI_W0_IFS FIELD32(0x08000000) 3092#define TXWI_W0_PHYMODE FIELD32(0xc0000000) 3093 3094/* 3095 * Word1 3096 * ACK: 0: No Ack needed, 1: Ack needed 3097 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number 3098 * BW_WIN_SIZE: BA windows size of the recipient 3099 * WIRELESS_CLI_ID: Client ID for WCID table access 3100 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame 3101 * PACKETID: Will be latched into the TX_STA_FIFO register once the according 3102 * frame was processed. If multiple frames are aggregated together 3103 * (AMPDU==1) the reported tx status will always contain the packet 3104 * id of the first frame. 0: Don't report tx status for this frame. 3105 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3) 3106 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3) 3107 * This identification number is calculated by ((idx % 3) + 1). 3108 * The (+1) is required to prevent PACKETID to become 0. 3109 */ 3110#define TXWI_W1_ACK FIELD32(0x00000001) 3111#define TXWI_W1_NSEQ FIELD32(0x00000002) 3112#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc) 3113#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00) 3114#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) 3115#define TXWI_W1_PACKETID FIELD32(0xf0000000) 3116#define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000) 3117#define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000) 3118 3119/* 3120 * Word2 3121 */ 3122#define TXWI_W2_IV FIELD32(0xffffffff) 3123 3124/* 3125 * Word3 3126 */ 3127#define TXWI_W3_EIV FIELD32(0xffffffff) 3128 3129/* 3130 * RX WI structure 3131 */ 3132 3133/* 3134 * Word0 3135 */ 3136#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff) 3137#define RXWI_W0_KEY_INDEX FIELD32(0x00000300) 3138#define RXWI_W0_BSSID FIELD32(0x00001c00) 3139#define RXWI_W0_UDF FIELD32(0x0000e000) 3140#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) 3141#define RXWI_W0_TID FIELD32(0xf0000000) 3142 3143/* 3144 * Word1 3145 */ 3146#define RXWI_W1_FRAG FIELD32(0x0000000f) 3147#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0) 3148#define RXWI_W1_MCS FIELD32(0x007f0000) 3149#define RXWI_W1_BW FIELD32(0x00800000) 3150#define RXWI_W1_SHORT_GI FIELD32(0x01000000) 3151#define RXWI_W1_STBC FIELD32(0x06000000) 3152#define RXWI_W1_PHYMODE FIELD32(0xc0000000) 3153 3154/* 3155 * Word2 3156 */ 3157#define RXWI_W2_RSSI0 FIELD32(0x000000ff) 3158#define RXWI_W2_RSSI1 FIELD32(0x0000ff00) 3159#define RXWI_W2_RSSI2 FIELD32(0x00ff0000) 3160 3161/* 3162 * Word3 3163 */ 3164#define RXWI_W3_SNR0 FIELD32(0x000000ff) 3165#define RXWI_W3_SNR1 FIELD32(0x0000ff00) 3166 3167/* 3168 * Macros for converting txpower from EEPROM to mac80211 value 3169 * and from mac80211 value to register value. 3170 */ 3171#define MIN_G_TXPOWER 0 3172#define MIN_A_TXPOWER -7 3173#define MAX_G_TXPOWER 31 3174#define MAX_A_TXPOWER 15 3175#define DEFAULT_TXPOWER 5 3176 3177#define MIN_A_TXPOWER_3593 0 3178#define MAX_A_TXPOWER_3593 31 3179 3180#define TXPOWER_G_FROM_DEV(__txpower) \ 3181 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) 3182 3183#define TXPOWER_A_FROM_DEV(__txpower) \ 3184 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) 3185 3186/* 3187 * Board's maximun TX power limitation 3188 */ 3189#define EIRP_MAX_TX_POWER_LIMIT 0x50 3190 3191/* 3192 * Number of TBTT intervals after which we have to adjust 3193 * the hw beacon timer. 3194 */ 3195#define BCN_TBTT_OFFSET 64 3196 3197/* Watchdog type mask */ 3198#define RT2800_WATCHDOG_HANG BIT(0) 3199#define RT2800_WATCHDOG_DMA_BUSY BIT(1) 3200 3201#endif /* RT2800_H */ 3202