1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * (c) Copyright 2002-2010, Ralink Technology, Inc.
4 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
5 */
6#ifndef _MT76X0_PHY_H_
7#define _MT76X0_PHY_H_
8
9#define RF_G_BAND	0x0100
10#define RF_A_BAND	0x0200
11#define RF_A_BAND_LB	0x0400
12#define RF_A_BAND_MB	0x0800
13#define RF_A_BAND_HB	0x1000
14#define RF_A_BAND_11J	0x2000
15
16#define RF_BW_20        1
17#define RF_BW_40        2
18#define RF_BW_10        4
19#define RF_BW_80        8
20
21#define MT_RF(bank, reg)		((bank) << 16 | (reg))
22#define MT_RF_BANK(offset)		((offset) >> 16)
23#define MT_RF_REG(offset)		((offset) & 0xff)
24
25#define MT_RF_VCO_BP_CLOSE_LOOP		BIT(3)
26#define MT_RF_VCO_BP_CLOSE_LOOP_MASK	GENMASK(3, 0)
27#define MT_RF_VCO_CAL_MASK		GENMASK(2, 0)
28#define MT_RF_START_TIME		0x3
29#define MT_RF_START_TIME_MASK		GENMASK(2, 0)
30#define MT_RF_SETTLE_TIME_MASK		GENMASK(6, 4)
31
32#define MT_RF_PLL_DEN_MASK		GENMASK(4, 0)
33#define MT_RF_PLL_K_MASK		GENMASK(4, 0)
34#define MT_RF_SDM_RESET_MASK		BIT(7)
35#define MT_RF_SDM_MASH_PRBS_MASK	GENMASK(6, 2)
36#define MT_RF_SDM_BP_MASK		BIT(1)
37#define MT_RF_ISI_ISO_MASK		GENMASK(7, 6)
38#define MT_RF_PFD_DLY_MASK		GENMASK(5, 4)
39#define MT_RF_CLK_SEL_MASK		GENMASK(3, 2)
40#define MT_RF_XO_DIV_MASK		GENMASK(1, 0)
41
42struct mt76x0_bbp_switch_item {
43	u16 bw_band;
44	struct mt76_reg_pair reg_pair;
45};
46
47struct mt76x0_rf_switch_item {
48	u32 rf_bank_reg;
49	u16 bw_band;
50	u8 value;
51};
52
53struct mt76x0_freq_item {
54	u8 channel;
55	u32 band;
56	u8 pllR37;
57	u8 pllR36;
58	u8 pllR35;
59	u8 pllR34;
60	u8 pllR33;
61	u8 pllR32_b7b5;
62	u8 pllR32_b4b0; /* PLL_DEN (Denomina - 8) */
63	u8 pllR31_b7b5;
64	u8 pllR31_b4b0; /* PLL_K (Nominator *)*/
65	u8 pllR30_b7;	/* sdm_reset_n */
66	u8 pllR30_b6b2; /* sdmmash_prbs,sin */
67	u8 pllR30_b1;	/* sdm_bp */
68	u16 pll_n;	/* R30<0>, R29<7:0> (hex) */
69	u8 pllR28_b7b6; /* isi,iso */
70	u8 pllR28_b5b4;	/* pfd_dly */
71	u8 pllR28_b3b2;	/* clksel option */
72	u32 pll_sdm_k;	/* R28<1:0>, R27<7:0>, R26<7:0> (hex) SDM_k */
73	u8 pllR24_b1b0;	/* xo_div */
74};
75
76struct mt76x0_rate_pwr_item {
77	s8 mcs_power;
78	u8 rf_pa_mode;
79};
80
81struct mt76x0_rate_pwr_tab {
82	struct mt76x0_rate_pwr_item cck[4];
83	struct mt76x0_rate_pwr_item ofdm[8];
84	struct mt76x0_rate_pwr_item ht[8];
85	struct mt76x0_rate_pwr_item vht[10];
86	struct mt76x0_rate_pwr_item stbc[8];
87	struct mt76x0_rate_pwr_item mcs32;
88};
89
90#endif /* _MT76X0_PHY_H_ */
91