1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Analog Devices AD7944/85/86 PulSAR ADC family driver. 4 * 5 * Copyright 2024 Analog Devices, Inc. 6 * Copyright 2024 BayLibre, SAS 7 */ 8 9#include <linux/align.h> 10#include <linux/bitfield.h> 11#include <linux/bitops.h> 12#include <linux/delay.h> 13#include <linux/device.h> 14#include <linux/err.h> 15#include <linux/gpio/consumer.h> 16#include <linux/module.h> 17#include <linux/property.h> 18#include <linux/regulator/consumer.h> 19#include <linux/spi/spi.h> 20#include <linux/string_helpers.h> 21 22#include <linux/iio/iio.h> 23#include <linux/iio/sysfs.h> 24#include <linux/iio/trigger_consumer.h> 25#include <linux/iio/triggered_buffer.h> 26 27#define AD7944_INTERNAL_REF_MV 4096 28 29struct ad7944_timing_spec { 30 /* Normal mode max conversion time (t_{CONV}). */ 31 unsigned int conv_ns; 32 /* TURBO mode max conversion time (t_{CONV}). */ 33 unsigned int turbo_conv_ns; 34}; 35 36enum ad7944_spi_mode { 37 /* datasheet calls this "4-wire mode" */ 38 AD7944_SPI_MODE_DEFAULT, 39 /* datasheet calls this "3-wire mode" (not related to SPI_3WIRE!) */ 40 AD7944_SPI_MODE_SINGLE, 41 /* datasheet calls this "chain mode" */ 42 AD7944_SPI_MODE_CHAIN, 43}; 44 45/* maps adi,spi-mode property value to enum */ 46static const char * const ad7944_spi_modes[] = { 47 [AD7944_SPI_MODE_DEFAULT] = "", 48 [AD7944_SPI_MODE_SINGLE] = "single", 49 [AD7944_SPI_MODE_CHAIN] = "chain", 50}; 51 52struct ad7944_adc { 53 struct spi_device *spi; 54 enum ad7944_spi_mode spi_mode; 55 struct spi_transfer xfers[3]; 56 struct spi_message msg; 57 void *chain_mode_buf; 58 /* Chip-specific timing specifications. */ 59 const struct ad7944_timing_spec *timing_spec; 60 /* GPIO connected to CNV pin. */ 61 struct gpio_desc *cnv; 62 /* Optional GPIO to enable turbo mode. */ 63 struct gpio_desc *turbo; 64 /* Indicates TURBO is hard-wired to be always enabled. */ 65 bool always_turbo; 66 /* Reference voltage (millivolts). */ 67 unsigned int ref_mv; 68 69 /* 70 * DMA (thus cache coherency maintenance) requires the 71 * transfer buffers to live in their own cache lines. 72 */ 73 struct { 74 union { 75 u16 u16; 76 u32 u32; 77 } raw; 78 u64 timestamp __aligned(8); 79 } sample __aligned(IIO_DMA_MINALIGN); 80}; 81 82/* quite time before CNV rising edge */ 83#define T_QUIET_NS 20 84 85static const struct ad7944_timing_spec ad7944_timing_spec = { 86 .conv_ns = 420, 87 .turbo_conv_ns = 320, 88}; 89 90static const struct ad7944_timing_spec ad7986_timing_spec = { 91 .conv_ns = 500, 92 .turbo_conv_ns = 400, 93}; 94 95struct ad7944_chip_info { 96 const char *name; 97 const struct ad7944_timing_spec *timing_spec; 98 const struct iio_chan_spec channels[2]; 99}; 100 101/* 102 * AD7944_DEFINE_CHIP_INFO - Define a chip info structure for a specific chip 103 * @_name: The name of the chip 104 * @_ts: The timing specification for the chip 105 * @_bits: The number of bits in the conversion result 106 * @_diff: Whether the chip is true differential or not 107 */ 108#define AD7944_DEFINE_CHIP_INFO(_name, _ts, _bits, _diff) \ 109static const struct ad7944_chip_info _name##_chip_info = { \ 110 .name = #_name, \ 111 .timing_spec = &_ts##_timing_spec, \ 112 .channels = { \ 113 { \ 114 .type = IIO_VOLTAGE, \ 115 .indexed = 1, \ 116 .differential = _diff, \ 117 .channel = 0, \ 118 .channel2 = _diff ? 1 : 0, \ 119 .scan_index = 0, \ 120 .scan_type.sign = _diff ? 's' : 'u', \ 121 .scan_type.realbits = _bits, \ 122 .scan_type.storagebits = _bits > 16 ? 32 : 16, \ 123 .scan_type.endianness = IIO_CPU, \ 124 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 125 | BIT(IIO_CHAN_INFO_SCALE), \ 126 }, \ 127 IIO_CHAN_SOFT_TIMESTAMP(1), \ 128 }, \ 129} 130 131/* pseudo-differential with ground sense */ 132AD7944_DEFINE_CHIP_INFO(ad7944, ad7944, 14, 0); 133AD7944_DEFINE_CHIP_INFO(ad7985, ad7944, 16, 0); 134/* fully differential */ 135AD7944_DEFINE_CHIP_INFO(ad7986, ad7986, 18, 1); 136 137static void ad7944_unoptimize_msg(void *msg) 138{ 139 spi_unoptimize_message(msg); 140} 141 142static int ad7944_3wire_cs_mode_init_msg(struct device *dev, struct ad7944_adc *adc, 143 const struct iio_chan_spec *chan) 144{ 145 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns 146 : adc->timing_spec->conv_ns; 147 struct spi_transfer *xfers = adc->xfers; 148 int ret; 149 150 /* 151 * NB: can get better performance from some SPI controllers if we use 152 * the same bits_per_word in every transfer. 153 */ 154 xfers[0].bits_per_word = chan->scan_type.realbits; 155 /* 156 * CS is tied to CNV and we need a low to high transition to start the 157 * conversion, so place CNV low for t_QUIET to prepare for this. 158 */ 159 xfers[0].delay.value = T_QUIET_NS; 160 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS; 161 162 /* 163 * CS has to be high for full conversion time to avoid triggering the 164 * busy indication. 165 */ 166 xfers[1].cs_off = 1; 167 xfers[1].delay.value = t_conv_ns; 168 xfers[1].delay.unit = SPI_DELAY_UNIT_NSECS; 169 xfers[1].bits_per_word = chan->scan_type.realbits; 170 171 /* Then we can read the data during the acquisition phase */ 172 xfers[2].rx_buf = &adc->sample.raw; 173 xfers[2].len = BITS_TO_BYTES(chan->scan_type.storagebits); 174 xfers[2].bits_per_word = chan->scan_type.realbits; 175 176 spi_message_init_with_transfers(&adc->msg, xfers, 3); 177 178 ret = spi_optimize_message(adc->spi, &adc->msg); 179 if (ret) 180 return ret; 181 182 return devm_add_action_or_reset(dev, ad7944_unoptimize_msg, &adc->msg); 183} 184 185static int ad7944_4wire_mode_init_msg(struct device *dev, struct ad7944_adc *adc, 186 const struct iio_chan_spec *chan) 187{ 188 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns 189 : adc->timing_spec->conv_ns; 190 struct spi_transfer *xfers = adc->xfers; 191 int ret; 192 193 /* 194 * NB: can get better performance from some SPI controllers if we use 195 * the same bits_per_word in every transfer. 196 */ 197 xfers[0].bits_per_word = chan->scan_type.realbits; 198 /* 199 * CS has to be high for full conversion time to avoid triggering the 200 * busy indication. 201 */ 202 xfers[0].cs_off = 1; 203 xfers[0].delay.value = t_conv_ns; 204 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS; 205 206 xfers[1].rx_buf = &adc->sample.raw; 207 xfers[1].len = BITS_TO_BYTES(chan->scan_type.storagebits); 208 xfers[1].bits_per_word = chan->scan_type.realbits; 209 210 spi_message_init_with_transfers(&adc->msg, xfers, 2); 211 212 ret = spi_optimize_message(adc->spi, &adc->msg); 213 if (ret) 214 return ret; 215 216 return devm_add_action_or_reset(dev, ad7944_unoptimize_msg, &adc->msg); 217} 218 219static int ad7944_chain_mode_init_msg(struct device *dev, struct ad7944_adc *adc, 220 const struct iio_chan_spec *chan, 221 u32 n_chain_dev) 222{ 223 struct spi_transfer *xfers = adc->xfers; 224 int ret; 225 226 /* 227 * NB: SCLK has to be low before we toggle CS to avoid triggering the 228 * busy indication. 229 */ 230 if (adc->spi->mode & SPI_CPOL) 231 return dev_err_probe(dev, -EINVAL, 232 "chain mode requires ~SPI_CPOL\n"); 233 234 /* 235 * We only support CNV connected to CS in chain mode and we need CNV 236 * to be high during the transfer to trigger the conversion. 237 */ 238 if (!(adc->spi->mode & SPI_CS_HIGH)) 239 return dev_err_probe(dev, -EINVAL, 240 "chain mode requires SPI_CS_HIGH\n"); 241 242 /* CNV has to be high for full conversion time before reading data. */ 243 xfers[0].delay.value = adc->timing_spec->conv_ns; 244 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS; 245 246 xfers[1].rx_buf = adc->chain_mode_buf; 247 xfers[1].len = BITS_TO_BYTES(chan->scan_type.storagebits) * n_chain_dev; 248 xfers[1].bits_per_word = chan->scan_type.realbits; 249 250 spi_message_init_with_transfers(&adc->msg, xfers, 2); 251 252 ret = spi_optimize_message(adc->spi, &adc->msg); 253 if (ret) 254 return ret; 255 256 return devm_add_action_or_reset(dev, ad7944_unoptimize_msg, &adc->msg); 257} 258 259/** 260 * ad7944_convert_and_acquire - Perform a single conversion and acquisition 261 * @adc: The ADC device structure 262 * @chan: The channel specification 263 * Return: 0 on success, a negative error code on failure 264 * 265 * Perform a conversion and acquisition of a single sample using the 266 * pre-optimized adc->msg. 267 * 268 * Upon successful return adc->sample.raw will contain the conversion result 269 * (or adc->chain_mode_buf if the device is using chain mode). 270 */ 271static int ad7944_convert_and_acquire(struct ad7944_adc *adc, 272 const struct iio_chan_spec *chan) 273{ 274 int ret; 275 276 /* 277 * In 4-wire mode, the CNV line is held high for the entire conversion 278 * and acquisition process. In other modes adc->cnv is NULL and is 279 * ignored (CS is wired to CNV in those cases). 280 */ 281 gpiod_set_value_cansleep(adc->cnv, 1); 282 ret = spi_sync(adc->spi, &adc->msg); 283 gpiod_set_value_cansleep(adc->cnv, 0); 284 285 return ret; 286} 287 288static int ad7944_single_conversion(struct ad7944_adc *adc, 289 const struct iio_chan_spec *chan, 290 int *val) 291{ 292 int ret; 293 294 ret = ad7944_convert_and_acquire(adc, chan); 295 if (ret) 296 return ret; 297 298 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) { 299 if (chan->scan_type.storagebits > 16) 300 *val = ((u32 *)adc->chain_mode_buf)[chan->scan_index]; 301 else 302 *val = ((u16 *)adc->chain_mode_buf)[chan->scan_index]; 303 } else { 304 if (chan->scan_type.storagebits > 16) 305 *val = adc->sample.raw.u32; 306 else 307 *val = adc->sample.raw.u16; 308 } 309 310 if (chan->scan_type.sign == 's') 311 *val = sign_extend32(*val, chan->scan_type.realbits - 1); 312 313 return IIO_VAL_INT; 314} 315 316static int ad7944_read_raw(struct iio_dev *indio_dev, 317 const struct iio_chan_spec *chan, 318 int *val, int *val2, long info) 319{ 320 struct ad7944_adc *adc = iio_priv(indio_dev); 321 int ret; 322 323 switch (info) { 324 case IIO_CHAN_INFO_RAW: 325 ret = iio_device_claim_direct_mode(indio_dev); 326 if (ret) 327 return ret; 328 329 ret = ad7944_single_conversion(adc, chan, val); 330 iio_device_release_direct_mode(indio_dev); 331 return ret; 332 333 case IIO_CHAN_INFO_SCALE: 334 switch (chan->type) { 335 case IIO_VOLTAGE: 336 *val = adc->ref_mv; 337 338 if (chan->scan_type.sign == 's') 339 *val2 = chan->scan_type.realbits - 1; 340 else 341 *val2 = chan->scan_type.realbits; 342 343 return IIO_VAL_FRACTIONAL_LOG2; 344 default: 345 return -EINVAL; 346 } 347 348 default: 349 return -EINVAL; 350 } 351} 352 353static const struct iio_info ad7944_iio_info = { 354 .read_raw = &ad7944_read_raw, 355}; 356 357static irqreturn_t ad7944_trigger_handler(int irq, void *p) 358{ 359 struct iio_poll_func *pf = p; 360 struct iio_dev *indio_dev = pf->indio_dev; 361 struct ad7944_adc *adc = iio_priv(indio_dev); 362 int ret; 363 364 ret = ad7944_convert_and_acquire(adc, &indio_dev->channels[0]); 365 if (ret) 366 goto out; 367 368 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) 369 iio_push_to_buffers_with_timestamp(indio_dev, adc->chain_mode_buf, 370 pf->timestamp); 371 else 372 iio_push_to_buffers_with_timestamp(indio_dev, &adc->sample.raw, 373 pf->timestamp); 374 375out: 376 iio_trigger_notify_done(indio_dev->trig); 377 378 return IRQ_HANDLED; 379} 380 381/** 382 * ad7944_chain_mode_alloc - allocate and initialize channel specs and buffers 383 * for daisy-chained devices 384 * @dev: The device for devm_ functions 385 * @chan_template: The channel template for the devices (array of 2 channels 386 * voltage and timestamp) 387 * @n_chain_dev: The number of devices in the chain 388 * @chain_chan: Pointer to receive the allocated channel specs 389 * @chain_mode_buf: Pointer to receive the allocated rx buffer 390 * @chain_scan_masks: Pointer to receive the allocated scan masks 391 * Return: 0 on success, a negative error code on failure 392 */ 393static int ad7944_chain_mode_alloc(struct device *dev, 394 const struct iio_chan_spec *chan_template, 395 u32 n_chain_dev, 396 struct iio_chan_spec **chain_chan, 397 void **chain_mode_buf, 398 unsigned long **chain_scan_masks) 399{ 400 struct iio_chan_spec *chan; 401 size_t chain_mode_buf_size; 402 unsigned long *scan_masks; 403 void *buf; 404 int i; 405 406 /* 1 channel for each device in chain plus 1 for soft timestamp */ 407 408 chan = devm_kcalloc(dev, n_chain_dev + 1, sizeof(*chan), GFP_KERNEL); 409 if (!chan) 410 return -ENOMEM; 411 412 for (i = 0; i < n_chain_dev; i++) { 413 chan[i] = chan_template[0]; 414 415 if (chan_template[0].differential) { 416 chan[i].channel = 2 * i; 417 chan[i].channel2 = 2 * i + 1; 418 } else { 419 chan[i].channel = i; 420 } 421 422 chan[i].scan_index = i; 423 } 424 425 /* soft timestamp */ 426 chan[i] = chan_template[1]; 427 chan[i].scan_index = i; 428 429 *chain_chan = chan; 430 431 /* 1 word for each voltage channel + aligned u64 for timestamp */ 432 433 chain_mode_buf_size = ALIGN(n_chain_dev * 434 BITS_TO_BYTES(chan[0].scan_type.storagebits), sizeof(u64)) 435 + sizeof(u64); 436 buf = devm_kzalloc(dev, chain_mode_buf_size, GFP_KERNEL); 437 if (!buf) 438 return -ENOMEM; 439 440 *chain_mode_buf = buf; 441 442 /* 443 * Have to limit n_chain_dev due to current implementation of 444 * available_scan_masks. 445 */ 446 if (n_chain_dev > BITS_PER_LONG) 447 return dev_err_probe(dev, -EINVAL, 448 "chain is limited to 32 devices\n"); 449 450 scan_masks = devm_kcalloc(dev, 2, sizeof(*scan_masks), GFP_KERNEL); 451 if (!scan_masks) 452 return -ENOMEM; 453 454 /* 455 * Scan mask is needed since we always have to read all devices in the 456 * chain in one SPI transfer. 457 */ 458 scan_masks[0] = GENMASK(n_chain_dev - 1, 0); 459 460 *chain_scan_masks = scan_masks; 461 462 return 0; 463} 464 465static const char * const ad7944_power_supplies[] = { 466 "avdd", "dvdd", "bvdd", "vio" 467}; 468 469static void ad7944_ref_disable(void *ref) 470{ 471 regulator_disable(ref); 472} 473 474static int ad7944_probe(struct spi_device *spi) 475{ 476 const struct ad7944_chip_info *chip_info; 477 struct device *dev = &spi->dev; 478 struct iio_dev *indio_dev; 479 struct ad7944_adc *adc; 480 bool have_refin = false; 481 struct regulator *ref; 482 struct iio_chan_spec *chain_chan; 483 unsigned long *chain_scan_masks; 484 u32 n_chain_dev; 485 int ret; 486 487 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 488 if (!indio_dev) 489 return -ENOMEM; 490 491 adc = iio_priv(indio_dev); 492 adc->spi = spi; 493 494 chip_info = spi_get_device_match_data(spi); 495 if (!chip_info) 496 return dev_err_probe(dev, -EINVAL, "no chip info\n"); 497 498 adc->timing_spec = chip_info->timing_spec; 499 500 ret = device_property_match_property_string(dev, "adi,spi-mode", 501 ad7944_spi_modes, 502 ARRAY_SIZE(ad7944_spi_modes)); 503 /* absence of adi,spi-mode property means default mode */ 504 if (ret == -EINVAL) 505 adc->spi_mode = AD7944_SPI_MODE_DEFAULT; 506 else if (ret < 0) 507 return dev_err_probe(dev, ret, 508 "getting adi,spi-mode property failed\n"); 509 else 510 adc->spi_mode = ret; 511 512 /* 513 * Some chips use unusual word sizes, so check now instead of waiting 514 * for the first xfer. 515 */ 516 if (!spi_is_bpw_supported(spi, chip_info->channels[0].scan_type.realbits)) 517 return dev_err_probe(dev, -EINVAL, 518 "SPI host does not support %d bits per word\n", 519 chip_info->channels[0].scan_type.realbits); 520 521 ret = devm_regulator_bulk_get_enable(dev, 522 ARRAY_SIZE(ad7944_power_supplies), 523 ad7944_power_supplies); 524 if (ret) 525 return dev_err_probe(dev, ret, 526 "failed to get and enable supplies\n"); 527 528 /* 529 * Sort out what is being used for the reference voltage. Options are: 530 * - internal reference: neither REF or REFIN is connected 531 * - internal reference with external buffer: REF not connected, REFIN 532 * is connected 533 * - external reference: REF is connected, REFIN is not connected 534 */ 535 536 ref = devm_regulator_get_optional(dev, "ref"); 537 if (IS_ERR(ref)) { 538 if (PTR_ERR(ref) != -ENODEV) 539 return dev_err_probe(dev, PTR_ERR(ref), 540 "failed to get REF supply\n"); 541 542 ref = NULL; 543 } 544 545 ret = devm_regulator_get_enable_optional(dev, "refin"); 546 if (ret == 0) 547 have_refin = true; 548 else if (ret != -ENODEV) 549 return dev_err_probe(dev, ret, 550 "failed to get and enable REFIN supply\n"); 551 552 if (have_refin && ref) 553 return dev_err_probe(dev, -EINVAL, 554 "cannot have both refin and ref supplies\n"); 555 556 if (ref) { 557 ret = regulator_enable(ref); 558 if (ret) 559 return dev_err_probe(dev, ret, 560 "failed to enable REF supply\n"); 561 562 ret = devm_add_action_or_reset(dev, ad7944_ref_disable, ref); 563 if (ret) 564 return ret; 565 566 ret = regulator_get_voltage(ref); 567 if (ret < 0) 568 return dev_err_probe(dev, ret, 569 "failed to get REF voltage\n"); 570 571 /* external reference */ 572 adc->ref_mv = ret / 1000; 573 } else { 574 /* internal reference */ 575 adc->ref_mv = AD7944_INTERNAL_REF_MV; 576 } 577 578 adc->cnv = devm_gpiod_get_optional(dev, "cnv", GPIOD_OUT_LOW); 579 if (IS_ERR(adc->cnv)) 580 return dev_err_probe(dev, PTR_ERR(adc->cnv), 581 "failed to get CNV GPIO\n"); 582 583 if (!adc->cnv && adc->spi_mode == AD7944_SPI_MODE_DEFAULT) 584 return dev_err_probe(&spi->dev, -EINVAL, "CNV GPIO is required\n"); 585 if (adc->cnv && adc->spi_mode != AD7944_SPI_MODE_DEFAULT) 586 return dev_err_probe(&spi->dev, -EINVAL, 587 "CNV GPIO in single and chain mode is not currently supported\n"); 588 589 adc->turbo = devm_gpiod_get_optional(dev, "turbo", GPIOD_OUT_LOW); 590 if (IS_ERR(adc->turbo)) 591 return dev_err_probe(dev, PTR_ERR(adc->turbo), 592 "failed to get TURBO GPIO\n"); 593 594 adc->always_turbo = device_property_present(dev, "adi,always-turbo"); 595 596 if (adc->turbo && adc->always_turbo) 597 return dev_err_probe(dev, -EINVAL, 598 "cannot have both turbo-gpios and adi,always-turbo\n"); 599 600 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN && adc->always_turbo) 601 return dev_err_probe(dev, -EINVAL, 602 "cannot have both chain mode and always turbo\n"); 603 604 switch (adc->spi_mode) { 605 case AD7944_SPI_MODE_DEFAULT: 606 ret = ad7944_4wire_mode_init_msg(dev, adc, &chip_info->channels[0]); 607 if (ret) 608 return ret; 609 610 break; 611 case AD7944_SPI_MODE_SINGLE: 612 ret = ad7944_3wire_cs_mode_init_msg(dev, adc, &chip_info->channels[0]); 613 if (ret) 614 return ret; 615 616 break; 617 case AD7944_SPI_MODE_CHAIN: 618 ret = device_property_read_u32(dev, "#daisy-chained-devices", 619 &n_chain_dev); 620 if (ret) 621 return dev_err_probe(dev, ret, 622 "failed to get #daisy-chained-devices\n"); 623 624 ret = ad7944_chain_mode_alloc(dev, chip_info->channels, 625 n_chain_dev, &chain_chan, 626 &adc->chain_mode_buf, 627 &chain_scan_masks); 628 if (ret) 629 return ret; 630 631 ret = ad7944_chain_mode_init_msg(dev, adc, &chain_chan[0], 632 n_chain_dev); 633 if (ret) 634 return ret; 635 636 break; 637 } 638 639 indio_dev->name = chip_info->name; 640 indio_dev->modes = INDIO_DIRECT_MODE; 641 indio_dev->info = &ad7944_iio_info; 642 643 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) { 644 indio_dev->available_scan_masks = chain_scan_masks; 645 indio_dev->channels = chain_chan; 646 indio_dev->num_channels = n_chain_dev + 1; 647 } else { 648 indio_dev->channels = chip_info->channels; 649 indio_dev->num_channels = ARRAY_SIZE(chip_info->channels); 650 } 651 652 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 653 iio_pollfunc_store_time, 654 ad7944_trigger_handler, NULL); 655 if (ret) 656 return ret; 657 658 return devm_iio_device_register(dev, indio_dev); 659} 660 661static const struct of_device_id ad7944_of_match[] = { 662 { .compatible = "adi,ad7944", .data = &ad7944_chip_info }, 663 { .compatible = "adi,ad7985", .data = &ad7985_chip_info }, 664 { .compatible = "adi,ad7986", .data = &ad7986_chip_info }, 665 { } 666}; 667MODULE_DEVICE_TABLE(of, ad7944_of_match); 668 669static const struct spi_device_id ad7944_spi_id[] = { 670 { "ad7944", (kernel_ulong_t)&ad7944_chip_info }, 671 { "ad7985", (kernel_ulong_t)&ad7985_chip_info }, 672 { "ad7986", (kernel_ulong_t)&ad7986_chip_info }, 673 { } 674 675}; 676MODULE_DEVICE_TABLE(spi, ad7944_spi_id); 677 678static struct spi_driver ad7944_driver = { 679 .driver = { 680 .name = "ad7944", 681 .of_match_table = ad7944_of_match, 682 }, 683 .probe = ad7944_probe, 684 .id_table = ad7944_spi_id, 685}; 686module_spi_driver(ad7944_driver); 687 688MODULE_AUTHOR("David Lechner <dlechner@baylibre.com>"); 689MODULE_DESCRIPTION("Analog Devices AD7944 PulSAR ADC family driver"); 690MODULE_LICENSE("GPL"); 691